source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S @ 95273a6

4.104.114.84.95
Last change on this file since 95273a6 was 95273a6, checked in by Joel Sherrill <joel.sherrill@…>, on 01/03/00 at 14:06:42

Combination of coverhd.h cleanup and MVME23xx/MCP750 patch from Eric Valette
<valette@…> and Jay Kulpinski <jskulpin@…>.

  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*
2 *  mmuAsm.S
3 *
4 *  $Id$
5 *
6 *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
7 *
8 *  This file contains the low-level support for various MMU
9 *  features.
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *     
15 */
16
17#include <libcpu/cpu.h>
18#include <libcpu/io.h>
19#include <rtems/score/targopts.h>
20#include "asm.h"
21
22/*
23 * Each setdbat routine start by invalidating the DBAT as some
24 * proc (604e) request the valid bit set to 0 before accepting
25 * to write in BAT
26 */
27
28        .globl  asm_setdbat1
29        .type   asm_setdbat1,@function
30asm_setdbat1:
31        li      r20,0
32        SYNC
33        mtspr   DBAT1U,r20
34        mtspr   DBAT1L,r20
35        SYNC
36        mtspr DBAT1L, r4
37        mtspr DBAT1U, r3
38        SYNC
39        blr
40
41        .globl  asm_setdbat2
42        .type   asm_setdbat2,@function
43asm_setdbat2:   
44        li      r20,0
45        SYNC
46        mtspr   DBAT2U,r20
47        mtspr   DBAT2L,r20
48        SYNC
49        mtspr DBAT2L, r4
50        mtspr DBAT2U, r3
51        SYNC
52        blr
53
54        .globl  asm_setdbat3
55        .type   asm_setdbat3,@function
56asm_setdbat3:   
57        li      r20,0
58        SYNC
59        mtspr   DBAT3U,r20
60        mtspr   DBAT3L,r20
61        SYNC
62        mtspr DBAT3L, r4
63        mtspr DBAT3U, r3
64        SYNC
65        blr
66               
67        .globl L1_caches_enables
68        .type  L1_caches_enables, @function
69       
70L1_caches_enables:     
71        /*
72         * Enable caches and 604-specific features if necessary.
73         */
74        mfspr   r9,PVR
75        rlwinm  r9,r9,16,16,31
76        cmpi    0,r9,1
77        beq     4f                      /* not needed for 601 */
78        mfspr   r11,HID0
79        andi.   r0,r11,HID0_DCE
80        ori     r11,r11,HID0_ICE|HID0_DCE
81        ori     r8,r11,HID0_ICFI
82        bne     3f                      /* don't invalidate the D-cache */
83        ori     r8,r8,HID0_DCI          /* unless it wasn't enabled */
843:
85        sync
86        mtspr   HID0,r8                 /* enable and invalidate caches */
87        sync
88        mtspr   HID0,r11                /* enable caches */
89        sync
90        isync
91        cmpi    0,r9,4                  /* check for 604 */
92        cmpi    1,r9,9                  /* or 604e */
93        cmpi    2,r9,10                 /* or mach5 */
94        cror    2,2,6
95        cror    2,2,10
96        bne     4f
97        ori     r11,r11,HID0_SIED|HID0_BHTE /* for 604[e], enable */
98        bne     2,5f
99        ori     r11,r11,HID0_BTCD
1005:      mtspr   HID0,r11                /* superscalar exec & br history tbl */
1014:
102        blr
103       
104        .globl get_L2CR
105        .type  get_L2CR, @function     
106get_L2CR:       
107        /* Make sure this is a 750 chip */
108        mfspr   r3,PVR
109        rlwinm  r3,r3,16,16,31
110        cmplwi  r3,0x0008
111        li      r3,0
112        bnelr
113       
114        /* Return the L2CR contents */
115        mfspr   r3,L2CR
116        blr
117
118        .globl set_L2CR
119        .type  set_L2CR, @function
120set_L2CR:       
121        /* Usage:
122         * When setting the L2CR register, you must do a few special things. 
123         * If you are enabling the cache, you must perform a global invalidate.
124         * If you are disabling the cache, you must flush the cache contents first.
125         * This routine takes care of doing these things.  When first
126         * enabling the cache, make sure you pass in the L2CR you want, as well as
127         * passing in the global invalidate bit set.  A global invalidate will
128         * only be performed if the L2I bit is set in applyThis.  When enabling
129         * the cache, you should also set the L2E bit in applyThis.  If you
130         * want to modify the L2CR contents after the cache has been enabled,
131         * the recommended procedure is to first call __setL2CR(0) to disable
132         * the cache and then call it again with the new values for L2CR.  Examples:
133         *
134         *      _setL2CR(0)             -       disables the cache
135         *      _setL2CR(0xb9A14000)    -       enables my G3 MCP750 card:
136         *                              -       L2E set to turn on the cache
137         *                              -       L2SIZ set to 1MB
138         *                              -       L2CLK set to %2
139         *                              -       L2RAM set to pipelined syncronous late-write
140         *                              -       L2I set to perform a global invalidation
141         *                              -       L2OH set to 1 nS
142         *
143         * A similar call should work for your card.  You need to know the correct
144         * setting for your card and then place them in the fields I have outlined
145         * above.  Other fields support optional features, such as L2DO which caches
146         * only data, or L2TS which causes cache pushes from the L1 cache to go to
147         *the L2 cache instead of to main memory.
148         */
149       
150        /* Make sure this is a 750 chip */
151        mfspr   r4,PVR
152        rlwinm  r4,r4,16,16,31
153        cmplwi  r4,0x0008
154        beq     thisIs750
155        li      r3,-1
156        blr
157       
158thisIs750:
159        /* Get the current enable bit of the L2CR into r4 */
160        mfspr   r4,L2CR
161        rlwinm  r4,r4,0,0,0
162       
163        /* See if we want to perform a global inval this time. */
164        rlwinm  r6,r3,0,10,10           /* r6 contains the new invalidate bit */
165        rlwinm. r5,r3,0,0,0             /* r5 contains the new enable bit */
166        rlwinm  r3,r3,0,11,9            /* Turn off the invalidate bit */
167        rlwinm  r3,r3,0,1,31            /* Turn off the enable bit */
168        or      r3,r3,r4                /* Keep the enable bit the same as it was for now. */
169        bne     dontDisableCache        /* Only disable the cache if L2CRApply has the enable bit off */
170
171disableCache:
172        /* Disable the cache.  First, we turn off data relocation. */
173        mfmsr   r7
174        rlwinm  r4,r7,0,28,26           /* Turn off DR bit */
175        rlwinm  r4,r4,0,17,15           /* Turn off EE bit - an external exception while we are flushing
176                                           the cache is fatal (comment this line and see!) */
177        sync
178        mtmsr   r4
179        sync
180       
181        /*
182                Now, read the first 2MB of memory to put new data in the cache.
183                (Actually we only need the size of the L2 cache plus
184                the size of the L1 cache, but 2MB will cover everything just to be safe).
185        */
186        lis     r4,0x0001
187        mtctr   r4
188        li      r4,0
189loadLoop:
190        lwzx    r0,r0,r4
191        addi    r4,r4,0x0020            /* Go to start of next cache line */
192        bdnz    loadLoop
193       
194        /* Now, flush the first 2MB of memory */
195        lis     r4,0x0001
196        mtctr   r4
197        li      r4,0
198        sync
199flushLoop:
200        dcbf    r0,r4
201        addi    r4,r4,0x0020    /* Go to start of next cache line */
202        bdnz    flushLoop
203       
204        /* Turn off the L2CR enable bit. */
205        rlwinm  r3,r3,0,1,31
206       
207        /* Reenable data relocation. */
208        sync
209        mtmsr   r7
210        sync
211       
212dontDisableCache:
213        /* Set up the L2CR configuration bits */
214        sync
215        mtspr   L2CR,r3
216        sync
217        cmplwi  r6,0
218        beq     noInval
219       
220        /* Perform a global invalidation */
221        oris    r3,r3,0x0020
222        sync
223        mtspr   1017,r3
224        sync
225invalCompleteLoop:                      /* Wait for the invalidation to complete */
226        mfspr   r3,1017
227        rlwinm. r4,r3,0,31,31
228        bne     invalCompleteLoop
229       
230        rlwinm  r3,r3,0,11,9;           /* Turn off the L2I bit */
231        sync
232        mtspr   L2CR,r3
233        sync
234       
235noInval:
236        /* See if we need to enable the cache */
237        cmplwi  r5,0
238        beqlr
239       
240enableCache:
241        /* Enable the cache */
242        oris    r3,r3,0x8000
243        mtspr   L2CR,r3
244        sync
245        blr
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