1 | /* |
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2 | * mmuAsm.S |
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3 | * |
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4 | * $Id$ |
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5 | * |
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6 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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7 | * |
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8 | * This file contains the low-level support for various MMU |
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9 | * features. |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.com/license/LICENSE. |
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14 | * |
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15 | * T. Straumann - 11/2001: added support for 7400 (no AltiVec yet) |
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16 | * S.K. Feng - 10/2003: added support for 7455 (no AltiVec yet) |
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17 | * |
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18 | */ |
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19 | |
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20 | #include <rtems/asm.h> |
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21 | #include <rtems/score/cpu.h> |
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22 | #include <libcpu/io.h> |
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23 | |
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24 | /* Unfortunately, the CPU types defined in cpu.h are |
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25 | * an 'enum' type and hence not available :-( |
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26 | */ |
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27 | #define PPC_601 0x1 |
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28 | #define PPC_603 0x3 |
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29 | #define PPC_604 0x4 |
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30 | #define PPC_603e 0x6 |
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31 | #define PPC_603ev 0x7 |
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32 | #define PPC_750 0x8 |
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33 | #define PPC_604e 0x9 |
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34 | #define PPC_604r 0xA |
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35 | #define PPC_7400 0xC |
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36 | #define PPC_7455 0x8001 |
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37 | #define PPC_620 0x16 |
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38 | #define PPC_860 0x50 |
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39 | #define PPC_821 PPC_860 |
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40 | #define PPC_8260 0x81 |
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41 | |
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42 | /* ALTIVEC instructions (not recognized by off-the shelf gcc yet) */ |
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43 | #define DSSALL .long 0x7e00066c /* DSSALL altivec instruction opcode */ |
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44 | |
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45 | /* A couple of defines to make the code more readable */ |
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46 | #define CACHE_LINE_SIZE 32 |
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47 | |
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48 | #ifndef MSSCR0 |
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49 | #define MSSCR0 1014 |
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50 | #else |
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51 | #warning MSSCR0 seems to be known, update __FILE__ |
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52 | #endif |
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53 | |
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54 | #define DL1HWF (1<<(31-8)) |
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55 | #define L2HWF (1<<(31-20)) |
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56 | |
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57 | /* |
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58 | * Each setdbat routine start by invalidating the DBAT as some |
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59 | * proc (604e) request the valid bit set to 0 before accepting |
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60 | * to write in BAT |
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61 | */ |
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62 | |
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63 | .globl asm_setdbat0 |
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64 | .type asm_setdbat0,@function |
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65 | asm_setdbat0: |
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66 | li r0,0 |
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67 | sync |
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68 | isync |
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69 | mtspr DBAT0U,r0 |
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70 | mtspr DBAT0L,r0 |
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71 | sync |
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72 | isync |
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73 | mtspr DBAT0L, r4 |
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74 | mtspr DBAT0U, r3 |
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75 | sync |
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76 | isync |
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77 | blr |
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78 | |
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79 | .globl asm_setdbat1 |
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80 | .type asm_setdbat1,@function |
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81 | asm_setdbat1: |
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82 | li r0,0 |
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83 | sync |
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84 | isync |
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85 | mtspr DBAT1U,r0 |
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86 | mtspr DBAT1L,r0 |
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87 | sync |
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88 | isync |
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89 | mtspr DBAT1L, r4 |
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90 | mtspr DBAT1U, r3 |
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91 | sync |
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92 | isync |
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93 | blr |
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94 | |
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95 | .globl asm_setdbat2 |
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96 | .type asm_setdbat2,@function |
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97 | asm_setdbat2: |
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98 | li r0,0 |
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99 | sync |
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100 | isync |
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101 | mtspr DBAT2U,r0 |
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102 | mtspr DBAT2L,r0 |
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103 | sync |
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104 | isync |
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105 | mtspr DBAT2L, r4 |
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106 | mtspr DBAT2U, r3 |
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107 | sync |
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108 | isync |
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109 | blr |
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110 | |
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111 | .globl asm_setdbat3 |
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112 | .type asm_setdbat3,@function |
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113 | asm_setdbat3: |
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114 | li r0,0 |
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115 | sync |
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116 | isync |
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117 | mtspr DBAT3U,r0 |
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118 | mtspr DBAT3L,r0 |
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119 | sync |
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120 | isync |
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121 | mtspr DBAT3L, r4 |
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122 | mtspr DBAT3U, r3 |
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123 | sync |
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124 | isync |
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125 | blr |
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126 | |
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127 | .globl L1_caches_enables |
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128 | .type L1_caches_enables, @function |
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129 | |
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130 | L1_caches_enables: |
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131 | /* |
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132 | * Enable caches and 604-specific features if necessary. |
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133 | */ |
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134 | mfspr r9,PVR |
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135 | rlwinm r9,r9,16,16,31 |
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136 | cmpi 0,r9,PPC_601 |
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137 | beq 4f /* not needed for 601 */ |
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138 | mfspr r11,HID0 |
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139 | andi. r0,r11,HID0_DCE |
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140 | ori r11,r11,HID0_ICE|HID0_DCE |
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141 | ori r8,r11,HID0_ICFI |
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142 | bne 3f /* don't invalidate the D-cache */ |
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143 | ori r8,r8,HID0_DCI /* unless it wasn't enabled */ |
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144 | 3: |
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145 | sync |
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146 | mtspr HID0,r8 /* enable and invalidate caches */ |
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147 | sync |
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148 | mtspr HID0,r11 /* enable caches */ |
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149 | sync |
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150 | isync |
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151 | cmpi 1,r9,PPC_604 /* check for 604 */ |
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152 | cmpi 2,r9,PPC_604e /* or 604e */ |
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153 | cmpi 3,r9,PPC_604r /* or mach5 */ |
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154 | cror 6,6,10 |
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155 | cror 6,6,14 |
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156 | cmpi 2,r9,PPC_750 /* or 750 */ |
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157 | cror 6,6,10 |
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158 | cmpi 2,r9,PPC_7400 /* or 7400 */ |
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159 | cror 6,6,10 |
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160 | cmpli 0,r9,PPC_7455 /* or 7455 */ |
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161 | bne 2f |
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162 | /* 7455:link register stack,branch folding & |
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163 | * TBEN : enable the time base and decrementer. |
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164 | * EMCP bit is defined in HID1. However, it's not used |
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165 | * in mvme5500 board because of GT64260 (e.g. it's connected |
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166 | * pull-up). |
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167 | */ |
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168 | oris r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@h |
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169 | ori r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@l |
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170 | 2: cror 2,2,10 |
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171 | bne 3f |
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172 | ori r11,r11,HID0_BTIC /* enable branch tgt cache on 7400 & 7455 */ |
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173 | 3: cror 2,2,6 |
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174 | bne 4f |
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175 | /* on 7400 SIED is actually SGE (store gathering enable) */ |
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176 | ori r11,r11,HID0_SIED|HID0_BHTE /* for 604[e], enable */ |
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177 | bne 2,5f |
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178 | ori r11,r11,HID0_BTCD |
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179 | 5: mtspr HID0,r11 /* superscalar exec & br history tbl */ |
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180 | sync /* for SGE bit */ |
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181 | isync /* P2-17 to 2-22 in MPC7450UM */ |
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182 | 4: |
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183 | blr |
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184 | |
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185 | .globl get_L1CR |
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186 | .type get_L1CR, @function |
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187 | get_L1CR: |
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188 | mfspr r3,HID0 |
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189 | blr |
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190 | |
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191 | .globl get_L2CR |
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192 | .type get_L2CR, @function |
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193 | get_L2CR: |
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194 | /* Make sure this is a > 750 chip */ |
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195 | mfspr r3,PVR |
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196 | rlwinm r3,r3,16,16,31 |
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197 | cmplwi r3,PPC_750 /* it's a 750 */ |
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198 | beq 1f |
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199 | cmplwi r3,PPC_7400 /* it's a 7400 */ |
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200 | beq 1f |
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201 | cmplwi r3,PPC_7455 /* it's a 7455 */ |
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202 | beq 1f |
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203 | li r3,-1 |
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204 | blr |
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205 | |
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206 | 1: |
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207 | /* Return the L2CR contents */ |
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208 | mfspr r3,L2CR |
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209 | blr |
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210 | |
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211 | .globl set_L2CR |
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212 | .type set_L2CR, @function |
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213 | set_L2CR: |
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214 | /* Usage: |
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215 | * When setting the L2CR register, you must do a few special things. |
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216 | * If you are enabling the cache, you must perform a global invalidate. |
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217 | * If you are disabling the cache, you must flush the cache contents first. |
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218 | * This routine takes care of doing these things. When first |
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219 | * enabling the cache, make sure you pass in the L2CR you want, as well as |
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220 | * passing in the global invalidate bit set. A global invalidate will |
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221 | * only be performed if the L2I bit is set in applyThis. When enabling |
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222 | * the cache, you should also set the L2E bit in applyThis. If you |
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223 | * want to modify the L2CR contents after the cache has been enabled, |
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224 | * the recommended procedure is to first call __setL2CR(0) to disable |
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225 | * the cache and then call it again with the new values for L2CR. Examples: |
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226 | * |
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227 | * _setL2CR(0) - disables the cache |
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228 | * _setL2CR(0xb9A14000) - enables my G3 MCP750 card: |
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229 | * - L2E set to turn on the cache |
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230 | * - L2SIZ set to 1MB |
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231 | * - L2CLK set to %2 |
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232 | * - L2RAM set to pipelined syncronous late-write |
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233 | * - L2I set to perform a global invalidation |
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234 | * - L2OH set to 1 nS |
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235 | * |
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236 | * A similar call should work for your card. You need to know the correct |
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237 | * setting for your card and then place them in the fields I have outlined |
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238 | * above. Other fields support optional features, such as L2DO which caches |
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239 | * only data, or L2TS which causes cache pushes from the L1 cache to go to |
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240 | *the L2 cache instead of to main memory. |
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241 | */ |
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242 | |
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243 | /* Make sure this is a > 750 chip */ |
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244 | mfspr r0,PVR |
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245 | rlwinm r0,r0,16,16,31 |
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246 | cmplwi r0,PPC_750 |
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247 | beq thisIs750 |
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248 | cmplwi r0,PPC_7400 |
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249 | beq thisIs750 |
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250 | cmplwi r0,PPC_7455 |
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251 | beq thisIs750 |
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252 | li r3,-1 |
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253 | blr |
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254 | |
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255 | thisIs750: |
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256 | /* Get the current enable bit of the L2CR into r4 */ |
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257 | mfspr r4,L2CR |
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258 | rlwinm r4,r4,0,0,0 |
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259 | |
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260 | /* See if we want to perform a global inval this time. */ |
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261 | rlwinm r6,r3,0,10,10 /* r6 contains the new invalidate bit */ |
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262 | rlwinm. r5,r3,0,0,0 /* r5 contains the new enable bit */ |
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263 | rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */ |
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264 | rlwinm r3,r3,0,1,31 /* Turn off the enable bit */ |
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265 | or r3,r3,r4 /* Keep the enable bit the same as it was for now. */ |
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266 | mfmsr r7 /* shut off interrupts around critical flush/invalidate sections */ |
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267 | rlwinm r4,r7,0,17,15 /* Turn off EE bit - an external exception while we are flushing |
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268 | the cache is fatal (comment this line and see!) */ |
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269 | mtmsr r4 |
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270 | bne dontDisableCache /* Only disable the cache if L2CRApply has the enable bit off */ |
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271 | |
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272 | cmplwi r0,PPC_7400 /* 7400 ? */ |
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273 | bne disableCache /* use traditional method */ |
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274 | |
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275 | /* On the 7400, they recommend using the hardware flush feature */ |
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276 | DSSALL /* stop all data streams */ |
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277 | sync |
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278 | /* we wouldn't have to flush L1, but for sake of consistency with the other code we do it anyway */ |
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279 | mfspr r4, MSSCR0 |
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280 | oris r4, r4, DL1HWF@h |
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281 | mtspr MSSCR0, r4 |
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282 | sync |
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283 | /* L1 flushed */ |
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284 | mfspr r4, L2CR |
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285 | ori r4, r4, L2HWF |
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286 | mtspr L2CR, r4 |
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287 | sync |
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288 | /* L2 flushed */ |
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289 | b flushDone |
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290 | |
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291 | disableCache: |
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292 | /* Disable the cache. First, we turn off data relocation. */ |
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293 | rlwinm r4,r4,0,28,26 /* Turn off DR bit */ |
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294 | mtmsr r4 |
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295 | isync /* make sure memory accesses have completed */ |
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296 | cmplwi r0,PPC_7455 /* 7455 ? */ |
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297 | bne not745x |
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298 | /* 7455:L1 Load/Flush, L2, L3 : hardware flush */ |
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299 | /* If not using AltiVec data streaming instructions,DSSALL not necessary */ |
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300 | sync |
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301 | mfspr r4, MSSCR0 |
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302 | rlwinm r4,r4,0,29,0 /* Turn off the L2PFE bits */ |
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303 | mtspr MSSCR0, r4 |
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304 | sync |
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305 | /* flush L1 first */ |
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306 | lis r4,0x0001 |
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307 | mtctr r4 |
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308 | li r4,0 |
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309 | li r0,0 |
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310 | loadFlush: |
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311 | lwzx r0,r0,r4 |
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312 | dcbf r0,r4 |
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313 | addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ |
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314 | bdnz loadFlush |
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315 | sync |
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316 | /* Set the L2CR[L2IO & L2DO] bits to completely lock the L2 cache */ |
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317 | mfspr r0, L2CR |
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318 | lis r4,L2CR_LOCK_745x@h |
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319 | ori r4,r4,L2CR_LOCK_745x@l |
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320 | or r4,r0,r4 |
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321 | rlwinm r4,r4,0,11,9 /* make sure the invalidate bit off */ |
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322 | mtspr L2CR, r4 |
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323 | sync |
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324 | ori r4, r4, L2HWF |
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325 | mtspr L2CR, r4 |
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326 | sync |
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327 | /* L2 flushed,L2IO & L2DO got cleared in the dontDisableCache: */ |
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328 | b reenableDR |
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329 | |
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330 | not745x: |
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331 | /* |
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332 | Now, read the first 2MB of memory to put new data in the cache. |
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333 | (Actually we only need the size of the L2 cache plus |
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334 | the size of the L1 cache, but 2MB will cover everything just to be safe). |
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335 | */ |
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336 | lis r4,0x0001 |
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337 | mtctr r4 |
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338 | li r4,0 |
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339 | loadLoop: |
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340 | lwzx r0,r0,r4 |
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341 | addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ |
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342 | bdnz loadLoop |
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343 | |
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344 | /* Now, flush the first 2MB of memory */ |
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345 | lis r4,0x0001 |
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346 | mtctr r4 |
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347 | li r4,0 |
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348 | sync |
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349 | flushLoop: |
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350 | dcbf r0,r4 |
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351 | addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ |
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352 | bdnz flushLoop |
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353 | sync |
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354 | reenableDR: |
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355 | rlwinm r4,r7,0,17,15 /* still mask EE but reenable data relocation */ |
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356 | mtmsr r4 |
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357 | isync |
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358 | |
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359 | flushDone: |
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360 | |
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361 | /* Turn off the L2CR enable bit. */ |
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362 | rlwinm r3,r3,0,1,31 |
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363 | |
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364 | dontDisableCache: |
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365 | /* Set up the L2CR configuration bits */ |
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366 | sync |
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367 | mtspr L2CR,r3 |
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368 | sync |
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369 | cmplwi r6,0 |
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370 | beq noInval |
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371 | |
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372 | /* Perform a global invalidation */ |
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373 | oris r3,r3,0x0020 |
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374 | sync |
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375 | mtspr L2CR,r3 |
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376 | sync |
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377 | invalCompleteLoop: /* Wait for the invalidation to complete */ |
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378 | mfspr r3,L2CR |
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379 | rlwinm. r4,r3,0,31,31 |
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380 | bne invalCompleteLoop |
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381 | |
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382 | rlwinm r3,r3,0,11,9; /* Turn off the L2I bit */ |
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383 | sync |
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384 | mtspr L2CR,r3 |
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385 | sync |
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386 | |
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387 | noInval: |
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388 | /* re-enable interrupts, i.e. restore original MSR */ |
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389 | mtmsr r7 /* (no sync needed) */ |
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390 | /* See if we need to enable the cache */ |
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391 | cmplwi r5,0 |
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392 | beqlr |
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393 | |
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394 | enableCache: |
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395 | /* Enable the cache */ |
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396 | oris r3,r3,0x8000 |
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397 | mtspr L2CR,r3 |
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398 | sync |
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399 | blr |
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400 | |
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401 | |
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402 | .globl get_L3CR |
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403 | .type get_L3CR, @function |
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404 | get_L3CR: |
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405 | /* Make sure this is a 7455 chip */ |
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406 | mfspr r3,PVR |
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407 | rlwinm r3,r3,16,16,31 |
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408 | cmplwi r3,PPC_7455 /* it's a 7455 */ |
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409 | beq 1f |
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410 | li r3,-1 |
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411 | blr |
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412 | |
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413 | 1: |
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414 | /* Return the L3CR contents */ |
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415 | mfspr r3,L3CR |
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416 | blr |
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417 | |
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418 | .globl set_L3CR |
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419 | .type set_L3CR, @function |
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420 | set_L3CR: |
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421 | /* Usage: |
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422 | * When setting the L3CR register, you must do a few special things. |
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423 | * If you are enabling the cache, you must perform a global invalidate. |
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424 | * Then call cpu_enable_l3cr(l3cr). |
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425 | * If you are disabling the cache, you must flush the cache contents first. |
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426 | * This routine takes care of doing these things. If you |
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427 | * want to modify the L3CR contents after the cache has been enabled, |
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428 | * the recommended procedure is to first call __setL3CR(0) to disable |
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429 | * the cache and then call cpu_enable_l3cr with the new values for |
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430 | * L3CR. |
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431 | */ |
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432 | |
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433 | /* Make sure this is a 7455 chip */ |
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434 | mfspr r0,PVR |
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435 | rlwinm r0,r0,16,16,31 |
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436 | cmplwi r0,PPC_7455 |
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437 | beq thisIs7455 |
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438 | li r3,-1 |
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439 | blr |
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440 | |
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441 | thisIs7455: |
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442 | /* Get the current enable bit of the L3CR into r4 */ |
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443 | mfspr r4,L3CR |
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444 | rlwinm r4,r4,0,0,0 |
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445 | |
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446 | /* See if we want to perform a global inval this time. */ |
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447 | rlwinm r6,r3,0,10,10 /* r6 contains the new invalidate bit */ |
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448 | rlwinm. r5,r3,0,0,0 /* r5 contains the new enable bit */ |
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449 | rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */ |
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450 | rlwinm r3,r3,0,1,31 /* Turn off the enable bit */ |
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451 | or r3,r3,r4 /* Keep the enable bit the same as it was for now. */ |
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452 | mfmsr r7 /* shut off interrupts around critical flush/invalidate sections */ |
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453 | rlwinm r4,r7,0,17,15 /* Turn off EE bit - an external exception while we are flushing |
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454 | the cache is fatal (comment this line and see!) */ |
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455 | mtmsr r4 |
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456 | bne dontDisableL3Cache /* Only disable the cache if L3CRApply has the enable bit off */ |
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457 | /* Before the L3 is disabled, it must be flused to prevent coherency problems */ |
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458 | /* First, we turn off data relocation. */ |
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459 | rlwinm r4,r4,0,28,26 /* Turn off DR bit */ |
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460 | mtmsr r4 |
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461 | isync /* make sure memory accesses have completed */ |
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462 | /* 7455: L3 : hardware flush |
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463 | * Set the L3CR[L3IO & L3DO] bits to completely lock the L3 cache */ |
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464 | mfspr r0, L3CR |
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465 | lis r4, L3CR_LOCK_745x@h |
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466 | ori r4,r4, L3CR_LOCK_745x@l |
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467 | or r4,r0,r4 |
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468 | rlwinm r4,r4,0,11,9 /* make sure the invalidate bit off */ |
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469 | mtspr L3CR, r4 |
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470 | sync |
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471 | ori r4, r4, L3CR_L3HWF |
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472 | mtspr L3CR, r4 |
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473 | sync |
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474 | /* L3 flushed,L3IO & L3DO got cleared in the dontDisableL3Cache: */ |
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475 | rlwinm r4,r7,0,17,15 /* still mask EE but reenable data relocation */ |
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476 | mtmsr r4 |
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477 | isync |
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478 | |
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479 | /* Turn off the L3CR enable bit. */ |
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480 | rlwinm r3,r3,0,1,31 |
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481 | |
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482 | dontDisableL3Cache: |
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483 | /* Set up the L3CR configuration bits */ |
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484 | sync |
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485 | mtspr L3CR,r3 |
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486 | sync |
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487 | ifL3Inval: |
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488 | cmplwi r6,0 |
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489 | beq noL3Inval |
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490 | |
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491 | /* Perform a global invalidation */ |
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492 | oris r3,r3,0x0020 |
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493 | sync |
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494 | mtspr L3CR,r3 |
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495 | sync |
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496 | invalCompleteL3: /* Wait for the invalidation to complete */ |
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497 | mfspr r3,L3CR |
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498 | rlwinm. r4,r3,0,31,31 |
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499 | bne invalCompleteL3 |
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500 | |
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501 | rlwinm r3,r3,0,11,9; /* Turn off the L3I bit */ |
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502 | sync |
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503 | mtspr L3CR,r3 |
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504 | sync |
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505 | |
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506 | noL3Inval: |
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507 | /* re-enable interrupts, i.e. restore original MSR */ |
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508 | mtmsr r7 /* (no sync needed) */ |
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509 | /* See if we need to enable the cache */ |
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510 | cmplwi r5,0 |
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511 | beqlr |
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512 | |
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513 | enableL3Cache: |
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514 | /* Enable the cache */ |
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515 | oris r3,r3,0x8000 |
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516 | mtspr L3CR,r3 |
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517 | sync |
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518 | blr |
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