source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c @ 0d776cd2

4.104.114.84.95
Last change on this file since 0d776cd2 was 0d776cd2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/14/02 at 16:56:44

2001-05-14 Till Straumann <strauman@…>

  • rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add the following:
    • support for the MPC74000 (AKA G4); there is no AltiVec? support yet, however.
    • the cache flushing assembly code uses hardware-flush on the G4. Also, a couple of hardcoded numerical values were replaced by more readable symbolic constants.
    • extended interrupt-disabled code section so enclose the entire cache flush/invalidate procedure (as recommended by the book). This is not (latency) critical as it is only used by init code but prevents possible corruption.
    • Trivial page table support as been added. (1:1 effective-virtual-physical address mapping which is only useful only on CPUs which feature hardware TLB replacement, e.g. >604. This allows for write-protecting memory regions, e.g. text/ro-data which makes catching corruptors a lot easier. It also frees one DBAT/IBAT and gives more flexibility for setting up address maps :-)
    • setdbat() allows changing BAT0 also (since the BSP may use a page table, BAT0 could be available...).
    • asm_setdbatX() violated the SVR ABI by using r20 as a scratch register; changed for r0
    • according to the book, a context synchronizing instruction is necessary prior to and after changing a DBAT -> isync added
  • Property mode set to 100644
File size: 1.9 KB
Line 
1/*
2 * bat.c
3 *
4 *          This file contains the implementation of C function to
5 *          Instanciate 60x/7xx ppc Block Address Translation (BAT) registers.
6 *          More detailled information can be found on motorola
7 *          site and more precisely in the following book :
8 *
9 *              MPC750
10 *              Risc Microporcessor User's Manual
11 *              Mtorola REF : MPC750UM/AD 8/97
12 *
13 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
14 *                     Canon Centre Recherche France.
15 *
16 *  The license and distribution terms for this file may be
17 *  found in found in the file LICENSE in this distribution or at
18 *  http://www.OARcorp.com/rtems/license.html.
19 *
20 * $Id$
21 */
22
23#include <libcpu/bat.h>
24
25typedef union {                 /* BAT register values to be loaded */
26        BAT             bat;
27        unsigned int    word[2];
28}ubat;
29
30typedef struct batrange {               /* stores address ranges mapped by BATs */
31        unsigned long start;
32        unsigned long limit;
33        unsigned long phys;
34}batrange;
35
36batrange bat_addrs[4];
37
38void setdbat(int bat_index, unsigned long virt, unsigned long phys,
39       unsigned int size, int flags)
40{
41  unsigned int bl;
42  int wimgxpp;
43  ubat bat;
44
45  bl = (size >> 17) - 1;
46  /* 603, 604, etc. */
47  wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
48                     | _PAGE_COHERENT | _PAGE_GUARDED);
49  wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
50  bat.word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
51  bat.word[1] = phys | wimgxpp;
52  if (flags & _PAGE_USER)
53    bat.bat.batu.vp = 1;
54  bat_addrs[bat_index].start = virt;
55  bat_addrs[bat_index].limit = virt + ((bl + 1) << 17) - 1;
56  bat_addrs[bat_index].phys = phys;
57  switch (bat_index) {
58  case 0 : asm_setdbat1(bat.word[0], bat.word[1]); break;
59  case 1 : asm_setdbat1(bat.word[0], bat.word[1]); break;
60  case 2 : asm_setdbat2(bat.word[0], bat.word[1]); break;
61  case 3 : asm_setdbat3(bat.word[0], bat.word[1]); break;
62  default: printk("bat.c : invalid BAT bat_index\n");
63  }
64}
65
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