source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c @ 0d776cd2

4.104.114.84.95
Last change on this file since 0d776cd2 was 0d776cd2, checked in by Joel Sherrill <joel.sherrill@…>, on May 14, 2002 at 4:56:44 PM

2001-05-14 Till Straumann <strauman@…>

  • rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add the following:
    • support for the MPC74000 (AKA G4); there is no AltiVec? support yet, however.
    • the cache flushing assembly code uses hardware-flush on the G4. Also, a couple of hardcoded numerical values were replaced by more readable symbolic constants.
    • extended interrupt-disabled code section so enclose the entire cache flush/invalidate procedure (as recommended by the book). This is not (latency) critical as it is only used by init code but prevents possible corruption.
    • Trivial page table support as been added. (1:1 effective-virtual-physical address mapping which is only useful only on CPUs which feature hardware TLB replacement, e.g. >604. This allows for write-protecting memory regions, e.g. text/ro-data which makes catching corruptors a lot easier. It also frees one DBAT/IBAT and gives more flexibility for setting up address maps :-)
    • setdbat() allows changing BAT0 also (since the BSP may use a page table, BAT0 could be available...).
    • asm_setdbatX() violated the SVR ABI by using r20 as a scratch register; changed for r0
    • according to the book, a context synchronizing instruction is necessary prior to and after changing a DBAT -> isync added
  • Property mode set to 100644
File size: 6.8 KB
Line 
1/*
2 * raw_exception.c  - This file contains implementation of C function to
3 *                    Instanciate 60x ppc primary exception entries.
4 *                    More detailled information can be found on motorola
5 *                    site and more precisely in the following book :
6 *
7 *                    MPC750
8 *                    Risc Microporcessor User's Manual
9 *                    Motorola REF : MPC750UM/AD 8/97
10 *
11 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
12 *                     Canon Centre Recherche France.
13 *
14 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
15 * to support 603, 603e, 604, 604e exceptions
16 *
17 *  The license and distribution terms for this file may be
18 *  found in found in the file LICENSE in this distribution or at
19 *  http://www.OARcorp.com/rtems/license.html.
20 *
21 * $Id$
22 */
23#include <rtems/system.h>
24#include <rtems/score/ppc.h>
25#include <rtems/system.h>
26#include <libcpu/raw_exception.h>
27#include <libcpu/cpuIdent.h>
28
29static rtems_raw_except_connect_data*           raw_except_table;
30static rtems_raw_except_connect_data            default_raw_except_entry;
31static rtems_raw_except_global_settings*        local_settings;
32
33int mpc750_vector_is_valid(rtems_vector vector)
34{
35  switch(vector) {
36  case ASM_RESET_VECTOR: /* fall through */
37  case ASM_MACH_VECTOR:
38  case ASM_PROT_VECTOR:
39  case ASM_ISI_VECTOR:
40  case ASM_EXT_VECTOR:
41  case ASM_ALIGN_VECTOR:
42  case ASM_PROG_VECTOR:
43  case ASM_FLOAT_VECTOR:
44  case ASM_DEC_VECTOR:
45  case ASM_SYS_VECTOR:
46  case ASM_TRACE_VECTOR:
47  case ASM_ADDR_VECTOR:
48  case ASM_SYSMGMT_VECTOR:
49  case ASM_ITM_VECTOR:
50    return 1;
51  default: return 0;
52  }
53}
54
55int mpc603_vector_is_valid(rtems_vector vector)
56{
57  switch(vector) {
58  case ASM_RESET_VECTOR: /* fall through */
59  case ASM_MACH_VECTOR:
60  case ASM_PROT_VECTOR:
61  case ASM_ISI_VECTOR:
62  case ASM_EXT_VECTOR:
63  case ASM_ALIGN_VECTOR:
64  case ASM_PROG_VECTOR:
65  case ASM_FLOAT_VECTOR:
66  case ASM_DEC_VECTOR:
67  case ASM_SYS_VECTOR:
68  case ASM_TRACE_VECTOR:
69    return 1;
70  case ASM_PERFMON_VECTOR:
71    return 0;
72  case ASM_IMISS_VECTOR: /* fall through */
73  case ASM_DLMISS_VECTOR:
74  case ASM_DSMISS_VECTOR:
75  case ASM_ADDR_VECTOR:
76  case ASM_SYSMGMT_VECTOR:
77    return 1;
78  case ASM_ITM_VECTOR:
79    return 0;
80  }
81  return 0;
82}
83
84int mpc604_vector_is_valid(rtems_vector vector)
85{
86  switch(vector) {
87  case ASM_RESET_VECTOR: /* fall through */
88  case ASM_MACH_VECTOR:
89  case ASM_PROT_VECTOR:
90  case ASM_ISI_VECTOR:
91  case ASM_EXT_VECTOR:
92  case ASM_ALIGN_VECTOR:
93  case ASM_PROG_VECTOR:
94  case ASM_FLOAT_VECTOR:
95  case ASM_DEC_VECTOR:
96  case ASM_SYS_VECTOR:
97  case ASM_TRACE_VECTOR:
98  case ASM_PERFMON_VECTOR:
99    return 1;
100  case ASM_IMISS_VECTOR: /* fall through */
101  case ASM_DLMISS_VECTOR:
102  case ASM_DSMISS_VECTOR:
103    return 0;
104  case ASM_ADDR_VECTOR: /* fall through */
105  case ASM_SYSMGMT_VECTOR:
106    return 1;
107  case ASM_ITM_VECTOR:
108    return 0;
109  }
110  return 0;
111}
112
113int mpc60x_vector_is_valid(rtems_vector vector)
114{
115     switch (current_ppc_cpu) {
116        case PPC_7400:
117        case PPC_750:
118            if (!mpc750_vector_is_valid(vector)) {
119                return 0;
120            }
121            break;
122        case PPC_604:
123        case PPC_604e:
124        case PPC_604r:
125            if (!mpc604_vector_is_valid(vector)) {
126                return 0;
127            }
128            break;
129        case PPC_603:
130        case PPC_603e:
131            if (!mpc603_vector_is_valid(vector)) {
132                return 0;
133            }
134            break;
135        default:
136            printk("Please complete libcpu/powerpc/mpc6xx/raw_exception.c\n");
137            printk("current_ppc_cpu = %x\n", current_ppc_cpu);
138            return 0;
139     }
140     return 1;
141}
142
143int mpc60x_set_exception  (const rtems_raw_except_connect_data* except)
144{
145    unsigned int level;
146
147    if (!mpc60x_vector_is_valid(except->exceptIndex)) {
148      return 0;
149    }
150    /*
151     * Check if default handler is actually connected. If not issue an error.
152     * You must first get the current handler via mpc60x_get_current_exception
153     * and then disconnect it using mpc60x_delete_exception.
154     * RATIONALE : to always have the same transition by forcing the user
155     * to get the previous handler before accepting to disconnect.
156     */
157    if (memcmp(mpc60x_get_vector_addr(except->exceptIndex), (void*)default_raw_except_entry.hdl.raw_hdl,default_raw_except_entry.hdl.raw_hdl_size)) {
158      return 0;
159    }
160
161    _CPU_ISR_Disable(level);
162   
163    raw_except_table [except->exceptIndex] = *except;
164    codemove((void*)mpc60x_get_vector_addr(except->exceptIndex),
165             except->hdl.raw_hdl,
166             except->hdl.raw_hdl_size,
167             PPC_CACHE_ALIGNMENT);
168    except->on(except);
169   
170    _CPU_ISR_Enable(level);
171    return 1;
172}
173
174int mpc60x_get_current_exception (rtems_raw_except_connect_data* except)
175{
176  if (!mpc60x_vector_is_valid(except->exceptIndex)){
177    return 0;
178  }
179   
180  *except = raw_except_table [except->exceptIndex];
181   
182  return 1;
183}
184
185int mpc60x_delete_exception (const rtems_raw_except_connect_data* except)
186{
187  unsigned int level;
188 
189  if (!mpc60x_vector_is_valid(except->exceptIndex)){
190    return 0;
191  }
192  /*
193   * Check if handler passed is actually connected. If not issue an error.
194   * You must first get the current handler via mpc60x_get_current_exception
195   * and then disconnect it using mpc60x_delete_exception.
196   * RATIONALE : to always have the same transition by forcing the user
197   * to get the previous handler before accepting to disconnect.
198   */
199  if (memcmp(mpc60x_get_vector_addr(except->exceptIndex),
200             (void*)except->hdl.raw_hdl,
201             except->hdl.raw_hdl_size)) {
202      return 0;
203  }
204  _CPU_ISR_Disable(level);
205
206  except->off(except);
207  codemove((void*)mpc60x_get_vector_addr(except->exceptIndex),
208           default_raw_except_entry.hdl.raw_hdl,
209           default_raw_except_entry.hdl.raw_hdl_size,
210           PPC_CACHE_ALIGNMENT);
211
212   
213  raw_except_table[except->exceptIndex] = default_raw_except_entry;
214  raw_except_table[except->exceptIndex].exceptIndex = except->exceptIndex;
215
216  _CPU_ISR_Enable(level);
217   
218  return 1;
219}
220
221/*
222 * Exception global init.
223 */
224int mpc60x_init_exceptions (rtems_raw_except_global_settings* config)
225{
226    unsigned                    i;
227    unsigned int level;
228   
229    /*
230     * store various accelerators
231     */
232    raw_except_table            = config->rawExceptHdlTbl;
233    local_settings              = config;
234    default_raw_except_entry    = config->defaultRawEntry;
235
236    _CPU_ISR_Disable(level);
237
238    for (i=0; i <= LAST_VALID_EXC; i++) {
239      if (!mpc60x_vector_is_valid(i)){
240        continue;
241      }
242      codemove((void*)mpc60x_get_vector_addr(i),
243             raw_except_table[i].hdl.raw_hdl,
244             raw_except_table[i].hdl.raw_hdl_size,
245             PPC_CACHE_ALIGNMENT);
246      if (raw_except_table[i].hdl.raw_hdl != default_raw_except_entry.hdl.raw_hdl) {
247        raw_except_table[i].on(&raw_except_table[i]);
248      }
249      else {
250        raw_except_table[i].off(&raw_except_table[i]);
251      }
252    }
253    _CPU_ISR_Enable(level);
254
255    return 1;
256}
257
258int mpc60x_get_exception_config (rtems_raw_except_global_settings** config)
259{
260  *config = local_settings;
261  return 1;
262}
263
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