source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S @ acc25ee

4.104.114.84.95
Last change on this file since acc25ee was acc25ee, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 2, 1999 at 2:31:19 PM

Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@…>.
As part of this effort, the mpc750 libcpu code is now shared with the
ppc6xx.

  • Property mode set to 100644
File size: 1.2 KB
Line 
1/*
2 *  asm_utils.s
3 *
4 *  $Id$
5 *
6 *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
7 *
8 *  This file contains the low-level support for moving exception
9 *  exception code to appropriate location.
10 *
11 */
12
13#include <libcpu/cpu.h>
14#include <libcpu/io.h>
15#include <rtems/score/targopts.h>
16#include "asm.h"
17
18        .globl  codemove
19codemove:
20        .type   codemove,@function
21/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
22        cmplw   cr1,r3,r4
23        addi    r0,r5,3
24        srwi.   r0,r0,2
25        beq     cr1,4f  /* In place copy is not necessary */
26        beq     7f      /* Protect against 0 count */
27        mtctr   r0
28        bge     cr1,2f
29       
30        la      r8,-4(r4)
31        la      r7,-4(r3)
321:      lwzu    r0,4(r8)
33        stwu    r0,4(r7)       
34        bdnz    1b
35        b       4f
36
372:      slwi    r0,r0,2
38        add     r8,r4,r0
39        add     r7,r3,r0
403:      lwzu    r0,-4(r8)
41        stwu    r0,-4(r7)
42        bdnz    3b
43       
44/* Now flush the cache: note that we must start from a cache aligned
45 * address. Otherwise we might miss one cache line.
46 */
474:      cmpwi   r6,0
48        add     r5,r3,r5
49        beq     7f      /* Always flush prefetch queue in any case */
50        subi    r0,r6,1
51        andc    r3,r3,r0
52        mr      r4,r3
535:      cmplw   r4,r5   
54        dcbst   0,r4
55        add     r4,r4,r6
56        blt     5b
57        sync            /* Wait for all dcbst to complete on bus */
58        mr      r4,r3
596:      cmplw   r4,r5   
60        icbi    0,r4
61        add     r4,r4,r6
62        blt     6b
637:      sync            /* Wait for all icbi to complete on bus */
64        isync
65        blr
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