source: rtems/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S @ 11c2382

4.104.114.84.95
Last change on this file since 11c2382 was 11c2382, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 1, 2004 at 10:07:38 AM

2004-04-01 Ralf Corsepius <ralf_corsepius@…>

  • mpc505/vectors/vectors.S: Include <rtems/asm.h> instead of <asm.h>.
  • mpc6xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>.
  • mpc6xx/mmu/mmuAsm.S: Include <rtems/asm.h> instead of <asm.h>.
  • mpc8260/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>.
  • mpc8xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>.
  • ppc403/vectors/vectors.S: Include <rtems/asm.h> instead of <asm.h>.
  • mpc5xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>.
  • mpc8260/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
  • mpc8xx/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
  • ppc403/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
  • Property mode set to 100644
File size: 1.2 KB
Line 
1/*
2 *  asm_utils.s
3 *
4 *  $Id$
5 *
6 *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
7 *
8 *  This file contains the low-level support for moving exception
9 *  exception code to appropriate location.
10 *
11 */
12
13#include <rtems/asm.h>
14#include <rtems/score/cpu.h>
15#include <libcpu/io.h>
16
17        .globl  codemove
18codemove:
19        .type   codemove,@function
20/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
21        cmplw   cr1,r3,r4
22        addi    r0,r5,3
23        srwi.   r0,r0,2
24        beq     cr1,4f  /* In place copy is not necessary */
25        beq     7f      /* Protect against 0 count */
26        mtctr   r0
27        bge     cr1,2f
28       
29        la      r8,-4(r4)
30        la      r7,-4(r3)
311:      lwzu    r0,4(r8)
32        stwu    r0,4(r7)       
33        bdnz    1b
34        b       4f
35
362:      slwi    r0,r0,2
37        add     r8,r4,r0
38        add     r7,r3,r0
393:      lwzu    r0,-4(r8)
40        stwu    r0,-4(r7)
41        bdnz    3b
42       
43/* Now flush the cache: note that we must start from a cache aligned
44 * address. Otherwise we might miss one cache line.
45 */
464:      cmpwi   r6,0
47        add     r5,r3,r5
48        beq     7f      /* Always flush prefetch queue in any case */
49        subi    r0,r6,1
50        andc    r3,r3,r0
51        mr      r4,r3
525:      cmplw   r4,r5   
53        dcbst   0,r4
54        add     r4,r4,r6
55        blt     5b
56        sync            /* Wait for all dcbst to complete on bus */
57        mr      r4,r3
586:      cmplw   r4,r5   
59        icbi    0,r4
60        add     r4,r4,r6
61        blt     6b
627:      sync            /* Wait for all icbi to complete on bus */
63        isync
64        blr
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