source: rtems/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h @ 73b5bd5d

4.104.114.84.95
Last change on this file since 73b5bd5d was 8430205, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 12, 2004 at 10:04:28 PM

2004-04-12 David Querbach <querbach@…>

  • README, configure.ac, mpc5xx/Makefile.am, mpc5xx/exceptions/raw_exception.c, mpc5xx/exceptions/raw_exception.h, mpc5xx/timer/timer.c, shared/include/cpuIdent.h: addition of a significant amount of MPC5xx support as part of the addition of the SS555 BSP.
  • mpc5xx/README, mpc5xx/clock/clock.c, mpc5xx/console-generic/console-generic.c, mpc5xx/include/console.h, mpc5xx/include/mpc5xx.h, mpc5xx/irq/irq.c, mpc5xx/irq/irq.h, mpc5xx/irq/irq_asm.S, mpc5xx/irq/irq_init.c, mpc5xx/vectors/vectors.S, mpc5xx/vectors/vectors.h, mpc5xx/vectors/vectors_init.c: New files.
  • mpc5xx/exceptions/asm_utils.S: Removed.
  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * vectors.h Exception frame related contant and API.
3 *
4 *  This include file describe the data structure and the functions implemented
5 *  by rtems to handle exceptions.
6 *
7 *
8 *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
9 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
10 *
11 *  Derived from libbsp/powerpc/mbx8xx/vectors/vectors.h:
12 *
13 *  CopyRight (C) 1999 valette@crf.canon.fr
14 *
15 *  The license and distribution terms for this file may be
16 *  found in found in the file LICENSE in this distribution or at
17 *  http://www.rtems.com/license/LICENSE.
18 *
19 *  $Id$
20 */
21#ifndef LIBCPU_POWERPC_MBX5XX_VECTORS_H
22#define LIBCPU_POWERPC_MBX5XX_VECTORS_H
23
24
25/*
26 * Size of hardware vector table.
27 */
28#define NUM_EXCEPTIONS          0x20
29
30/*
31 * The callee (high level exception code written in C)
32 * will store the Link Registers (return address) at entry r1 + 4 !!!.
33 * So let room for it!!!.
34 */ 
35#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
36#define SRR0_FRAME_OFFSET 8
37#define SRR1_FRAME_OFFSET 12
38#define EXCEPTION_NUMBER_OFFSET 16
39#define GPR0_OFFSET 20
40#define GPR1_OFFSET 24
41#define GPR2_OFFSET 28
42#define GPR3_OFFSET 32
43#define GPR4_OFFSET 36
44#define GPR5_OFFSET 40
45#define GPR6_OFFSET 44
46#define GPR7_OFFSET 48
47#define GPR8_OFFSET 52
48#define GPR9_OFFSET 56
49#define GPR10_OFFSET 60
50#define GPR11_OFFSET 64
51#define GPR12_OFFSET 68
52#define GPR13_OFFSET 72
53#define GPR14_OFFSET 76
54#define GPR15_OFFSET 80
55#define GPR16_OFFSET 84
56#define GPR17_OFFSET 88
57#define GPR18_OFFSET 92
58#define GPR19_OFFSET 96
59#define GPR20_OFFSET 100
60#define GPR21_OFFSET 104
61#define GPR22_OFFSET 108
62#define GPR23_OFFSET 112
63#define GPR24_OFFSET 116
64#define GPR25_OFFSET 120
65#define GPR26_OFFSET 124
66#define GPR27_OFFSET 128
67#define GPR28_OFFSET 132
68#define GPR29_OFFSET 136
69#define GPR30_OFFSET 140
70#define GPR31_OFFSET 144
71#define EXC_CR_OFFSET 148
72#define EXC_CTR_OFFSET 152
73#define EXC_XER_OFFSET 156
74#define EXC_LR_OFFSET 160
75#define EXC_DAR_OFFSET 164
76/*
77 * maintain the EABI requested 8 bytes aligment
78 * As SVR4 ABI requires 16, make it 16 (as some
79 * exception may need more registers to be processed...)
80 */
81#define    EXCEPTION_FRAME_END 176
82
83#ifndef ASM
84/*
85 * default raw exception handlers
86 */
87
88extern  void default_exception_vector_code_prolog();
89extern  int  default_exception_vector_code_prolog_size;
90extern  void initialize_exceptions();
91
92typedef struct {
93  unsigned      EXC_SRR0;
94  unsigned      EXC_SRR1;
95  unsigned      _EXC_number;
96  unsigned      GPR0;
97  unsigned      GPR1;
98  unsigned      GPR2;
99  unsigned      GPR3;
100  unsigned      GPR4;
101  unsigned      GPR5;
102  unsigned      GPR6;
103  unsigned      GPR7;
104  unsigned      GPR8;
105  unsigned      GPR9;
106  unsigned      GPR10;
107  unsigned      GPR11;
108  unsigned      GPR12;
109  unsigned      GPR13;
110  unsigned      GPR14;
111  unsigned      GPR15;
112  unsigned      GPR16;
113  unsigned      GPR17;
114  unsigned      GPR18;
115  unsigned      GPR19;
116  unsigned      GPR20;
117  unsigned      GPR21;
118  unsigned      GPR22;
119  unsigned      GPR23;
120  unsigned      GPR24;
121  unsigned      GPR25;
122  unsigned      GPR26;
123  unsigned      GPR27;
124  unsigned      GPR28;
125  unsigned      GPR29;
126  unsigned      GPR30;
127  unsigned      GPR31;
128  unsigned      EXC_CR;
129  unsigned      EXC_CTR;
130  unsigned      EXC_XER;
131  unsigned      EXC_LR;
132  unsigned      EXC_MSR;
133  unsigned      EXC_DAR;
134}CPU_Exception_frame;
135
136
137typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr);
138/*DEBUG typedef rtems_exception_handler_t cpuExcHandlerType; */
139
140/*
141 * Exception handler table.
142 *
143 * This table contains pointers to assembly-language exception handlers.
144 * The common exception prologue in vectors.S looks up an entry in this
145 * table and jumps to it.  No return address is saved, so the handlers in
146 * this table must return directly to the interrupted code.
147 *
148 * On entry to an exception handler, R1 points to a new exception stack
149 * frame in which R3, R4, and LR have been saved.  R4 holds the exception
150 * number.
151 */
152extern rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS];
153
154#endif /* ASM */
155
156#endif /* LIBCPU_POWERPC_MPC5XX_VECTORS_H */
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