1 | /* |
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2 | * vectors.S |
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3 | * |
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4 | * This file contains the assembly code for the PowerPC exception veneers |
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5 | * for RTEMS. |
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6 | * |
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7 | * |
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8 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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9 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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10 | * |
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11 | * Derived from libbsp/powerpc/mbx8xx/vectors/vectors.S, |
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12 | * |
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13 | * (c) 1999, Eric Valette valette@crf.canon.fr |
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14 | */ |
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15 | |
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16 | #include <rtems/asm.h> |
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17 | #include <rtems/score/cpu.h> |
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18 | #include <libcpu/vectors.h> |
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19 | |
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20 | #define SYNC \ |
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21 | sync; \ |
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22 | isync |
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23 | |
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24 | |
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25 | /* |
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26 | * Hardware exception vector table. |
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27 | * |
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28 | * The MPC555 can be configured to use a compressed vector table with 8 |
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29 | * bytes per entry, rather than the usual 0x100 bytes of other PowerPC |
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30 | * devices. The following macro uses this feature to save the better part |
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31 | * of 8 kbytes of flash ROM. |
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32 | * |
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33 | * Each vector table entry has room for only a simple branch instruction |
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34 | * which branches to a prologue specific to that exception. This |
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35 | * exception-specific prologue begins the context save, loads the exception |
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36 | * number into a register, and jumps to a common exception prologue, below. |
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37 | */ |
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38 | |
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39 | .macro vectors num=0, total=NUM_EXCEPTIONS /* create vector table */ |
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40 | |
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41 | /* vector table entry */ |
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42 | .section .vectors, "ax" |
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43 | |
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44 | ba specific_prologue\@ /* run specific prologue */ |
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45 | .long 0 /* each entry is 8 bytes */ |
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46 | |
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47 | /* exception-specific prologue */ |
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48 | .text |
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49 | |
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50 | specific_prologue\@: |
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51 | stwu r1, -EXCEPTION_FRAME_END(r1) /* open stack frame */ |
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52 | stw r4, GPR4_OFFSET(r1) /* preserve register */ |
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53 | li r4, \num /* get exception number */ |
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54 | b common_prologue /* run common prologue */ |
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55 | |
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56 | /* invoke macro recursively to create remainder of table */ |
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57 | .if \total - (\num + 1) |
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58 | vectors "(\num + 1)", \total |
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59 | .endif |
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60 | |
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61 | .endm |
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62 | |
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63 | |
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64 | /* invoke macro to create entire vector table */ |
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65 | vectors |
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66 | |
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67 | |
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68 | /* |
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69 | * Common exception prologue. |
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70 | * |
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71 | * Because the MPC555 vector table is in flash ROM, it's not possible to |
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72 | * change the exception handlers by overwriting them at run-time, so this |
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73 | * common exception prologue uses a table of exception handler pointers to |
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74 | * provide equivalent flexibility. |
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75 | * |
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76 | * When the actual exception handler is run, R1 points to the base of a new |
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77 | * exception stack frame, in which R3, R4 and LR have been saved. R4 holds |
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78 | * the exception number. |
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79 | */ |
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80 | .text |
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81 | |
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82 | common_prologue: |
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83 | stw r3, GPR3_OFFSET(r1) /* preserve registers */ |
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84 | mflr r3 |
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85 | stw r3, EXC_LR_OFFSET(r1) |
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86 | |
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87 | slwi r3, r4, 2 /* make table offset */ |
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88 | addis r3, r3, exception_handler_table@ha /* point to entry */ |
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89 | addi r3, r3, exception_handler_table@l |
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90 | lwz r3, 0(r3) /* get entry */ |
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91 | mtlr r3 /* run it */ |
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92 | blr |
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93 | |
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94 | |
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95 | /* |
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96 | * Default exception handler. |
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97 | * |
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98 | * The function initialize_exceptions() initializes all of the entries in |
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99 | * the exception handler table with pointers to this routine, which saves |
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100 | * the remainder of the interrupted code's state, then calls |
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101 | * C_default_exception_handler() to dump registers. |
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102 | * |
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103 | * On entry, R1 points to a new exception stack frame in which R3, R4, and |
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104 | * LR have been saved. R4 holds the exception number. |
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105 | */ |
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106 | .text |
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107 | |
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108 | PUBLIC_VAR(default_exception_handler) |
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109 | SYM (default_exception_handler): |
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110 | /* |
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111 | * Save the interrupted code's program counter and MSR. Beyond this |
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112 | * point, all exceptions are recoverable. Use an RCPU-specific SPR |
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113 | * to set the RI bit in the MSR to indicate the recoverable state. |
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114 | */ |
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115 | mfsrr0 r3 |
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116 | stw r3, SRR0_FRAME_OFFSET(r1) |
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117 | mfsrr1 r3 |
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118 | stw r3, SRR1_FRAME_OFFSET(r1) |
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119 | |
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120 | mtspr eid, r3 /* set MSR[RI], clear MSR[EE] */ |
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121 | SYNC |
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122 | |
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123 | /* |
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124 | * Save the remainder of the general-purpose registers. |
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125 | * |
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126 | * Compute the value of R1 at exception entry before storing it in |
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127 | * the frame. |
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128 | * |
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129 | * Note that R2 should never change (it's the EABI pointer to |
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130 | * .sdata2), but we save it just in case. |
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131 | * |
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132 | * Recall that R3 and R4 were saved by the specific- and |
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133 | * common-exception handlers before entry to this routine. |
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134 | */ |
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135 | stw r0, GPR0_OFFSET(r1) |
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136 | addi r0, r1, EXCEPTION_FRAME_END |
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137 | stw r0, GPR1_OFFSET(r1) |
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138 | stw r2, GPR2_OFFSET(r1) |
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139 | stmw r5, GPR5_OFFSET(r1) /* save R5 to R31 */ |
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140 | |
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141 | /* |
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142 | * Save the remainder of the UISA special-purpose registers. Recall |
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143 | * that LR was saved before entry. |
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144 | */ |
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145 | mfcr r0 |
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146 | stw r0, EXC_CR_OFFSET(r1) |
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147 | mfctr r0 |
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148 | stw r0, EXC_CTR_OFFSET(r1) |
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149 | mfxer r0 |
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150 | stw r0, EXC_XER_OFFSET(r1) |
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151 | |
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152 | /* |
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153 | * Call C-language portion of the default exception handler, passing |
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154 | * in the address of the frame. |
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155 | * |
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156 | * To simplify things a bit, we assume that the target routine is |
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157 | * within +/- 32 Mbyte from here, which is a reasonable assumption |
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158 | * on the MPC555. |
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159 | */ |
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160 | stw r4, EXCEPTION_NUMBER_OFFSET(r1) /* save exception number */ |
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161 | addi r3, r1, 0x8 /* get frame address */ |
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162 | bl C_default_exception_handler /* call handler */ |
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163 | |
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164 | /* |
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165 | * Restore UISA special-purpose registers. |
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166 | */ |
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167 | lwz r0, EXC_XER_OFFSET(r1) |
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168 | mtxer r0 |
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169 | lwz r0, EXC_CTR_OFFSET(r1) |
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170 | mtctr r0 |
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171 | lwz r0, EXC_CR_OFFSET(r1) |
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172 | mtcr r0 |
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173 | lwz r0, EXC_LR_OFFSET(r1) |
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174 | mtlr r0 |
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175 | |
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176 | /* |
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177 | * Restore most general-purpose registers. |
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178 | */ |
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179 | lmw r2, GPR2_OFFSET(r1) |
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180 | |
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181 | /* |
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182 | * Restore the interrupted code's program counter and MSR, but first |
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183 | * use an RCPU-specific special-purpose register to clear the RI |
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184 | * bit, indicating that exceptions are temporarily non-recoverable. |
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185 | */ |
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186 | mtspr nri, r0 /* clear MSR[RI] */ |
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187 | SYNC |
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188 | |
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189 | lwz r0, SRR1_FRAME_OFFSET(r1) |
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190 | mtsrr1 r0 |
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191 | lwz r0, SRR0_FRAME_OFFSET(r1) |
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192 | mtsrr0 r0 |
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193 | |
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194 | /* |
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195 | * Restore the final GPR, close the stack frame, and return to the |
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196 | * interrupted code. |
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197 | */ |
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198 | lwz r0, GPR0_OFFSET(r1) |
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199 | addi r1, r1, EXCEPTION_FRAME_END |
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200 | SYNC |
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201 | rfi |
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