source: rtems/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c @ 8430205

4.104.114.84.95
Last change on this file since 8430205 was 8430205, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 12, 2004 at 10:04:28 PM

2004-04-12 David Querbach <querbach@…>

  • README, configure.ac, mpc5xx/Makefile.am, mpc5xx/exceptions/raw_exception.c, mpc5xx/exceptions/raw_exception.h, mpc5xx/timer/timer.c, shared/include/cpuIdent.h: addition of a significant amount of MPC5xx support as part of the addition of the SS555 BSP.
  • mpc5xx/README, mpc5xx/clock/clock.c, mpc5xx/console-generic/console-generic.c, mpc5xx/include/console.h, mpc5xx/include/mpc5xx.h, mpc5xx/irq/irq.c, mpc5xx/irq/irq.h, mpc5xx/irq/irq_asm.S, mpc5xx/irq/irq_init.c, mpc5xx/vectors/vectors.S, mpc5xx/vectors/vectors.h, mpc5xx/vectors/vectors_init.c: New files.
  • mpc5xx/exceptions/asm_utils.S: Removed.
  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * irq_init.c
3 *
4 *  This file contains the implementation of rtems initialization
5 *  related to interrupt handling.
6 *
7 *
8 *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
9 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
10 *
11 *  Derived from libbsp/powerpc/mbx8xx/irq/irq_init.c:
12 *
13 *  CopyRight (C) 2001 valette@crf.canon.fr
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.com/license/LICENSE.
18 *
19 *  $Id$
20 */
21
22#include <rtems.h>
23#include <mpc5xx.h>
24#include <libcpu/vectors.h>
25#include <libcpu/raw_exception.h>
26#include <libcpu/irq.h>
27
28
29extern rtems_exception_handler_t dispatch_irq_handler;
30
31volatile unsigned int ppc_cached_irq_mask;
32
33/*
34 * default on/off function
35 */
36static void nop_func(){}
37
38/*
39 * default isOn function
40 */
41static int not_connected() {return 0;}
42
43/*
44 * default possible isOn function
45 */
46static int connected() {return 1;}
47
48static rtems_irq_connect_data           rtemsIrq[CPU_IRQ_COUNT];
49static rtems_irq_global_settings        initial_config;
50static rtems_irq_connect_data           defaultIrq = {
51  /* vector,     hdl            , on            , off           , isOn */
52  0,             nop_func       , nop_func      , nop_func      , not_connected
53};
54
55static rtems_irq_prio irqPrioTable[CPU_IRQ_COUNT]={
56  /*
57   * actual priorities for interrupt :
58   *    0   means that only current interrupt is masked
59   *    255 means all other interrupts are masked
60   */
61  /*
62   * USIU interrupts.
63   */
64  7,7, 6,6, 5,5, 4,4, 3,3, 2,2, 1,1, 0,0,
65  /*
66   * UIMB Interrupts
67   *
68   * Note that the first 8 UIMB interrupts overlap the 8 external USIU
69   * interrupts.
70   */
71                          0, 0, 0, 0, 0, 0, 0, 0,
72  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
73  /*
74   * Processor exceptions handled as interrupts
75   */
76  0
77};
78
79void CPU_USIU_irq_init()
80{
81  /*
82   * In theory we should initialize two registers at least : SIMASK and
83   * SIEL. SIMASK is reset at 0 value meaning no interrupts.  If someone
84   * find a reasonnable value for SIEL, and the need to change it, please
85   * feel free to add it here.
86   */
87  ppc_cached_irq_mask = 0;
88  usiu.simask = ppc_cached_irq_mask;
89  usiu.sipend = 0xffff0000;
90  usiu.siel = usiu.siel;
91}
92
93/*
94 * Initialize UIMB interrupt management
95 */
96void
97CPU_UIMB_irq_init(void)
98{
99}
100
101void CPU_rtems_irq_mng_init(unsigned cpuId)
102{
103  rtems_raw_except_connect_data vectorDesc;
104  int i;
105 
106  CPU_USIU_irq_init();
107  CPU_UIMB_irq_init();
108  /*
109   * Initialize Rtems management interrupt table
110   */
111    /*
112     * re-init the rtemsIrq table
113     */
114    for (i = 0; i < CPU_IRQ_COUNT; i++) {
115      rtemsIrq[i]      = defaultIrq;
116      rtemsIrq[i].name = i;
117    }
118    /*
119     * Init initial Interrupt management config
120     */
121    initial_config.irqNb        = CPU_IRQ_COUNT;
122    initial_config.defaultEntry = defaultIrq;
123    initial_config.irqHdlTbl    = rtemsIrq;
124    initial_config.irqBase      = CPU_ASM_IRQ_VECTOR_BASE;
125    initial_config.irqPrioTbl   = irqPrioTable;
126
127    if (!CPU_rtems_irq_mngt_set(&initial_config)) {
128      /*
129       * put something here that will show the failure...
130       */
131      BSP_panic("Unable to initialize RTEMS interrupt Management\n");
132    }
133 
134  /*
135   * We must connect the raw irq handler for the two
136   * expected interrupt sources : decrementer and external interrupts.
137   */
138    vectorDesc.exceptIndex      =       ASM_DEC_VECTOR;
139    vectorDesc.hdl.vector       =       ASM_DEC_VECTOR;
140    vectorDesc.hdl.raw_hdl      =       dispatch_irq_handler;
141    vectorDesc.on               =       nop_func;
142    vectorDesc.off              =       nop_func;
143    vectorDesc.isOn             =       connected;
144    if (!mpc5xx_set_exception (&vectorDesc)) {
145      BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
146    }
147    vectorDesc.exceptIndex      =       ASM_EXT_VECTOR;
148    vectorDesc.hdl.vector       =       ASM_EXT_VECTOR;
149    if (!mpc5xx_set_exception (&vectorDesc)) {
150      BSP_panic("Unable to initialize RTEMS external raw exception\n");
151    }
152}
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