1 | /* |
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2 | * irq_asm.S |
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3 | * |
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4 | * This file contains the assembly code for the PowerPC |
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5 | * IRQ veneers for RTEMS. |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * |
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12 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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13 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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14 | * |
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15 | * Derived from libbsp/powerpc/mbx8xx/irq/irq_asm.S: |
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16 | * |
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17 | * Modified to support the MCP750. |
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18 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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19 | * |
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20 | * Till Straumann <strauman@slac.stanford.edu>, 2003/7: |
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21 | * - store isr nesting level in _ISR_Nest_level rather than |
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22 | * SPRG0 - RTEMS relies on that variable. |
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23 | * |
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24 | * $Id$ |
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25 | */ |
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26 | |
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27 | #include <rtems/asm.h> |
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28 | #include <rtems/score/cpu.h> |
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29 | #include <libcpu/vectors.h> |
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30 | #include <libcpu/raw_exception.h> |
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31 | |
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32 | |
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33 | #define SYNC \ |
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34 | sync; \ |
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35 | isync |
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36 | |
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37 | /* |
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38 | * Common handler for interrupt exceptions. |
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39 | * |
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40 | * The function CPU_rtems_irq_mng_init() initializes the decrementer and |
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41 | * external interrupt entries in the exception handler table with pointers |
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42 | * to this routine, which saves the remainder of the interrupted code's |
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43 | * state, then calls C_dispatch_irq_handler(). |
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44 | * |
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45 | * On entry, R1 points to a new exception stack frame in which R3, R4, and |
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46 | * LR have been saved. R4 holds the exception number. |
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47 | */ |
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48 | PUBLIC_VAR(C_dispatch_irq_handler) |
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49 | |
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50 | PUBLIC_VAR(dispatch_irq_handler) |
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51 | SYM (dispatch_irq_handler): |
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52 | /* |
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53 | * Save SRR0/SRR1 As soon As possible as it is the minimal needed |
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54 | * to re-enable exception processing. |
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55 | * |
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56 | * Note that R2 should never change (it's the EABI pointer to |
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57 | * .sdata2), but we save it just in case. |
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58 | */ |
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59 | stw r0, GPR0_OFFSET(r1) |
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60 | stw r2, GPR2_OFFSET(r1) |
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61 | |
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62 | mfsrr0 r0 |
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63 | mfsrr1 r3 |
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64 | |
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65 | stw r0, SRR0_FRAME_OFFSET(r1) |
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66 | stw r3, SRR1_FRAME_OFFSET(r1) |
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67 | |
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68 | /* |
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69 | * Enable exception recovery. Also enable FP so that FP context |
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70 | * can be saved and restored (using FP instructions). |
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71 | */ |
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72 | mfmsr r3 |
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73 | ori r3, r3, MSR_RI | MSR_FP |
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74 | mtmsr r3 |
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75 | SYNC |
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76 | |
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77 | /* |
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78 | * Push C scratch registers on the current stack. It may actually be |
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79 | * the thread stack or the interrupt stack. Anyway we have to make |
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80 | * it in order to be able to call C/C++ functions. Depending on the |
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81 | * nesting interrupt level, we will switch to the right stack later. |
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82 | */ |
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83 | stw r5, GPR5_OFFSET(r1) |
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84 | stw r6, GPR6_OFFSET(r1) |
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85 | stw r7, GPR7_OFFSET(r1) |
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86 | stw r8, GPR8_OFFSET(r1) |
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87 | stw r9, GPR9_OFFSET(r1) |
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88 | stw r10, GPR10_OFFSET(r1) |
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89 | stw r11, GPR11_OFFSET(r1) |
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90 | stw r12, GPR12_OFFSET(r1) |
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91 | stw r13, GPR13_OFFSET(r1) |
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92 | |
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93 | mfcr r5 |
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94 | mfctr r6 |
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95 | mfxer r7 |
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96 | |
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97 | stw r5, EXC_CR_OFFSET(r1) |
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98 | stw r6, EXC_CTR_OFFSET(r1) |
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99 | stw r7, EXC_XER_OFFSET(r1) |
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100 | |
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101 | /* |
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102 | * Add some non volatile registers to store information that will be |
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103 | * used when returning from C handler. |
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104 | */ |
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105 | stw r14, GPR14_OFFSET(r1) |
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106 | stw r15, GPR15_OFFSET(r1) |
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107 | |
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108 | /* |
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109 | * Save current stack pointer location in R14. |
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110 | */ |
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111 | addi r14, r1, 0 |
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112 | |
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113 | /* |
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114 | * store part of _Thread_Dispatch_disable_level address in R15 |
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115 | */ |
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116 | addis r15, 0, _Thread_Dispatch_disable_level@ha |
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117 | |
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118 | /* |
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119 | * Retrieve current nesting level from _ISR_Nest_level |
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120 | */ |
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121 | lis r7, _ISR_Nest_level@ha |
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122 | lwz r3, _ISR_Nest_level@l(r7) |
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123 | |
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124 | /* |
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125 | * Check if stack switch is necessary |
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126 | */ |
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127 | cmpwi r3, 0 |
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128 | bne nested |
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129 | |
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130 | mfspr r1, SPRG1 /* switch to interrupt stack */ |
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131 | nested: |
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132 | |
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133 | /* |
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134 | * Start Incrementing nesting level in R3 |
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135 | */ |
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136 | addi r3, r3, 1 |
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137 | |
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138 | /* |
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139 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
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140 | */ |
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141 | lwz r6, _Thread_Dispatch_disable_level@l(r15) |
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142 | |
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143 | /* store new nesting level in _ISR_Nest_level */ |
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144 | stw r3, _ISR_Nest_level@l(r7) |
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145 | |
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146 | addi r6, r6, 1 |
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147 | |
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148 | /* |
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149 | * store new _Thread_Dispatch_disable_level value |
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150 | */ |
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151 | stw r6, _Thread_Dispatch_disable_level@l(r15) |
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152 | |
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153 | /* |
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154 | * We are now running on the interrupt stack. External and decrementer |
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155 | * exceptions are still disabled. I see no purpose trying to optimize |
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156 | * further assembler code. |
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157 | */ |
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158 | |
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159 | /* |
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160 | * Call C exception handler for decrementer or external interrupt. |
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161 | * Pass frame along just in case.. |
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162 | * |
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163 | * C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) |
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164 | */ |
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165 | addi r3, r14, 0x8 |
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166 | bl C_dispatch_irq_handler |
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167 | |
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168 | /* |
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169 | * start decrementing nesting level. Note : do not test result against 0 |
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170 | * value as an easy exit condition because if interrupt nesting level > 1 |
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171 | * then _Thread_Dispatch_disable_level > 1 |
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172 | */ |
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173 | lis r7, _ISR_Nest_level@ha |
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174 | lwz r4, _ISR_Nest_level@l(r7) |
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175 | |
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176 | /* |
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177 | * start decrementing _Thread_Dispatch_disable_level |
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178 | */ |
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179 | lwz r3,_Thread_Dispatch_disable_level@l(r15) |
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180 | |
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181 | addi r4, r4, -1 /* Continue decrementing nesting level */ |
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182 | addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */ |
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183 | |
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184 | stw r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */ |
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185 | stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ |
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186 | |
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187 | cmpwi r3, 0 |
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188 | |
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189 | /* |
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190 | * switch back to original stack (done here just optimize registers |
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191 | * contention. Could have been done before...) |
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192 | */ |
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193 | addi r1, r14, 0 |
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194 | bne easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */ |
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195 | |
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196 | /* |
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197 | * Here we are running again on the thread system stack. |
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198 | * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. |
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199 | * Interrupt are still disabled. Time to check if scheduler request to |
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200 | * do something with the current thread... |
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201 | */ |
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202 | addis r4, 0, _Context_Switch_necessary@ha |
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203 | lbz r5, _Context_Switch_necessary@l(r4) |
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204 | cmpwi r5, 0 |
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205 | bne switch |
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206 | |
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207 | addis r6, 0, _ISR_Signals_to_thread_executing@ha |
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208 | lbz r7, _ISR_Signals_to_thread_executing@l(r6) |
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209 | cmpwi r7, 0 |
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210 | li r8, 0 |
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211 | beq easy_exit |
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212 | |
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213 | stb r8, _ISR_Signals_to_thread_executing@l(r6) |
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214 | |
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215 | /* |
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216 | * going to call _ThreadProcessSignalsFromIrq |
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217 | * Push a complete exception like frame... |
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218 | */ |
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219 | stmw r16, GPR16_OFFSET(r1) |
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220 | addi r3, r1, 0x8 |
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221 | |
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222 | /* |
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223 | * compute SP at exception entry |
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224 | */ |
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225 | addi r4, r1, EXCEPTION_FRAME_END |
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226 | |
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227 | /* |
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228 | * store it at the right place |
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229 | */ |
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230 | stw r4, GPR1_OFFSET(r1) |
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231 | |
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232 | /* |
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233 | * Call High Level signal handling code |
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234 | */ |
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235 | bl _ThreadProcessSignalsFromIrq |
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236 | |
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237 | /* |
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238 | * start restoring exception like frame |
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239 | */ |
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240 | lwz r31, EXC_CTR_OFFSET(r1) |
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241 | lwz r30, EXC_XER_OFFSET(r1) |
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242 | lwz r29, EXC_CR_OFFSET(r1) |
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243 | lwz r28, EXC_LR_OFFSET(r1) |
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244 | |
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245 | mtctr r31 |
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246 | mtxer r30 |
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247 | mtcr r29 |
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248 | mtlr r28 |
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249 | |
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250 | lmw r4, GPR4_OFFSET(r1) |
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251 | lwz r2, GPR2_OFFSET(r1) |
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252 | lwz r0, GPR0_OFFSET(r1) |
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253 | |
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254 | /* |
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255 | * Make path non recoverable... |
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256 | */ |
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257 | mtspr nri, r0 |
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258 | SYNC |
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259 | |
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260 | /* |
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261 | * Restore rfi related settings |
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262 | */ |
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263 | |
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264 | lwz r3, SRR1_FRAME_OFFSET(r1) |
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265 | mtsrr1 r3 |
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266 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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267 | mtsrr0 r3 |
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268 | |
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269 | lwz r3, GPR3_OFFSET(r1) |
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270 | addi r1,r1, EXCEPTION_FRAME_END |
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271 | SYNC |
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272 | rfi |
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273 | |
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274 | |
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275 | switch: |
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276 | bl SYM (_Thread_Dispatch) |
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277 | |
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278 | easy_exit: |
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279 | /* |
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280 | * start restoring interrupt frame |
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281 | */ |
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282 | lwz r3, EXC_CTR_OFFSET(r1) |
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283 | lwz r4, EXC_XER_OFFSET(r1) |
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284 | lwz r5, EXC_CR_OFFSET(r1) |
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285 | lwz r6, EXC_LR_OFFSET(r1) |
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286 | |
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287 | mtctr r3 |
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288 | mtxer r4 |
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289 | mtcr r5 |
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290 | mtlr r6 |
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291 | |
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292 | lwz r15, GPR15_OFFSET(r1) |
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293 | lwz r14, GPR14_OFFSET(r1) |
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294 | lwz r13, GPR13_OFFSET(r1) |
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295 | lwz r12, GPR12_OFFSET(r1) |
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296 | lwz r11, GPR11_OFFSET(r1) |
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297 | lwz r10, GPR10_OFFSET(r1) |
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298 | lwz r9, GPR9_OFFSET(r1) |
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299 | lwz r8, GPR8_OFFSET(r1) |
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300 | lwz r7, GPR7_OFFSET(r1) |
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301 | lwz r6, GPR6_OFFSET(r1) |
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302 | lwz r5, GPR5_OFFSET(r1) |
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303 | |
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304 | /* |
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305 | * Disable nested exception processing. |
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306 | */ |
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307 | mtspr nri, r0 |
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308 | SYNC |
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309 | |
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310 | /* |
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311 | * Restore rfi related settings |
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312 | */ |
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313 | lwz r4, SRR1_FRAME_OFFSET(r1) |
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314 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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315 | lwz r2, GPR2_OFFSET(r1) |
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316 | lwz r0, GPR0_OFFSET(r1) |
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317 | |
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318 | mtsrr1 r4 |
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319 | mtsrr0 r3 |
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320 | lwz r4, GPR4_OFFSET(r1) |
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321 | lwz r3, GPR3_OFFSET(r1) |
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322 | addi r1,r1, EXCEPTION_FRAME_END |
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323 | SYNC |
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324 | rfi |
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