source: rtems/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h @ 359e537

4.104.115
Last change on this file since 359e537 was 359e537, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/30/09 at 05:09:41

Whitespace removal.
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File size: 6.0 KB
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1/*
2 * irq.h
3 *
4 *  This include file describe the data structure and the functions implemented
5 *  by rtems to write interrupt handlers.
6 *
7 *
8 *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
9 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
10 *
11 *  Derived from libbsp/powerpc/mbx8xx/irq/irq.h:
12 *
13 *  CopyRight (C) 1999 valette@crf.canon.fr
14 *
15 *  This code is heavilly inspired by the public specification of STREAM V2
16 *  that can be found at :
17 *
18 *      <http://www.chorus.com/Documentation/index.html> by following
19 *  the STREAM API Specification Document link.
20 *
21 *  The license and distribution terms for this file may be
22 *  found in found in the file LICENSE in this distribution or at
23 *  http://www.rtems.com/license/LICENSE.
24 *
25 *  $Id$
26 */
27
28#ifndef _LIBCPU_IRQ_H
29#define _LIBCPU_IRQ_H
30
31#include <rtems/irq.h>
32
33#define CPU_ASM_IRQ_VECTOR_BASE 0x0
34
35#ifndef ASM
36
37extern volatile unsigned int ppc_cached_irq_mask;
38
39/*
40 * Symblolic IRQ names and related definitions.
41 */
42
43  /*
44   * Base vector for our USIU IRQ handlers.
45   */
46#define CPU_USIU_VECTOR_BASE    (CPU_ASM_IRQ_VECTOR_BASE)
47  /*
48   * USIU IRQ handler related definitions
49   */
50#define CPU_USIU_IRQ_COUNT      (16) /* 16 reserved but in the future... */
51#define CPU_USIU_IRQ_MIN_OFFSET (0)
52#define CPU_USIU_IRQ_MAX_OFFSET (CPU_USIU_IRQ_MIN_OFFSET + CPU_USIU_IRQ_COUNT - 1)
53  /*
54   * UIMB IRQ handlers related definitions
55   */
56#define CPU_UIMB_IRQ_COUNT      (32 - 8) /* first 8 overlap USIU */
57#define CPU_UIMB_IRQ_MIN_OFFSET (CPU_USIU_IRQ_COUNT + CPU_USIU_VECTOR_BASE)
58#define CPU_UIMB_IRQ_MAX_OFFSET (CPU_UIMB_IRQ_MIN_OFFSET + CPU_UIMB_IRQ_COUNT - 1)
59  /*
60   * PowerPc exceptions handled as interrupt where a rtems managed interrupt
61   * handler might be connected
62   */
63#define CPU_PROC_IRQ_COUNT      (1)
64#define CPU_PROC_IRQ_MIN_OFFSET (CPU_UIMB_IRQ_MAX_OFFSET + 1)
65#define CPU_PROC_IRQ_MAX_OFFSET (CPU_PROC_IRQ_MIN_OFFSET + CPU_PROC_IRQ_COUNT - 1)
66  /*
67   * Summary
68   */
69#define CPU_IRQ_COUNT           (CPU_PROC_IRQ_MAX_OFFSET + 1)
70#define CPU_MIN_OFFSET          (CPU_USIU_IRQ_MIN_OFFSET)
71#define CPU_MAX_OFFSET          (CPU_PROC_IRQ_MAX_OFFSET)
72  /*
73   * USIU IRQ symbolic name definitions.
74   */
75#define CPU_USIU_EXT_IRQ_0      (CPU_USIU_IRQ_MIN_OFFSET + 0)
76#define CPU_USIU_INT_IRQ_0      (CPU_USIU_IRQ_MIN_OFFSET + 1)
77
78#define CPU_USIU_EXT_IRQ_1      (CPU_USIU_IRQ_MIN_OFFSET + 2)
79#define CPU_USIU_INT_IRQ_1      (CPU_USIU_IRQ_MIN_OFFSET + 3)
80
81#define CPU_USIU_EXT_IRQ_2      (CPU_USIU_IRQ_MIN_OFFSET + 4)
82#define CPU_USIU_INT_IRQ_2      (CPU_USIU_IRQ_MIN_OFFSET + 5)
83
84#define CPU_USIU_EXT_IRQ_3      (CPU_USIU_IRQ_MIN_OFFSET + 6)
85#define CPU_USIU_INT_IRQ_3      (CPU_USIU_IRQ_MIN_OFFSET + 7)
86
87#define CPU_USIU_EXT_IRQ_4      (CPU_USIU_IRQ_MIN_OFFSET + 8)
88#define CPU_USIU_INT_IRQ_4      (CPU_USIU_IRQ_MIN_OFFSET + 9)
89
90#define CPU_USIU_EXT_IRQ_5      (CPU_USIU_IRQ_MIN_OFFSET + 10)
91#define CPU_USIU_INT_IRQ_5      (CPU_USIU_IRQ_MIN_OFFSET + 11)
92
93#define CPU_USIU_EXT_IRQ_6      (CPU_USIU_IRQ_MIN_OFFSET + 12)
94#define CPU_USIU_INT_IRQ_6      (CPU_USIU_IRQ_MIN_OFFSET + 13)
95
96#define CPU_USIU_EXT_IRQ_7      (CPU_USIU_IRQ_MIN_OFFSET + 14)
97#define CPU_USIU_INT_IRQ_7      (CPU_USIU_IRQ_MIN_OFFSET + 15)
98
99  /*
100   * Symbolic names for UISU interrupt sources.
101   */
102#define CPU_PERIODIC_TIMER      (CPU_USIU_INT_IRQ_6)
103#define CPU_UIMB_INTERRUPT      (CPU_USIU_INT_IRQ_7)
104
105  /*
106   * UIMB IRQ symbolic name definitions.  The first 8 sources are aliases to
107   * the USIU interrupts of the same number, because they are detected in
108   * the USIU pending register rather than the UIMB pending register.
109   */
110#define CPU_UIMB_IRQ_0          (CPU_USIU_INT_IRQ_0)
111#define CPU_UIMB_IRQ_1          (CPU_USIU_INT_IRQ_1)
112#define CPU_UIMB_IRQ_2          (CPU_USIU_INT_IRQ_2)
113#define CPU_UIMB_IRQ_3          (CPU_USIU_INT_IRQ_3)
114#define CPU_UIMB_IRQ_4          (CPU_USIU_INT_IRQ_4)
115#define CPU_UIMB_IRQ_5          (CPU_USIU_INT_IRQ_5)
116#define CPU_UIMB_IRQ_6          (CPU_USIU_INT_IRQ_6)
117#define CPU_UIMB_IRQ_7          (CPU_USIU_INT_IRQ_7)
118
119#define CPU_UIMB_IRQ_8          (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
120#define CPU_UIMB_IRQ_9          (CPU_UIMB_IRQ_MIN_OFFSET+ 1)
121#define CPU_UIMB_IRQ_10         (CPU_UIMB_IRQ_MIN_OFFSET+ 2)
122#define CPU_UIMB_IRQ_11         (CPU_UIMB_IRQ_MIN_OFFSET+ 3)
123#define CPU_UIMB_IRQ_12         (CPU_UIMB_IRQ_MIN_OFFSET+ 4)
124#define CPU_UIMB_IRQ_13         (CPU_UIMB_IRQ_MIN_OFFSET+ 5)
125#define CPU_UIMB_IRQ_14         (CPU_UIMB_IRQ_MIN_OFFSET+ 6)
126#define CPU_UIMB_IRQ_15         (CPU_UIMB_IRQ_MIN_OFFSET+ 7)
127#define CPU_UIMB_IRQ_16         (CPU_UIMB_IRQ_MIN_OFFSET+ 8)
128#define CPU_UIMB_IRQ_17         (CPU_UIMB_IRQ_MIN_OFFSET+ 9)
129#define CPU_UIMB_IRQ_18         (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
130#define CPU_UIMB_IRQ_19         (CPU_UIMB_IRQ_MIN_OFFSET+11)
131#define CPU_UIMB_IRQ_20         (CPU_UIMB_IRQ_MIN_OFFSET+12)
132#define CPU_UIMB_IRQ_21         (CPU_UIMB_IRQ_MIN_OFFSET+13)
133#define CPU_UIMB_IRQ_22         (CPU_UIMB_IRQ_MIN_OFFSET+14)
134#define CPU_UIMB_IRQ_23         (CPU_UIMB_IRQ_MIN_OFFSET+15)
135#define CPU_UIMB_IRQ_24         (CPU_UIMB_IRQ_MIN_OFFSET+16)
136#define CPU_UIMB_IRQ_25         (CPU_UIMB_IRQ_MIN_OFFSET+17)
137#define CPU_UIMB_IRQ_26         (CPU_UIMB_IRQ_MIN_OFFSET+18)
138#define CPU_UIMB_IRQ_27         (CPU_UIMB_IRQ_MIN_OFFSET+19)
139#define CPU_UIMB_IRQ_28         (CPU_UIMB_IRQ_MIN_OFFSET+20)
140#define CPU_UIMB_IRQ_29         (CPU_UIMB_IRQ_MIN_OFFSET+21)
141#define CPU_UIMB_IRQ_30         (CPU_UIMB_IRQ_MIN_OFFSET+22)
142#define CPU_UIMB_IRQ_31         (CPU_UIMB_IRQ_MIN_OFFSET+23)
143
144  /*
145   * Symbolic names for UIMB interrupt sources.
146   */
147#define CPU_IRQ_SCI             (CPU_UIMB_IRQ_5)
148
149  /*
150   * Processor exceptions handled as rtems IRQ symbolic name definitions.
151   */
152#define CPU_DECREMENTER         (CPU_PROC_IRQ_MIN_OFFSET)
153
154/*
155 * Convert an rtems_irq_number constant to an interrupt level
156 * suitable for programming into an I/O device's interrupt level field.
157 */
158int CPU_irq_level_from_symbolic_name(const rtems_irq_number name);
159
160/*-------------------------------------------------------------------------+
161| Function Prototypes.
162+--------------------------------------------------------------------------*/
163
164extern void CPU_rtems_irq_mng_init(unsigned cpuId);
165
166#endif
167
168#endif
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