[8430205] | 1 | /* |
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| 2 | * irq.c |
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| 3 | * |
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| 4 | * This file contains the implementation of the function described in irq.h |
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| 5 | * |
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| 6 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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| 7 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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| 8 | * |
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| 9 | * Derived from libbsp/powerpc/mbx8xx/irq/irq.c: |
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| 10 | * |
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| 11 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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| 12 | * |
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| 13 | * The license and distribution terms for this file may be |
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| 14 | * found in found in the file LICENSE in this distribution or at |
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| 15 | * http://www.rtems.com/license/LICENSE. |
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| 16 | * |
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| 17 | * $Id$ |
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| 18 | */ |
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| 19 | |
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| 20 | #include <rtems.h> |
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| 21 | #include <rtems/score/apiext.h> |
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| 22 | #include <mpc5xx.h> |
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| 23 | #include <libcpu/vectors.h> |
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| 24 | #include <libcpu/raw_exception.h> |
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| 25 | #include <libcpu/irq.h> |
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| 26 | |
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| 27 | /* |
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| 28 | * Convert an rtems_irq_symbolic_name constant to an interrupt level |
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| 29 | * suitable for programming into an I/O device's interrupt level field. |
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| 30 | */ |
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| 31 | |
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| 32 | int CPU_irq_level_from_symbolic_name(const rtems_irq_symbolic_name name) |
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| 33 | { |
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| 34 | if (CPU_USIU_EXT_IRQ_0 <= name && name <= CPU_USIU_INT_IRQ_7) |
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| 35 | return (name - CPU_USIU_EXT_IRQ_0) / 2; |
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| 36 | |
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| 37 | if (CPU_UIMB_IRQ_8 <= name && name <= CPU_UIMB_IRQ_31) |
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| 38 | return 8 + (name - CPU_UIMB_IRQ_8); |
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| 39 | |
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| 40 | return 31; /* reasonable default */ |
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| 41 | } |
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| 42 | |
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| 43 | /* |
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| 44 | * default handler connected on each irq after bsp initialization |
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| 45 | */ |
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| 46 | static rtems_irq_connect_data default_rtems_entry; |
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| 47 | |
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| 48 | /* |
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| 49 | * location used to store initial tables used for interrupt |
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| 50 | * management. |
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| 51 | */ |
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| 52 | static rtems_irq_global_settings* internal_config; |
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| 53 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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| 54 | |
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| 55 | /* |
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| 56 | * Check if symbolic IRQ name is an USIU IRQ |
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| 57 | */ |
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| 58 | static inline int is_usiu_irq(const rtems_irq_symbolic_name irqLine) |
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| 59 | { |
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| 60 | return (((int) irqLine <= CPU_USIU_IRQ_MAX_OFFSET) && |
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| 61 | ((int) irqLine >= CPU_USIU_IRQ_MIN_OFFSET) |
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| 62 | ); |
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| 63 | } |
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| 64 | |
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| 65 | /* |
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| 66 | * Check if symbolic IRQ name is an UIMB IRQ |
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| 67 | */ |
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| 68 | static inline int is_uimb_irq(const rtems_irq_symbolic_name irqLine) |
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| 69 | { |
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| 70 | return (((int) irqLine <= CPU_UIMB_IRQ_MAX_OFFSET) && |
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| 71 | ((int) irqLine >= CPU_UIMB_IRQ_MIN_OFFSET) |
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| 72 | ); |
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| 73 | } |
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| 74 | |
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| 75 | /* |
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| 76 | * Check if symbolic IRQ name is a Processor IRQ |
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| 77 | */ |
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| 78 | static inline int is_proc_irq(const rtems_irq_symbolic_name irqLine) |
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| 79 | { |
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| 80 | return (((int) irqLine <= CPU_PROC_IRQ_MAX_OFFSET) && |
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| 81 | ((int) irqLine >= CPU_PROC_IRQ_MIN_OFFSET) |
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| 82 | ); |
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| 83 | } |
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| 84 | |
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| 85 | |
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| 86 | /* |
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| 87 | * Masks used to mask off the interrupts. For exmaple, for ILVL2, the |
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| 88 | * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 |
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| 89 | * and ILVL7. |
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| 90 | * |
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| 91 | */ |
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| 92 | const static unsigned int USIU_IvectMask[CPU_USIU_IRQ_COUNT] = |
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| 93 | { |
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| 94 | 0, /* external IRQ 0 */ |
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| 95 | 0xFFFFFFFF << 31, /* internal level 0 */ |
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| 96 | 0xFFFFFFFF << 30, /* external IRQ 1 */ |
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| 97 | 0xFFFFFFFF << 29, /* internal level 1 */ |
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| 98 | 0xFFFFFFFF << 28, /* external IRQ 2 */ |
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| 99 | 0xFFFFFFFF << 27, /* internal level 2 */ |
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| 100 | 0xFFFFFFFF << 26, /* external IRQ 3 */ |
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| 101 | 0xFFFFFFFF << 25, /* internal level 3 */ |
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| 102 | 0xFFFFFFFF << 24, /* external IRQ 4 */ |
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| 103 | 0xFFFFFFFF << 23, /* internal level 4 */ |
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| 104 | 0xFFFFFFFF << 22, /* external IRQ 5 */ |
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| 105 | 0xFFFFFFFF << 21, /* internal level 5 */ |
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| 106 | 0xFFFFFFFF << 20, /* external IRQ 6 */ |
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| 107 | 0xFFFFFFFF << 19, /* internal level 6 */ |
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| 108 | 0xFFFFFFFF << 18, /* external IRQ 7 */ |
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| 109 | 0xFFFFFFFF << 17 /* internal level 7 */ |
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| 110 | }; |
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| 111 | |
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| 112 | |
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| 113 | /* |
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| 114 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 115 | */ |
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| 116 | |
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| 117 | /* |
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| 118 | * Caution : this function assumes the variable "internal_config" |
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| 119 | * is already set and that the tables it contains are still valid |
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| 120 | * and accessible. |
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| 121 | */ |
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| 122 | static void compute_USIU_IvectMask_from_prio () |
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| 123 | { |
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| 124 | /* |
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| 125 | * In theory this is feasible. No time to code it yet. See i386/shared/irq.c |
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| 126 | * for an example based on 8259 controller mask. The actual masks defined |
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| 127 | * correspond to the priorities defined for the USIU in irq_init.c. |
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| 128 | */ |
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| 129 | } |
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| 130 | |
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| 131 | /* |
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| 132 | * This function check that the value given for the irq line |
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| 133 | * is valid. |
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| 134 | */ |
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| 135 | static int isValidInterrupt(int irq) |
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| 136 | { |
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| 137 | if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET) |
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| 138 | || (irq == CPU_UIMB_INTERRUPT) ) |
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| 139 | return 0; |
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| 140 | return 1; |
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| 141 | } |
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| 142 | |
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| 143 | int CPU_irq_enable_at_uimb(const rtems_irq_symbolic_name irqLine) |
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| 144 | { |
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| 145 | if (!is_uimb_irq(irqLine)) |
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| 146 | return 1; |
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| 147 | return 0; |
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| 148 | } |
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| 149 | |
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| 150 | int CPU_irq_disable_at_uimb(const rtems_irq_symbolic_name irqLine) |
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| 151 | { |
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| 152 | if (!is_uimb_irq(irqLine)) |
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| 153 | return 1; |
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| 154 | return 0; |
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| 155 | } |
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| 156 | |
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| 157 | int CPU_irq_enabled_at_uimb(const rtems_irq_symbolic_name irqLine) |
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| 158 | { |
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| 159 | if (!is_uimb_irq(irqLine)) |
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| 160 | return 0; |
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| 161 | return 1; |
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| 162 | } |
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| 163 | |
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| 164 | int CPU_irq_enable_at_usiu(const rtems_irq_symbolic_name irqLine) |
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| 165 | { |
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| 166 | int usiu_irq_index; |
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| 167 | |
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| 168 | if (!is_usiu_irq(irqLine)) |
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| 169 | return 1; |
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| 170 | |
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| 171 | usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET); |
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| 172 | ppc_cached_irq_mask |= (1 << (31-usiu_irq_index)); |
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| 173 | usiu.simask = ppc_cached_irq_mask; |
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| 174 | |
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| 175 | return 0; |
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| 176 | } |
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| 177 | |
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| 178 | int CPU_irq_disable_at_usiu(const rtems_irq_symbolic_name irqLine) |
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| 179 | { |
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| 180 | int usiu_irq_index; |
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| 181 | |
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| 182 | if (!is_usiu_irq(irqLine)) |
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| 183 | return 1; |
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| 184 | |
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| 185 | usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET); |
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| 186 | ppc_cached_irq_mask &= ~(1 << (31-usiu_irq_index)); |
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| 187 | usiu.simask = ppc_cached_irq_mask; |
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| 188 | |
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| 189 | return 0; |
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| 190 | } |
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| 191 | |
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| 192 | int CPU_irq_enabled_at_usiu(const rtems_irq_symbolic_name irqLine) |
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| 193 | { |
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| 194 | int usiu_irq_index; |
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| 195 | |
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| 196 | if (!is_usiu_irq(irqLine)) |
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| 197 | return 0; |
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| 198 | |
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| 199 | usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET); |
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| 200 | return ppc_cached_irq_mask & (1 << (31-usiu_irq_index)); |
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| 201 | } |
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| 202 | |
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| 203 | /* |
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| 204 | * --------------- RTEMS Single Irq Handler Mngt Routines ---------------- |
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| 205 | */ |
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| 206 | |
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| 207 | int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 208 | { |
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| 209 | unsigned int level; |
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| 210 | |
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| 211 | if (!isValidInterrupt(irq->name)) { |
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| 212 | return 0; |
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| 213 | } |
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| 214 | /* |
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| 215 | * Check if default handler is actually connected. If not issue an error. |
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| 216 | * You must first get the current handler via CPU_get_current_idt_entry |
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| 217 | * and then disconnect it using CPU_delete_idt_entry. |
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| 218 | * RATIONALE : to always have the same transition by forcing the user |
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| 219 | * to get the previous handler before accepting to disconnect. |
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| 220 | */ |
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| 221 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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| 222 | return 0; |
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| 223 | } |
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| 224 | |
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| 225 | _CPU_ISR_Disable(level); |
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| 226 | |
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| 227 | /* |
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| 228 | * store the data provided by user |
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| 229 | */ |
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| 230 | rtems_hdl_tbl[irq->name] = *irq; |
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| 231 | |
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| 232 | if (is_uimb_irq(irq->name)) { |
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| 233 | /* |
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| 234 | * Enable interrupt at UIMB level |
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| 235 | */ |
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| 236 | CPU_irq_enable_at_uimb (irq->name); |
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| 237 | } |
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| 238 | |
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| 239 | if (is_usiu_irq(irq->name)) { |
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| 240 | /* |
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| 241 | * Enable interrupt at USIU level |
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| 242 | */ |
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| 243 | CPU_irq_enable_at_usiu (irq->name); |
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| 244 | } |
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| 245 | |
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| 246 | if (is_proc_irq(irq->name)) { |
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| 247 | /* |
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| 248 | * Should Enable exception at processor level but not needed. Will restore |
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| 249 | * EE flags at the end of the routine anyway. |
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| 250 | */ |
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| 251 | } |
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| 252 | /* |
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| 253 | * Enable interrupt on device |
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| 254 | */ |
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| 255 | irq->on(irq); |
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| 256 | |
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| 257 | _CPU_ISR_Enable(level); |
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| 258 | |
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| 259 | return 1; |
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| 260 | } |
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| 261 | |
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| 262 | |
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| 263 | int CPU_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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| 264 | { |
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| 265 | if (!isValidInterrupt(irq->name)) { |
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| 266 | return 0; |
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| 267 | } |
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| 268 | *irq = rtems_hdl_tbl[irq->name]; |
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| 269 | return 1; |
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| 270 | } |
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| 271 | |
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| 272 | int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 273 | { |
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| 274 | unsigned int level; |
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| 275 | |
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| 276 | if (!isValidInterrupt(irq->name)) { |
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| 277 | return 0; |
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| 278 | } |
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| 279 | /* |
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| 280 | * Check if default handler is actually connected. If not issue an error. |
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| 281 | * You must first get the current handler via CPU_get_current_idt_entry |
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| 282 | * and then disconnect it using CPU_delete_idt_entry. |
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| 283 | * RATIONALE : to always have the same transition by forcing the user |
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| 284 | * to get the previous handler before accepting to disconnect. |
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| 285 | */ |
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| 286 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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| 287 | return 0; |
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| 288 | } |
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| 289 | _CPU_ISR_Disable(level); |
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| 290 | |
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| 291 | /* |
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| 292 | * Disable interrupt on device |
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| 293 | */ |
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| 294 | irq->off(irq); |
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| 295 | |
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| 296 | if (is_uimb_irq(irq->name)) { |
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| 297 | /* |
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| 298 | * disable interrupt at UIMB level |
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| 299 | */ |
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| 300 | CPU_irq_disable_at_uimb (irq->name); |
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| 301 | } |
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| 302 | if (is_usiu_irq(irq->name)) { |
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| 303 | /* |
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| 304 | * disable interrupt at USIU level |
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| 305 | */ |
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| 306 | CPU_irq_disable_at_usiu (irq->name); |
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| 307 | } |
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| 308 | if (is_proc_irq(irq->name)) { |
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| 309 | /* |
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| 310 | * disable exception at processor level |
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| 311 | */ |
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| 312 | } |
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| 313 | |
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| 314 | /* |
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| 315 | * restore the default irq value |
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| 316 | */ |
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| 317 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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| 318 | |
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| 319 | _CPU_ISR_Enable(level); |
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| 320 | |
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| 321 | return 1; |
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| 322 | } |
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| 323 | |
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| 324 | /* |
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| 325 | * ---------------- RTEMS Global Irq Handler Mngt Routines ---------------- |
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| 326 | */ |
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| 327 | |
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| 328 | int CPU_rtems_irq_mngt_set (rtems_irq_global_settings* config) |
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| 329 | { |
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| 330 | int i; |
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| 331 | unsigned int level; |
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| 332 | |
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| 333 | /* |
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| 334 | * Store various code accelerators |
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| 335 | */ |
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| 336 | internal_config = config; |
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| 337 | default_rtems_entry = config->defaultEntry; |
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| 338 | rtems_hdl_tbl = config->irqHdlTbl; |
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| 339 | |
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| 340 | _CPU_ISR_Disable(level); |
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| 341 | |
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| 342 | /* |
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| 343 | * Start with UIMB IRQ |
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| 344 | */ |
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| 345 | for (i = CPU_UIMB_IRQ_MIN_OFFSET; i <= CPU_UIMB_IRQ_MAX_OFFSET ; i++) { |
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| 346 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 347 | CPU_irq_enable_at_uimb (i); |
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| 348 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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| 349 | } |
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| 350 | else { |
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| 351 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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| 352 | CPU_irq_disable_at_uimb (i); |
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| 353 | } |
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| 354 | } |
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| 355 | |
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| 356 | /* |
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| 357 | * Continue with USIU IRQ |
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| 358 | * Set up internal tables used by rtems interrupt prologue |
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| 359 | */ |
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| 360 | compute_USIU_IvectMask_from_prio (); |
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| 361 | |
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| 362 | for (i = CPU_USIU_IRQ_MIN_OFFSET; i <= CPU_USIU_IRQ_MAX_OFFSET ; i++) { |
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| 363 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 364 | CPU_irq_enable_at_usiu (i); |
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| 365 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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| 366 | } |
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| 367 | else { |
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| 368 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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| 369 | CPU_irq_disable_at_usiu (i); |
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| 370 | } |
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| 371 | } |
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| 372 | |
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| 373 | /* |
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| 374 | * Enable all UIMB interrupt lines, then enable at USIU. |
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| 375 | */ |
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| 376 | imb.uimb.umcr |= UIMB_UMCR_IRQMUX(3); |
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| 377 | CPU_irq_enable_at_usiu (CPU_UIMB_INTERRUPT); |
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| 378 | |
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| 379 | /* |
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| 380 | * finish with Processor exceptions handled like IRQ |
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| 381 | */ |
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| 382 | for (i = CPU_PROC_IRQ_MIN_OFFSET; i <= CPU_PROC_IRQ_MAX_OFFSET; i++) { |
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| 383 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 384 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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| 385 | } |
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| 386 | else { |
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| 387 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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| 388 | } |
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| 389 | } |
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| 390 | _CPU_ISR_Enable(level); |
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| 391 | return 1; |
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| 392 | } |
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| 393 | |
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| 394 | int CPU_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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| 395 | { |
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| 396 | *config = internal_config; |
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| 397 | return 0; |
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| 398 | } |
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| 399 | |
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| 400 | |
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| 401 | /* |
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| 402 | * High level IRQ handler called from shared_raw_irq_code_entry |
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| 403 | */ |
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| 404 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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| 405 | { |
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| 406 | register unsigned int irq; |
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| 407 | register unsigned uimbIntr; /* boolean */ |
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| 408 | register unsigned oldMask; /* old siu pic masks */ |
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| 409 | register unsigned msr; |
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| 410 | register unsigned new_msr; |
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| 411 | |
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| 412 | /* |
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| 413 | * Handle decrementer interrupt |
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| 414 | */ |
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| 415 | if (excNum == ASM_DEC_VECTOR) { |
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| 416 | _CPU_MSR_GET(msr); |
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| 417 | new_msr = msr | MSR_EE; |
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| 418 | _CPU_MSR_SET(new_msr); |
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| 419 | |
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| 420 | rtems_hdl_tbl[CPU_DECREMENTER].hdl(); |
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| 421 | |
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| 422 | _CPU_MSR_SET(msr); |
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| 423 | return; |
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| 424 | } |
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| 425 | |
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| 426 | /* |
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| 427 | * Handle external interrupt generated by USIU on PPC core |
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| 428 | */ |
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| 429 | while ((ppc_cached_irq_mask & usiu.sipend) != 0) { |
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| 430 | irq = (usiu.sivec >> 26); |
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| 431 | uimbIntr = (irq == CPU_UIMB_INTERRUPT); |
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| 432 | /* |
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| 433 | * Disable the interrupt of the same and lower priority. |
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| 434 | */ |
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| 435 | oldMask = ppc_cached_irq_mask; |
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| 436 | ppc_cached_irq_mask = oldMask & USIU_IvectMask[irq]; |
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| 437 | usiu.simask = ppc_cached_irq_mask; |
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| 438 | /* |
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| 439 | * Acknowledge current interrupt. This has no effect on internal level |
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| 440 | * interrupts. |
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| 441 | */ |
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| 442 | usiu.sipend = (1 << (31 - irq)); |
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| 443 | |
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| 444 | if (uimbIntr) { |
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| 445 | /* |
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| 446 | * Look at the bits set in the UIMB interrupt-pending register. The |
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| 447 | * highest-order set bit indicates the handler we will run. |
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| 448 | * |
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| 449 | * Unfortunately, we can't easily mask individual UIMB interrupts |
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| 450 | * unless they use USIU levels 0 to 6, so we must mask all low-level |
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| 451 | * (level > 7) UIMB interrupts while we service any interrupt. |
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| 452 | */ |
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| 453 | int uipend = imb.uimb.uipend << 8; |
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| 454 | |
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| 455 | if (uipend == 0) { /* spurious interrupt? use last vector */ |
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| 456 | irq = CPU_UIMB_IRQ_MAX_OFFSET; |
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| 457 | } |
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| 458 | else { |
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| 459 | irq = CPU_UIMB_IRQ_MIN_OFFSET; |
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| 460 | for ( ; (uipend & 0x8000000) == 0; uipend <<= 1) { |
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| 461 | irq++; |
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| 462 | } |
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| 463 | } |
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| 464 | } |
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| 465 | _CPU_MSR_GET(msr); |
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| 466 | new_msr = msr | MSR_EE; |
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| 467 | _CPU_MSR_SET(new_msr); |
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| 468 | |
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| 469 | rtems_hdl_tbl[irq].hdl(); |
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| 470 | |
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| 471 | _CPU_MSR_SET(msr); |
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| 472 | |
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| 473 | ppc_cached_irq_mask = oldMask; |
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| 474 | usiu.simask = ppc_cached_irq_mask; |
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| 475 | } |
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| 476 | } |
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| 477 | |
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| 478 | void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx) |
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| 479 | { |
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| 480 | /* |
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| 481 | * Process pending signals that have not already been |
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| 482 | * processed by _Thread_Displatch. This happens quite |
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| 483 | * unfrequently : the ISR must have posted an action |
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| 484 | * to the current running thread. |
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| 485 | */ |
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| 486 | if ( _Thread_Do_post_task_switch_extension || |
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| 487 | _Thread_Executing->do_post_task_switch_extension ) { |
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| 488 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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| 489 | _API_extensions_Run_postswitch(); |
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| 490 | } |
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| 491 | /* |
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| 492 | * I plan to process other thread related events here. |
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| 493 | * This will include DEBUG session requested from keyboard... |
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| 494 | */ |
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| 495 | } |
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