1 | /* |
---|
2 | * mpc5xx.h |
---|
3 | * |
---|
4 | * MPC5xx Internal I/O Definitions |
---|
5 | * |
---|
6 | * |
---|
7 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
---|
8 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
---|
9 | * |
---|
10 | * Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h: |
---|
11 | * |
---|
12 | * Submitted By: * |
---|
13 | * * |
---|
14 | * W. Eric Norum * |
---|
15 | * Saskatchewan Accelerator Laboratory * |
---|
16 | * University of Saskatchewan * |
---|
17 | * 107 North Road * |
---|
18 | * Saskatoon, Saskatchewan, CANADA * |
---|
19 | * S7N 5C6 * |
---|
20 | * * |
---|
21 | * eric@skatter.usask.ca * |
---|
22 | * * |
---|
23 | * Modified for use with the MPC860 (original code was for MC68360) * |
---|
24 | * by * |
---|
25 | * Jay Monkman * |
---|
26 | * Frasca International, Inc. * |
---|
27 | * 906 E. Airport Rd. * |
---|
28 | * Urbana, IL, 61801 * |
---|
29 | * * |
---|
30 | * jmonkman@frasca.com * |
---|
31 | * * |
---|
32 | * Modified further for use with the MPC821 by: * |
---|
33 | * Andrew Bray <andy@chaos.org.uk> * |
---|
34 | * * |
---|
35 | * With some corrections/additions by: * |
---|
36 | * Darlene A. Stewart and * |
---|
37 | * Charles-Antoine Gauthier * |
---|
38 | * Institute for Information Technology * |
---|
39 | * National Research Council of Canada * |
---|
40 | * Ottawa, ON K1A 0R6 * |
---|
41 | * * |
---|
42 | * Darlene.Stewart@iit.nrc.ca * |
---|
43 | * charles.gauthier@iit.nrc.ca * |
---|
44 | * * |
---|
45 | * Corrections/additions: * |
---|
46 | * Copyright (c) 1999, National Research Council of Canada * |
---|
47 | * |
---|
48 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
---|
49 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
---|
50 | * |
---|
51 | * The license and distribution terms for this file may be |
---|
52 | * found in found in the file LICENSE in this distribution or at |
---|
53 | * http://www.rtems.com/license/LICENSE. |
---|
54 | * |
---|
55 | * $Id$ |
---|
56 | */ |
---|
57 | |
---|
58 | #ifndef _MPC5xx_h |
---|
59 | #define _MPC5xx_h |
---|
60 | |
---|
61 | #include <libcpu/spr.h> |
---|
62 | |
---|
63 | |
---|
64 | #ifndef ASM |
---|
65 | |
---|
66 | #ifdef __cplusplus |
---|
67 | extern "C" { |
---|
68 | #endif |
---|
69 | |
---|
70 | /* |
---|
71 | * Macros for accessing Special Purpose Registers (SPRs) |
---|
72 | */ |
---|
73 | |
---|
74 | #define _eieio __asm__ volatile ("eieio\n"::) |
---|
75 | #define _sync __asm__ volatile ("sync\n"::) |
---|
76 | #define _isync __asm__ volatile ("isync\n"::) |
---|
77 | |
---|
78 | /* |
---|
79 | * Core Registers (SPRs) |
---|
80 | */ |
---|
81 | #define DER 149 /* Debug Enable Register */ |
---|
82 | #define IMMR 638 /* Internal Memory Map Register */ |
---|
83 | #define IMMR_FLEN (1<<11) /* Internal flash ROM enabled */ |
---|
84 | |
---|
85 | /* |
---|
86 | * Interrupt Control Registers (SPRs) |
---|
87 | */ |
---|
88 | #define EIE 80 /* External Interrupt Enable Register */ |
---|
89 | #define EID 81 /* External Interrupt Disable Register */ |
---|
90 | #define NRI 82 /* Non-Recoverable Interrupt Register */ |
---|
91 | |
---|
92 | #define ECR 148 /* Exception Cause Register */ |
---|
93 | |
---|
94 | /* |
---|
95 | * Bus Control Registers (SPRs) |
---|
96 | */ |
---|
97 | #define LCTRL1 156 /* L-Bus Support Control Register 1 */ |
---|
98 | #define LCTRL2 157 /* L-Bus Support Control Register 2 */ |
---|
99 | #define ICTRL 158 /* I-Bus Support Control Register */ |
---|
100 | |
---|
101 | /* |
---|
102 | * Burst Buffer Control Registers (SPRs) |
---|
103 | */ |
---|
104 | #define BBCMCR 560 /* Burst Buffer Configuration Register */ |
---|
105 | #define BBCMCR_BE (1<<13) /* Burst enable */ |
---|
106 | #define BBCMCR_ETRE (1<<12) /* Exception table relocation enable */ |
---|
107 | |
---|
108 | #define MI_RBA0 784 /* Region 0 Address Register */ |
---|
109 | #define MI_RBA1 785 /* Region 1 Address Register */ |
---|
110 | #define MI_RBA2 786 /* Region 2 Address Register */ |
---|
111 | #define MI_RBA3 787 /* Region 3 Address Register */ |
---|
112 | |
---|
113 | #define MI_RA0 816 /* Region 0 Attribute Register */ |
---|
114 | #define MI_RA1 817 /* Region 1 Attribute Register */ |
---|
115 | #define MI_RA2 818 /* Region 2 Attribute Register */ |
---|
116 | #define MI_RA3 819 /* Region 3 Attribute Register */ |
---|
117 | #define MI_GRA 528 /* Region Global Attribute Register */ |
---|
118 | #define MI_RA_PP (3 << 10) /* Protection bits: */ |
---|
119 | #define MI_RA_PP_SUPV (1 << 10) /* Supervisor */ |
---|
120 | #define MI_RA_PP_USER (2 << 10) /* User */ |
---|
121 | #define MI_RA_G (1 << 6) /* Guarded region */ |
---|
122 | |
---|
123 | |
---|
124 | /* |
---|
125 | * L-Bus to U-Bus Interface (L2U) Registers (SPRs) |
---|
126 | */ |
---|
127 | #define L2U_MCR 568 /* L2U Module Configuration Register */ |
---|
128 | |
---|
129 | #define L2U_RBA0 792 /* L2U Region 0 Address Register */ |
---|
130 | #define L2U_RBA1 793 /* L2U Region 1 Address Register */ |
---|
131 | #define L2U_RBA2 794 /* L2U Region 2 Address Register */ |
---|
132 | #define L2U_RBA3 795 /* L2U Region 3 Address Register */ |
---|
133 | |
---|
134 | #define L2U_RA0 824 /* L2U Region 0 Attribute Register */ |
---|
135 | #define L2U_RA1 825 /* L2U Region 1 Attribute Register */ |
---|
136 | #define L2U_RA2 826 /* L2U Region 2 Attribute Register */ |
---|
137 | #define L2U_RA3 827 /* L2U Region 3 Attribute Register */ |
---|
138 | #define L2U_GRA 536 /* L2U Global Region Attribute Register */ |
---|
139 | #define L2U_RA_PP (3 << 10) /* Protection bits: */ |
---|
140 | #define L2U_RA_PP_SUPV (1 << 10) /* Supervisor */ |
---|
141 | #define L2U_RA_PP_USER (2 << 10) /* User */ |
---|
142 | #define L2U_RA_G (1 << 6) /* Guarded region */ |
---|
143 | |
---|
144 | |
---|
145 | /* |
---|
146 | ************************************************************************* |
---|
147 | * REGISTER SUBBLOCKS * |
---|
148 | ************************************************************************* |
---|
149 | */ |
---|
150 | |
---|
151 | /* |
---|
152 | ************************************************************************* |
---|
153 | * System Protection Control Register (SYPCR) * |
---|
154 | ************************************************************************* |
---|
155 | */ |
---|
156 | #define USIU_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ |
---|
157 | #define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ |
---|
158 | #define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ |
---|
159 | #define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ |
---|
160 | #define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ |
---|
161 | #define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ |
---|
162 | #define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ |
---|
163 | |
---|
164 | #define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ |
---|
165 | #define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ |
---|
166 | #define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ |
---|
167 | #define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ |
---|
168 | #define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ |
---|
169 | #define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ |
---|
170 | |
---|
171 | /* |
---|
172 | ************************************************************************* |
---|
173 | * Software Service Register (SWSR) * |
---|
174 | ************************************************************************* |
---|
175 | */ |
---|
176 | #define TICKLE_WATCHDOG() \ |
---|
177 | do { \ |
---|
178 | usiu.swsr = 0x556C; \ |
---|
179 | usiu.swsr = 0xAA39; \ |
---|
180 | } while (0) \ |
---|
181 | |
---|
182 | /* |
---|
183 | ************************************************************************* |
---|
184 | * Memory Control Registers * |
---|
185 | ************************************************************************* |
---|
186 | */ |
---|
187 | #define USIU_MEMC_BR_BA(x) (((rtems_unsigned32)x)&0xffff8000) |
---|
188 | /* Base address */ |
---|
189 | #define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */ |
---|
190 | #define USIU_MEMC_BR_PS8 (1<<10) /* 8 bit port */ |
---|
191 | #define USIU_MEMC_BR_PS16 (2<<10) /* 16 bit port */ |
---|
192 | #define USIU_MEMC_BR_PS32 (0<<10) /* 32 bit port */ |
---|
193 | #define USIU_MEMC_BR_WP (1<<8) /* Write protect */ |
---|
194 | #define USIU_MEMC_BR_WEBS (1<<5) /* Write enable/byte select */ |
---|
195 | #define USIU_MEMC_BR_TBDIP (1<<4) /* Toggle-Burst data in progress*/ |
---|
196 | #define USIU_MEMC_BR_LBDIP (1<<3) /* Late-burst data in progress */ |
---|
197 | #define USIU_MEMC_BR_SETA (1<<2) /* External transfer acknowledge */ |
---|
198 | #define USIU_MEMC_BR_BI (1<<1) /* Burst inhibit */ |
---|
199 | #define USIU_MEMC_BR_V (1<<0) /* Base/Option register are valid */ |
---|
200 | |
---|
201 | #define USIU_MEMC_OR_32K 0xffff8000 /* Address range */ |
---|
202 | #define USIU_MEMC_OR_64K 0xffff0000 |
---|
203 | #define USIU_MEMC_OR_128K 0xfffe0000 |
---|
204 | #define USIU_MEMC_OR_256K 0xfffc0000 |
---|
205 | #define USIU_MEMC_OR_512K 0xfff80000 |
---|
206 | #define USIU_MEMC_OR_1M 0xfff00000 |
---|
207 | #define USIU_MEMC_OR_2M 0xffe00000 |
---|
208 | #define USIU_MEMC_OR_4M 0xffc00000 |
---|
209 | #define USIU_MEMC_OR_8M 0xff800000 |
---|
210 | #define USIU_MEMC_OR_16M 0xff000000 |
---|
211 | #define USIU_MEMC_OR_32M 0xfe000000 |
---|
212 | #define USIU_MEMC_OR_64M 0xfc000000 |
---|
213 | #define USIU_MEMC_OR_128 0xf8000000 |
---|
214 | #define USIU_MEMC_OR_256M 0xf0000000 |
---|
215 | #define USIU_MEMC_OR_512M 0xe0000000 |
---|
216 | #define USIU_MEMC_OR_1G 0xc0000000 |
---|
217 | #define USIU_MEMC_OR_2G 0x80000000 |
---|
218 | #define USIU_MEMC_OR_4G 0x00000000 |
---|
219 | #define USIU_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ |
---|
220 | #define USIU_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ |
---|
221 | #define USIU_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ |
---|
222 | #define USIU_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ |
---|
223 | #define USIU_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ |
---|
224 | #define USIU_MEMC_OR_ETHR (1<<8) /* Extended hold time on reads */ |
---|
225 | #define USIU_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ |
---|
226 | #define USIU_MEMC_OR_BSCY(x) ((x)<<1) /* Burst beat length in clocks */ |
---|
227 | #define USIU_MEMC_OR_TRLX (1<<0) /* Relaxed timing in GPCM */ |
---|
228 | |
---|
229 | /* |
---|
230 | ************************************************************************* |
---|
231 | * Clocks and Reset Controlmer * |
---|
232 | ************************************************************************* |
---|
233 | */ |
---|
234 | |
---|
235 | #define USIU_SCCR_DBCT (1<<31) /* Disable backup clock for timers */ |
---|
236 | #define USIU_SCCR_COM(x) ((x)<<29) /* Clock output mode */ |
---|
237 | #define USIU_SCCR_RTDIV (1<<24) /* RTC, PIT divide by 256, not 4 */ |
---|
238 | #define USIU_PRQEN (1<<21) /* MSR[POW] controls frequency */ |
---|
239 | #define USIU_SCCR_EBDF(x) ((x)<<17) /* External bus division factor */ |
---|
240 | #define USIU_LME (1<<16) /* Enable limp mode */ |
---|
241 | #define USIU_ENGDIV(x) ((x)<<9) /* Set engineering clock divisor */ |
---|
242 | |
---|
243 | #define USIU_PLPRCR_MF(x) (((x)-1)<<20) /* PLL mult. factor (true) */ |
---|
244 | #define USIU_PLPRCR_SPLS (1<<16) /* System PLL locked */ |
---|
245 | #define USIU_PLPRCR_TEXPS (1<<14) /* Assert TEXP always */ |
---|
246 | |
---|
247 | /* |
---|
248 | ************************************************************************* |
---|
249 | * Programmable Interval Timer * |
---|
250 | ************************************************************************* |
---|
251 | */ |
---|
252 | #define USIU_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ |
---|
253 | #define USIU_PISCR_PS (1<<7) /* PIT Interrupt state */ |
---|
254 | #define USIU_PISCR_PIE (1<<2) /* PIT interrupt enable */ |
---|
255 | #define USIU_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ |
---|
256 | #define USIU_PISCR_PTE (1<<0) /* PIT enable */ |
---|
257 | |
---|
258 | /* |
---|
259 | ************************************************************************* |
---|
260 | * Time Base * |
---|
261 | ************************************************************************* |
---|
262 | */ |
---|
263 | #define USIU_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ |
---|
264 | #define USIU_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ |
---|
265 | #define USIU_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ |
---|
266 | #define USIU_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ |
---|
267 | #define USIU_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ |
---|
268 | #define USIU_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ |
---|
269 | #define USIU_TBSCR_TBE (1<<0) /* enable TB and decrementer */ |
---|
270 | |
---|
271 | /* |
---|
272 | ************************************************************************* |
---|
273 | * SIU Interrupt Mask * |
---|
274 | ************************************************************************* |
---|
275 | */ |
---|
276 | #define USIU_SIMASK_IRM0 (1<<31) |
---|
277 | #define USIU_SIMASK_LVM0 (1<<30) |
---|
278 | #define USIU_SIMASK_IRM1 (1<<29) |
---|
279 | #define USIU_SIMASK_LVM1 (1<<28) |
---|
280 | #define USIU_SIMASK_IRM2 (1<<27) |
---|
281 | #define USIU_SIMASK_LVM2 (1<<26) |
---|
282 | #define USIU_SIMASK_IRM3 (1<<25) |
---|
283 | #define USIU_SIMASK_LVM3 (1<<24) |
---|
284 | #define USIU_SIMASK_IRM4 (1<<23) |
---|
285 | #define USIU_SIMASK_LVM4 (1<<22) |
---|
286 | #define USIU_SIMASK_IRM5 (1<<21) |
---|
287 | #define USIU_SIMASK_LVM5 (1<<20) |
---|
288 | #define USIU_SIMASK_IRM6 (1<<19) |
---|
289 | #define USIU_SIMASK_LVM6 (1<<18) |
---|
290 | #define USIU_SIMASK_IRM7 (1<<17) |
---|
291 | #define USIU_SIMASK_LVM7 (1<<16) |
---|
292 | |
---|
293 | /* |
---|
294 | ************************************************************************* |
---|
295 | * SIU Module Control * |
---|
296 | ************************************************************************* |
---|
297 | */ |
---|
298 | #define USIU_SIUMCR_EARB (1<<31) |
---|
299 | #define USIU_SIUMCR_EARP0 (0<<28) |
---|
300 | #define USIU_SIUMCR_EARP1 (1<<28) |
---|
301 | #define USIU_SIUMCR_EARP2 (2<<28) |
---|
302 | #define USIU_SIUMCR_EARP3 (3<<28) |
---|
303 | #define USIU_SIUMCR_EARP4 (4<<28) |
---|
304 | #define USIU_SIUMCR_EARP5 (5<<28) |
---|
305 | #define USIU_SIUMCR_EARP6 (6<<28) |
---|
306 | #define USIU_SIUMCR_EARP7 (7<<28) |
---|
307 | #define USIU_SIUMCR_DSHW (1<<23) |
---|
308 | #define USIU_SIUMCR_DBGC0 (0<<21) |
---|
309 | #define USIU_SIUMCR_DBGC1 (1<<21) |
---|
310 | #define USIU_SIUMCR_DBGC2 (2<<21) |
---|
311 | #define USIU_SIUMCR_DBGC3 (3<<21) |
---|
312 | #define USIU_SIUMCR_DBPC (1<<20) |
---|
313 | #define USIU_SIUMCR_ATWC (1<<19) |
---|
314 | #define USIU_SIUMCR_GPC0 (0<<17) |
---|
315 | #define USIU_SIUMCR_GPC1 (1<<17) |
---|
316 | #define USIU_SIUMCR_GPC2 (2<<17) |
---|
317 | #define USIU_SIUMCR_GPC3 (3<<17) |
---|
318 | #define USIU_SIUMCR_DLK (1<<16) |
---|
319 | #define USIU_SIUMCR_SC0 (0<<13) |
---|
320 | #define USIU_SIUMCR_SC1 (1<<13) |
---|
321 | #define USIU_SIUMCR_SC2 (2<<13) |
---|
322 | #define USIU_SIUMCR_SC3 (3<<13) |
---|
323 | #define USIU_SIUMCR_RCTX (1<<12) |
---|
324 | #define USIU_SIUMCR_MLRC0 (0<<10) |
---|
325 | #define USIU_SIUMCR_MLRC1 (1<<10) |
---|
326 | #define USIU_SIUMCR_MLRC2 (2<<10) |
---|
327 | #define USIU_SIUMCR_MLRC3 (3<<10) |
---|
328 | #define USIU_SIUMCR_MTSC (1<<7) |
---|
329 | |
---|
330 | /* |
---|
331 | * Value to write to a key register to unlock the corresponding SIU register |
---|
332 | */ |
---|
333 | #define USIU_UNLOCK_KEY 0x55CCAA33 |
---|
334 | |
---|
335 | /* |
---|
336 | ************************************************************************* |
---|
337 | * UIMB Module Control * |
---|
338 | ************************************************************************* |
---|
339 | */ |
---|
340 | #define UIMB_UMCR_STOP (1<<31) |
---|
341 | #define UIMB_UMCR_IRQMUX(x) ((x)<<29) |
---|
342 | #define UIMB_UMCR_HSPEED (1<<28) |
---|
343 | |
---|
344 | /* |
---|
345 | ************************************************************************* |
---|
346 | * QSMCM Serial Communications Interface (SCI) * |
---|
347 | ************************************************************************* |
---|
348 | */ |
---|
349 | |
---|
350 | |
---|
351 | #define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */ |
---|
352 | |
---|
353 | #define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */ |
---|
354 | |
---|
355 | #define QSMCM_SCI_LOOPS (1<<14) /* Loopback test mode */ |
---|
356 | #define QSMCM_SCI_WOMS (1<<13) /* Wire-or mode select */ |
---|
357 | #define QSMCM_SCI_ILT (1<<12) /* Idle-line detect type */ |
---|
358 | #define QSMCM_SCI_PT (1<<11) /* Parity type */ |
---|
359 | #define QSMCM_SCI_PE (1<<10) /* Parity enable */ |
---|
360 | #define QSMCM_SCI_M (1<<9) /* 11-bit mode */ |
---|
361 | #define QSMCM_SCI_WAKE (1<<8) /* Wakeup mode */ |
---|
362 | |
---|
363 | #define QSMCM_SCI_TIE (1<<7) /* Transmitter interrupt enable */ |
---|
364 | #define QSMCM_SCI_TCIE (1<<6) /* Transmit complete intr. enable */ |
---|
365 | #define QSMCM_SCI_RIE (1<<5) /* Receiver interrupt enable */ |
---|
366 | #define QSMCM_SCI_ILIE (1<<4) /* Idle line interrupt enable */ |
---|
367 | #define QSMCM_SCI_TE (1<<3) /* Transmitter enable */ |
---|
368 | #define QSMCM_SCI_RE (1<<2) /* Receiver enable */ |
---|
369 | #define QSMCM_SCI_RWU (1<<1) /* Receiver wake-up enable */ |
---|
370 | #define QSMCM_SCI_SBK (1<<0) /* Send break */ |
---|
371 | |
---|
372 | #define QSMCM_SCI_TDRE (1<<8) /* Transmit data register empty */ |
---|
373 | #define QSMCM_SCI_TC (1<<7) /* Transmit complete */ |
---|
374 | #define QSMCM_SCI_RDRF (1<<6) /* Receive data register full */ |
---|
375 | #define QSMCM_SCI_RAF (1<<5) /* Receiver active flag */ |
---|
376 | #define QSMCM_SCI_IDLE (1<<4) /* Idle line detected */ |
---|
377 | #define QSMCM_SCI_OR (1<<3) /* Receiver overrun error */ |
---|
378 | #define QSMCM_SCI_NF (1<<2) /* Receiver noise error flag */ |
---|
379 | #define QSMCM_SCI_FE (1<<1) /* Receiver framing error */ |
---|
380 | #define QSMCM_SCI_PF (1<<0) /* Receiver parity error */ |
---|
381 | |
---|
382 | /* |
---|
383 | ************************************************************************* |
---|
384 | * Unified System Interface Unit * |
---|
385 | ************************************************************************* |
---|
386 | */ |
---|
387 | |
---|
388 | /* |
---|
389 | * Memory controller registers |
---|
390 | */ |
---|
391 | typedef struct m5xxMEMCRegisters_ { |
---|
392 | rtems_unsigned32 _br; |
---|
393 | rtems_unsigned32 _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ |
---|
394 | } m5xxMEMCRegisters_t; |
---|
395 | |
---|
396 | /* |
---|
397 | * USIU itself |
---|
398 | */ |
---|
399 | typedef struct usiu_ { |
---|
400 | /* |
---|
401 | * SIU Block |
---|
402 | */ |
---|
403 | rtems_unsigned32 siumcr; |
---|
404 | rtems_unsigned32 sypcr; |
---|
405 | rtems_unsigned32 _pad70; |
---|
406 | rtems_unsigned16 _pad0; |
---|
407 | rtems_unsigned16 swsr; |
---|
408 | rtems_unsigned32 sipend; |
---|
409 | rtems_unsigned32 simask; |
---|
410 | rtems_unsigned32 siel; |
---|
411 | rtems_unsigned32 sivec; |
---|
412 | rtems_unsigned32 tesr; |
---|
413 | rtems_unsigned32 sgpiodt1; |
---|
414 | rtems_unsigned32 sgpiodt2; |
---|
415 | rtems_unsigned32 sgpiocr; |
---|
416 | rtems_unsigned32 emcr; |
---|
417 | rtems_unsigned8 _pad71[0x03C-0x034]; |
---|
418 | rtems_unsigned32 pdmcr; |
---|
419 | rtems_unsigned8 _pad2[0x100-0x40]; |
---|
420 | |
---|
421 | /* |
---|
422 | * MEMC Block |
---|
423 | */ |
---|
424 | m5xxMEMCRegisters_t memc[4]; |
---|
425 | rtems_unsigned8 _pad7[0x140-0x120]; |
---|
426 | rtems_unsigned32 dmbr; |
---|
427 | rtems_unsigned32 dmor; |
---|
428 | rtems_unsigned8 _pad8[0x178-0x148]; |
---|
429 | rtems_unsigned16 mstat; |
---|
430 | rtems_unsigned8 _pad9[0x200-0x17A]; |
---|
431 | |
---|
432 | /* |
---|
433 | * System integration timers |
---|
434 | */ |
---|
435 | rtems_unsigned16 tbscr; |
---|
436 | rtems_unsigned16 _pad10; |
---|
437 | rtems_unsigned32 tbreff0; |
---|
438 | rtems_unsigned32 tbreff1; |
---|
439 | rtems_unsigned8 _pad11[0x220-0x20c]; |
---|
440 | rtems_unsigned16 rtcsc; |
---|
441 | rtems_unsigned16 _pad12; |
---|
442 | rtems_unsigned32 rtc; |
---|
443 | rtems_unsigned32 rtsec; |
---|
444 | rtems_unsigned32 rtcal; |
---|
445 | rtems_unsigned32 _pad13[4]; |
---|
446 | rtems_unsigned16 piscr; |
---|
447 | rtems_unsigned16 _pad14; |
---|
448 | rtems_unsigned16 pitc; |
---|
449 | rtems_unsigned16 _pad_14_1; |
---|
450 | rtems_unsigned16 pitr; |
---|
451 | rtems_unsigned16 _pad_14_2; |
---|
452 | rtems_unsigned8 _pad15[0x280-0x24c]; |
---|
453 | |
---|
454 | /* |
---|
455 | * Clocks and Reset |
---|
456 | */ |
---|
457 | rtems_unsigned32 sccr; |
---|
458 | rtems_unsigned32 plprcr; |
---|
459 | rtems_unsigned16 rsr; |
---|
460 | rtems_unsigned16 _pad72; |
---|
461 | rtems_unsigned16 colir; |
---|
462 | rtems_unsigned16 _pad73; |
---|
463 | rtems_unsigned16 vsrmcr; |
---|
464 | rtems_unsigned8 _pad16[0x300-0x292]; |
---|
465 | |
---|
466 | /* |
---|
467 | * System integration timers keys |
---|
468 | */ |
---|
469 | rtems_unsigned32 tbscrk; |
---|
470 | rtems_unsigned32 tbreff0k; |
---|
471 | rtems_unsigned32 tbreff1k; |
---|
472 | rtems_unsigned32 tbk; |
---|
473 | rtems_unsigned32 _pad17[4]; |
---|
474 | rtems_unsigned32 rtcsk; |
---|
475 | rtems_unsigned32 rtck; |
---|
476 | rtems_unsigned32 rtseck; |
---|
477 | rtems_unsigned32 rtcalk; |
---|
478 | rtems_unsigned32 _pad18[4]; |
---|
479 | rtems_unsigned32 piscrk; |
---|
480 | rtems_unsigned32 pitck; |
---|
481 | rtems_unsigned8 _pad19[0x380-0x348]; |
---|
482 | |
---|
483 | /* |
---|
484 | * Clocks and Reset Keys |
---|
485 | */ |
---|
486 | rtems_unsigned32 sccrk; |
---|
487 | rtems_unsigned32 plprck; |
---|
488 | rtems_unsigned32 rsrk; |
---|
489 | rtems_unsigned8 _pad20[0x400-0x38c]; |
---|
490 | } usiu_t; |
---|
491 | |
---|
492 | extern volatile usiu_t usiu; /* defined in linkcmds */ |
---|
493 | |
---|
494 | /* |
---|
495 | ************************************************************************* |
---|
496 | * Inter-Module Bus and Devices * |
---|
497 | ************************************************************************* |
---|
498 | */ |
---|
499 | |
---|
500 | /* |
---|
501 | * Dual-Port TPU RAM (DPTRAM) |
---|
502 | */ |
---|
503 | typedef struct m5xxDPTRAMRegisters_ { |
---|
504 | rtems_unsigned8 pad[0x4000]; /* define later */ |
---|
505 | } m5xxDPTRAMRegisters_t; |
---|
506 | |
---|
507 | /* |
---|
508 | * Time Processor Unit (TPU) |
---|
509 | */ |
---|
510 | typedef struct m5xxTPU3Registers_ { |
---|
511 | rtems_unsigned8 pad[0x400]; /* define later */ |
---|
512 | } m5xxTPU3Registers_t; |
---|
513 | |
---|
514 | /* |
---|
515 | * Queued A/D Converter (QADC) |
---|
516 | */ |
---|
517 | typedef struct m5xxQADC64Registers_ { |
---|
518 | rtems_unsigned8 pad[0x400]; /* define later */ |
---|
519 | } m5xxQADC64Registers_t; |
---|
520 | |
---|
521 | /* |
---|
522 | * Serial Communications Interface (SCI) |
---|
523 | */ |
---|
524 | typedef struct m5xxSCIRegisters_ { |
---|
525 | rtems_unsigned16 sccr0; |
---|
526 | rtems_unsigned16 sccr1; |
---|
527 | rtems_unsigned16 scsr; |
---|
528 | rtems_unsigned16 scdr; |
---|
529 | } m5xxSCIRegisters_t; |
---|
530 | |
---|
531 | /* |
---|
532 | * Serial Peripheral Interface (SPI) |
---|
533 | */ |
---|
534 | typedef struct m5xxSPIRegisters_ { |
---|
535 | rtems_unsigned16 spcr0; |
---|
536 | rtems_unsigned16 spcr1; |
---|
537 | rtems_unsigned16 spcr2; |
---|
538 | rtems_unsigned8 spcr3; |
---|
539 | rtems_unsigned8 spsr; |
---|
540 | } m5xxSPIRegisters_t; |
---|
541 | |
---|
542 | /* |
---|
543 | * Queued Serial Multi-Channel Module (QSMCM) |
---|
544 | */ |
---|
545 | typedef struct m5xxQSMCMRegisters_ { |
---|
546 | rtems_unsigned16 qsmcmmcr; |
---|
547 | rtems_unsigned16 qtest; |
---|
548 | rtems_unsigned16 qdsci_il; |
---|
549 | rtems_unsigned16 qspi_il; |
---|
550 | |
---|
551 | m5xxSCIRegisters_t sci1; |
---|
552 | |
---|
553 | rtems_unsigned8 _pad10[0x14-0x10]; |
---|
554 | |
---|
555 | rtems_unsigned16 portqs; |
---|
556 | rtems_unsigned16 pqspar; |
---|
557 | m5xxSPIRegisters_t spi; |
---|
558 | |
---|
559 | m5xxSCIRegisters_t sci2; |
---|
560 | |
---|
561 | rtems_unsigned16 qsci1cr; |
---|
562 | rtems_unsigned16 qsci1sr; |
---|
563 | rtems_unsigned16 sctq[0x10]; |
---|
564 | rtems_unsigned16 scrq[0x10]; |
---|
565 | |
---|
566 | rtems_unsigned8 _pad6C[0x140-0x06C]; |
---|
567 | |
---|
568 | rtems_unsigned16 recram[0x20]; |
---|
569 | rtems_unsigned16 tranram[0x20]; |
---|
570 | rtems_unsigned16 comdram[0x20]; |
---|
571 | } m5xxQSMCMRegisters_t; |
---|
572 | |
---|
573 | /* |
---|
574 | * Modular Input/Output System (MIOS) |
---|
575 | */ |
---|
576 | typedef struct m5xxMIOS1Registers_ { |
---|
577 | rtems_unsigned8 pad[0x1000]; /* define later */ |
---|
578 | } m5xxMIOS1Registers_t; |
---|
579 | |
---|
580 | /* |
---|
581 | * Can 2.0B Controller (TouCAN) |
---|
582 | */ |
---|
583 | typedef struct m5xxTouCANRegisters_ { |
---|
584 | rtems_unsigned8 pad[0x400]; /* define later */ |
---|
585 | } m5xxTouCANRegisters_t; |
---|
586 | |
---|
587 | /* |
---|
588 | * U-Bus to IMB3 Bus Interface Module (UIMB) |
---|
589 | */ |
---|
590 | typedef struct m5xxUIMBRegisters_ { |
---|
591 | rtems_unsigned32 umcr; |
---|
592 | rtems_unsigned32 utstcreg; |
---|
593 | rtems_unsigned32 uipend; |
---|
594 | } m5xxUIMBRegisters_t; |
---|
595 | |
---|
596 | /* |
---|
597 | * IMB itself |
---|
598 | */ |
---|
599 | typedef struct imb_ { |
---|
600 | m5xxDPTRAMRegisters_t dptram; |
---|
601 | m5xxTPU3Registers_t tpu[2]; |
---|
602 | m5xxQADC64Registers_t qadc[2]; |
---|
603 | m5xxQSMCMRegisters_t qsmcm; |
---|
604 | rtems_unsigned8 _pad5200[0x6000-0x5200]; |
---|
605 | m5xxMIOS1Registers_t mios; |
---|
606 | m5xxTouCANRegisters_t toucan[2]; |
---|
607 | rtems_unsigned8 _pad7800[0x7F80-0x7800]; |
---|
608 | m5xxUIMBRegisters_t uimb; |
---|
609 | } imb_t; |
---|
610 | |
---|
611 | extern volatile imb_t imb; /* defined in linkcmds */ |
---|
612 | |
---|
613 | |
---|
614 | #ifdef __cplusplus |
---|
615 | } |
---|
616 | #endif |
---|
617 | |
---|
618 | #endif /* ASM */ |
---|
619 | |
---|
620 | #endif /* _MPC5xx_h */ |
---|
621 | |
---|