source: rtems/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c @ 73b5bd5d

4.104.114.84.95
Last change on this file since 73b5bd5d was f0f1641, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 13, 2004 at 10:03:32 AM

2004-04-13 Ralf Corsepius <ralf_corsepius@…>

  • mpc505/ictrl/ictrl.c, mpc505/vectors/vectors.S, mpc6xx/exceptions/raw_exception.c, mpc8260/exceptions/raw_exception.c, mpc8xx/exceptions/raw_exception.c, rtems/powerpc/cache.h, mpc5xx/ictrl/ictrl.c, mpc5xx/exceptions/raw_exception.c: Include <rtems/score/powerpc.h> instead of <rtems/score/ppc.h>.
  • Property mode set to 100644
File size: 1.2 KB
Line 
1/*
2 * mpc505/509 external interrupt controller management.
3 */
4
5#include "ictrl.h"
6
7#include <rtems.h>
8#include <rtems/score/powerpc.h>
9
10/*
11 * Internal routines.
12 */
13
14static unsigned long volatile *const IRQAND     =
15              (unsigned long volatile *const)0x8007EFA4;
16
17static void nullHandler()
18{
19}
20
21/* Interrupt dispatch table. */
22static ExtIsrHandler extIrqHandlers[NUM_IRQS] =
23{
24  nullHandler,
25  nullHandler,
26  nullHandler,
27  nullHandler,
28  nullHandler,
29  nullHandler,
30  nullHandler
31};
32
33
34/* RTEMS external interrupt handler. Calls installed external interrupt
35   handlers for every pending external interrupt in turn. */
36static rtems_isr extIsr_( rtems_vector_number i )
37{
38#define BIT_NUMBER(val, bit) \
39    asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
40
41  int bit;
42  (void)i;
43
44  BIT_NUMBER(*IRQAND & IMASK_ALL, bit);
45  while ( bit < NUM_IRQS ) {
46    extIrqHandlers[bit]();
47    BIT_NUMBER(*IRQAND & IMASK_ALL, bit);
48  }
49}
50
51/*
52 * Public routines
53 */
54
55void extIrqSetHandler(ExtInt interrupt,ExtIsrHandler handler)
56{
57  extIrqHandlers[interrupt] = handler;
58}
59
60void extIsrInit( void )
61{
62  int i = 0;
63
64  extIrqDisable(IMASK_ALL);
65  for( i = 0; i < NUM_IRQS; i++)
66    extIrqHandlers[i] = nullHandler;
67  set_vector(extIsr_,PPC_IRQ_EXTERNAL,1);
68}
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