1 | /* |
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2 | * General Serial I/O functions. |
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3 | * |
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4 | * This file contains the functions for performing serial I/O. The actual |
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5 | * system calls (console_*) should be in the BSP part of the source tree. |
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6 | * That way different BSPs can use whichever SCI they wish for /dev/console. |
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7 | * |
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8 | * On-chip resources used: |
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9 | * resource minor note |
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10 | * SCI1 0 |
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11 | * SCI2 1 |
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12 | * |
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13 | * |
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14 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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15 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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16 | * |
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17 | * Derived from |
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18 | * c/src/lib/libcpu/powerpc/mpc8xx/console_generic/console_generic.c: |
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19 | * Author: Jay Monkman (jmonkman@frasca.com) |
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20 | * Copyright (C) 1998 by Frasca International, Inc. |
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21 | * |
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22 | * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c written by: |
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23 | * W. Eric Norum |
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24 | * Saskatchewan Accelerator Laboratory |
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25 | * University of Saskatchewan |
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26 | * Saskatoon, Saskatchewan, CANADA |
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27 | * eric@skatter.usask.ca |
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28 | * |
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29 | * COPYRIGHT (c) 1989-1998. |
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30 | * On-Line Applications Research Corporation (OAR). |
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31 | * |
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32 | * Modifications by Darlene Stewart <Darlene.Stewart@iit.nrc.ca> |
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33 | * and Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca> |
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34 | * Copyright (c) 1999, National Research Council of Canada |
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35 | * |
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36 | * The license and distribution terms for this file may be |
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37 | * found in the file LICENSE in this distribution or at |
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38 | * |
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39 | * http://www.rtems.com/license/LICENSE. |
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40 | * |
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41 | * $Id$ |
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42 | */ |
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43 | |
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44 | #include <stdlib.h> |
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45 | #include <unistd.h> |
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46 | #include <termios.h> |
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47 | #include <rtems.h> |
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48 | #include <rtems/libio.h> |
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49 | #include <rtems/bspIo.h> /* for printk */ |
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50 | #include <mpc5xx.h> |
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51 | #include <mpc5xx/console.h> |
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52 | #include <libcpu/irq.h> |
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53 | |
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54 | |
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55 | extern rtems_cpu_table Cpu_table; /* for CPU clock speed */ |
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56 | |
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57 | /* |
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58 | * SCI port descriptor table. |
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59 | */ |
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60 | typedef struct |
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61 | { |
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62 | volatile m5xxSCIRegisters_t *regs; /* hardware registers */ |
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63 | struct rtems_termios_tty *ttyp; /* termios data for this port */ |
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64 | } sci_desc; |
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65 | |
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66 | static sci_desc sci_descs[] = { |
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67 | { &imb.qsmcm.sci1, 0 }, /* SCI 1 */ |
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68 | { &imb.qsmcm.sci2, 0 }, /* SCI 2 */ |
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69 | }; |
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70 | |
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71 | /* |
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72 | * Number of SCI port initialization calls made so far. Used to avoid |
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73 | * installing the common interrupt handler more than once. |
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74 | */ |
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75 | int init_calls = 0; |
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76 | |
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77 | /* |
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78 | * Default configuration. |
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79 | */ |
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80 | static struct termios default_termios = { |
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81 | 0, /* input mode flags */ |
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82 | 0, /* output mode flags */ |
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83 | CS8 | CREAD | CLOCAL | B9600, /* control mode flags */ |
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84 | 0, /* local mode flags */ |
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85 | 0, /* line discipline */ |
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86 | { 0 } /* control characters */ |
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87 | }; |
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88 | |
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89 | |
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90 | /* |
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91 | * Termios callback functions |
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92 | */ |
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93 | |
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94 | int |
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95 | m5xx_uart_firstOpen( |
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96 | int major, |
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97 | int minor, |
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98 | void *arg |
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99 | ) |
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100 | { |
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101 | rtems_libio_open_close_args_t *args = arg; |
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102 | sci_desc* desc = &sci_descs[minor]; |
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103 | struct rtems_termios_tty *tty = args->iop->data1; |
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104 | |
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105 | desc->ttyp = tty; /* connect tty */ |
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106 | if ( tty->device.outputUsesInterrupts == TERMIOS_IRQ_DRIVEN) |
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107 | desc->regs->sccr1 |= QSMCM_SCI_RIE; /* enable rx interrupt */ |
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108 | |
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109 | return RTEMS_SUCCESSFUL; |
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110 | } |
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111 | |
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112 | int |
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113 | m5xx_uart_lastClose( |
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114 | int major, |
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115 | int minor, |
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116 | void* arg |
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117 | ) |
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118 | { |
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119 | sci_desc* desc = &sci_descs[minor]; |
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120 | |
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121 | desc->regs->sccr1 &= ~(QSMCM_SCI_RIE | QSMCM_SCI_TIE); /* disable all */ |
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122 | desc->ttyp = NULL; /* disconnect tty */ |
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123 | |
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124 | return RTEMS_SUCCESSFUL; |
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125 | } |
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126 | |
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127 | int |
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128 | m5xx_uart_pollRead( |
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129 | int minor |
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130 | ) |
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131 | { |
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132 | volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs; |
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133 | int c = -1; |
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134 | |
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135 | if ( regs ) { |
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136 | while ( (regs->scsr & QSMCM_SCI_RDRF) == 0 ) |
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137 | ; |
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138 | c = regs->scdr; |
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139 | } |
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140 | |
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141 | return c; |
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142 | } |
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143 | |
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144 | int |
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145 | m5xx_uart_write( |
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146 | int minor, |
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147 | const char *buf, |
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148 | int len |
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149 | ) |
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150 | { |
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151 | volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs; |
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152 | |
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153 | regs->scdr = *buf; /* start transmission */ |
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154 | regs->sccr1 |= QSMCM_SCI_TIE; /* enable interrupt */ |
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155 | return 0; |
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156 | } |
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157 | |
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158 | int |
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159 | m5xx_uart_pollWrite( |
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160 | int minor, |
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161 | const char *buf, |
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162 | int len |
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163 | ) |
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164 | { |
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165 | volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs; |
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166 | |
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167 | while ( len-- ) { |
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168 | while ( (regs->scsr & QSMCM_SCI_TDRE) == 0 ) |
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169 | ; |
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170 | regs->scdr = *buf++; |
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171 | } |
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172 | return 0; |
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173 | } |
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174 | |
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175 | void |
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176 | m5xx_uart_reserve_resources( |
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177 | rtems_configuration_table *configuration |
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178 | ) |
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179 | { |
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180 | rtems_termios_reserve_resources (configuration, NUM_PORTS); |
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181 | } |
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182 | |
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183 | int |
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184 | m5xx_uart_setAttributes( |
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185 | int minor, |
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186 | const struct termios *t |
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187 | ) |
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188 | { |
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189 | uint16_t sccr0 = sci_descs[minor].regs->sccr0; |
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190 | uint16_t sccr1 = sci_descs[minor].regs->sccr1; |
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191 | int baud; |
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192 | |
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193 | /* |
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194 | * Check that port number is valid |
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195 | */ |
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196 | if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) |
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197 | return RTEMS_INVALID_NUMBER; |
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198 | |
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199 | /* Baud rate */ |
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200 | switch (t->c_cflag & CBAUD) { |
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201 | default: baud = -1; break; |
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202 | case B50: baud = 50; break; |
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203 | case B75: baud = 75; break; |
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204 | case B110: baud = 110; break; |
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205 | case B134: baud = 134; break; |
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206 | case B150: baud = 150; break; |
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207 | case B200: baud = 200; break; |
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208 | case B300: baud = 300; break; |
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209 | case B600: baud = 600; break; |
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210 | case B1200: baud = 1200; break; |
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211 | case B1800: baud = 1800; break; |
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212 | case B2400: baud = 2400; break; |
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213 | case B4800: baud = 4800; break; |
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214 | case B9600: baud = 9600; break; |
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215 | case B19200: baud = 19200; break; |
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216 | case B38400: baud = 38400; break; |
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217 | case B57600: baud = 57600; break; |
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218 | case B115200: baud = 115200; break; |
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219 | case B230400: baud = 230400; break; |
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220 | case B460800: baud = 460800; break; |
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221 | } |
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222 | if (baud > 0) { |
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223 | extern uint32_t bsp_clock_speed; |
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224 | sccr0 &= ~QSMCM_SCI_BAUD(-1); |
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225 | sccr0 |= |
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226 | QSMCM_SCI_BAUD((bsp_clock_speed + (16 * baud)) / (32 * baud)); |
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227 | } |
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228 | |
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229 | /* Number of data bits -- not available with MPC5xx SCI */ |
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230 | switch ( t->c_cflag & CSIZE ) { |
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231 | case CS5: break; |
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232 | case CS6: break; |
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233 | case CS7: break; |
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234 | case CS8: break; |
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235 | } |
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236 | |
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237 | /* Stop bits -- not easily available with MPC5xx SCI */ |
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238 | if ( t->c_cflag & CSTOPB ) { |
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239 | /* Two stop bits */ |
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240 | } else { |
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241 | /* One stop bit */ |
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242 | } |
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243 | |
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244 | /* Parity */ |
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245 | if ( t->c_cflag & PARENB ) |
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246 | sccr1 |= QSMCM_SCI_PE; |
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247 | else |
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248 | sccr1 &= ~QSMCM_SCI_PE; |
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249 | |
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250 | if ( t->c_cflag & PARODD ) |
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251 | sccr1 |= QSMCM_SCI_PT; |
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252 | else |
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253 | sccr1 &= ~QSMCM_SCI_PT; |
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254 | |
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255 | /* Transmitter and receiver enable */ |
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256 | sccr1 |= QSMCM_SCI_TE; |
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257 | if ( t->c_cflag & CREAD ) |
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258 | sccr1 |= QSMCM_SCI_RE; |
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259 | else |
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260 | sccr1 &= ~QSMCM_SCI_RE; |
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261 | |
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262 | /* Write hardware registers */ |
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263 | sci_descs[minor].regs->sccr0 = sccr0; |
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264 | sci_descs[minor].regs->sccr1 = sccr1; |
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265 | |
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266 | return RTEMS_SUCCESSFUL; |
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267 | } |
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268 | |
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269 | |
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270 | /* |
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271 | * Interrupt handling. |
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272 | */ |
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273 | static void |
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274 | m5xx_sci_interrupt_handler (rtems_irq_hdl_param unused) |
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275 | { |
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276 | int minor; |
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277 | |
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278 | for ( minor = 0; minor < NUM_PORTS; minor++ ) { |
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279 | sci_desc *desc = &sci_descs[minor]; |
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280 | int sccr1 = desc->regs->sccr1; |
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281 | int scsr = desc->regs->scsr; |
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282 | |
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283 | /* |
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284 | * Character received? |
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285 | */ |
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286 | if ((sccr1 & QSMCM_SCI_RIE) && (scsr & QSMCM_SCI_RDRF)) { |
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287 | char c = desc->regs->scdr; |
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288 | rtems_termios_enqueue_raw_characters(desc->ttyp, &c, 1); |
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289 | } |
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290 | /* |
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291 | * Transmitter empty? |
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292 | */ |
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293 | if ((sccr1 & QSMCM_SCI_TIE) && (scsr & QSMCM_SCI_TDRE)) { |
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294 | desc->regs->sccr1 &= ~QSMCM_SCI_TIE; |
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295 | rtems_termios_dequeue_characters (desc->ttyp, 1); |
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296 | } |
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297 | } |
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298 | } |
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299 | |
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300 | void m5xx_sci_nop(const rtems_irq_connect_data* ptr) |
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301 | { |
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302 | } |
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303 | |
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304 | int m5xx_sci_isOn(const rtems_irq_connect_data* ptr) |
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305 | { |
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306 | return 1; |
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307 | } |
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308 | |
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309 | /* |
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310 | * Basic initialization. |
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311 | */ |
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312 | |
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313 | void |
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314 | m5xx_uart_initialize (int minor) |
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315 | { |
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316 | /* |
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317 | * Check that minor number is valid. |
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318 | */ |
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319 | if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) |
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320 | return; |
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321 | |
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322 | /* |
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323 | * Configure and enable receiver and transmitter. |
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324 | */ |
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325 | m5xx_uart_setAttributes(minor, &default_termios); |
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326 | |
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327 | /* |
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328 | * Connect interrupt if not yet done. |
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329 | */ |
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330 | if ( init_calls++ == 0 ) { |
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331 | rtems_irq_connect_data irq_data; |
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332 | |
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333 | irq_data.name = CPU_IRQ_SCI; |
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334 | irq_data.hdl = m5xx_sci_interrupt_handler; |
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335 | irq_data.on = m5xx_sci_nop; /* can't enable both channels here */ |
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336 | irq_data.off = m5xx_sci_nop; /* can't disable both channels here */ |
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337 | irq_data.isOn = m5xx_sci_isOn; |
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338 | |
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339 | if (!CPU_install_rtems_irq_handler (&irq_data)) { |
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340 | printk("Unable to connect SCI Irq handler\n"); |
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341 | rtems_fatal_error_occurred(1); |
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342 | } |
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343 | |
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344 | imb.qsmcm.qdsci_il = /* set interrupt level in port */ |
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345 | QSMCM_ILDSCI(CPU_irq_level_from_symbolic_name(CPU_IRQ_SCI)); |
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346 | } |
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347 | } |
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