1 | /* clock.c |
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2 | * |
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3 | * This routine initializes the PIT on the MPC5xx. |
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4 | * The tick frequency is specified by the bsp. |
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5 | * |
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6 | * |
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7 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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8 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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9 | * |
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10 | * Derived from c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c: |
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11 | * |
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12 | * Author: Jay Monkman (jmonkman@frasca.com) |
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13 | * Copyright (C) 1998 by Frasca International, Inc. |
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14 | * |
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15 | * Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: |
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16 | * |
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17 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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18 | * |
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19 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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20 | * |
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21 | * To anyone who acknowledges that this file is provided "AS IS" |
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22 | * without any express or implied warranty: |
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23 | * permission to use, copy, modify, and distribute this file |
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24 | * for any purpose is hereby granted without fee, provided that |
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25 | * the above copyright notice and this notice appears in all |
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26 | * copies, and that the name of i-cubed limited not be used in |
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27 | * advertising or publicity pertaining to distribution of the |
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28 | * software without specific, written prior permission. |
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29 | * i-cubed limited makes no representations about the suitability |
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30 | * of this software for any purpose. |
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31 | * |
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32 | * Derived from c/src/lib/libcpu/hppa1_1/clock/clock.c: |
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33 | * |
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34 | * COPYRIGHT (c) 1989-2007. |
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35 | * On-Line Applications Research Corporation (OAR). |
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36 | * |
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37 | * The license and distribution terms for this file may be |
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38 | * found in the file LICENSE in this distribution or at |
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39 | * http://www.rtems.com/license/LICENSE. |
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40 | * |
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41 | * $Id$ |
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42 | */ |
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43 | |
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44 | #include <rtems.h> |
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45 | #include <rtems/clockdrv.h> |
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46 | #include <rtems/libio.h> |
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47 | #include <libcpu/irq.h> |
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48 | |
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49 | #include <stdlib.h> /* for atexit() */ |
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50 | #include <mpc5xx.h> |
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51 | |
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52 | volatile uint32_t Clock_driver_ticks; |
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53 | extern int BSP_connect_clock_handler(rtems_isr_entry); |
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54 | extern int BSP_disconnect_clock_handler(); |
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55 | |
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56 | void Clock_exit( void ); |
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57 | |
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58 | /* |
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59 | * These are set by clock driver during its init |
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60 | */ |
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61 | |
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62 | rtems_device_major_number rtems_clock_major = ~0; |
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63 | rtems_device_minor_number rtems_clock_minor; |
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64 | |
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65 | /* |
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66 | * ISR Handler |
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67 | */ |
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68 | rtems_isr Clock_isr(rtems_vector_number vector) |
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69 | { |
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70 | usiu.piscrk = USIU_UNLOCK_KEY; |
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71 | usiu.piscr |= USIU_PISCR_PS; /* acknowledge interrupt */ |
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72 | usiu.piscrk = 0; |
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73 | |
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74 | Clock_driver_ticks++; |
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75 | rtems_clock_tick(); |
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76 | } |
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77 | |
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78 | void clockOn(void* unused) |
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79 | { |
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80 | unsigned desiredLevel; |
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81 | uint32_t pit_value; |
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82 | extern uint32_t bsp_clicks_per_usec; |
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83 | |
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84 | /* calculate and set modulus */ |
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85 | pit_value = (rtems_configuration_get_microseconds_per_tick() * |
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86 | bsp_clicks_per_usec) - 1 ; |
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87 | |
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88 | if (pit_value > 0xffff) { /* pit is only 16 bits long */ |
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89 | rtems_fatal_error_occurred(-1); |
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90 | } |
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91 | usiu.sccrk = USIU_UNLOCK_KEY; |
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92 | usiu.sccr &= ~USIU_SCCR_RTDIV; /* RTC and PIT clock is divided by 4 */ |
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93 | usiu.sccrk = 0; |
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94 | |
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95 | usiu.pitck = USIU_UNLOCK_KEY; |
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96 | usiu.pitc = pit_value; |
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97 | usiu.pitck = 0; |
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98 | |
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99 | /* set PIT irq level, enable PIT, PIT interrupts */ |
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100 | /* and clear int. status */ |
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101 | desiredLevel = CPU_irq_level_from_symbolic_name(CPU_PERIODIC_TIMER); |
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102 | |
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103 | usiu.piscrk = USIU_UNLOCK_KEY; |
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104 | usiu.piscr = USIU_PISCR_PIRQ(desiredLevel) /* set interrupt priority */ |
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105 | | USIU_PISCR_PS /* acknowledge interrupt */ |
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106 | | USIU_PISCR_PIE /* enable interrupt */ |
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107 | | USIU_PISCR_PITF /* freeze during debug */ |
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108 | | USIU_PISCR_PTE; /* enable timer */ |
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109 | usiu.piscrk = 0; |
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110 | } |
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111 | |
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112 | void |
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113 | clockOff(void* unused) |
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114 | { |
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115 | /* disable PIT and PIT interrupts */ |
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116 | usiu.piscrk = USIU_UNLOCK_KEY; |
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117 | usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE); |
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118 | usiu.piscrk = 0; |
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119 | } |
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120 | |
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121 | int clockIsOn(void* unused) |
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122 | { |
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123 | if (usiu.piscr & USIU_PISCR_PIE) |
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124 | return 1; |
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125 | return 0; |
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126 | } |
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127 | |
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128 | /* |
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129 | * Called via atexit() |
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130 | * Remove the clock interrupt handler by setting handler to NULL |
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131 | */ |
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132 | void |
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133 | Clock_exit(void) |
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134 | { |
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135 | (void) BSP_disconnect_clock_handler (); |
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136 | } |
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137 | |
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138 | void Install_clock(rtems_isr_entry clock_isr) |
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139 | { |
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140 | Clock_driver_ticks = 0; |
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141 | |
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142 | BSP_connect_clock_handler (clock_isr); |
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143 | atexit(Clock_exit); |
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144 | } |
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145 | |
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146 | void |
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147 | ReInstall_clock(rtems_isr_entry new_clock_isr) |
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148 | { |
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149 | BSP_connect_clock_handler (new_clock_isr); |
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150 | } |
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151 | |
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152 | |
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153 | rtems_device_driver Clock_initialize( |
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154 | rtems_device_major_number major, |
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155 | rtems_device_minor_number minor, |
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156 | void *pargp |
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157 | ) |
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158 | { |
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159 | Install_clock( Clock_isr ); |
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160 | |
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161 | /* |
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162 | * make major/minor avail to others such as shared memory driver |
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163 | */ |
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164 | |
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165 | rtems_clock_major = major; |
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166 | rtems_clock_minor = minor; |
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167 | |
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168 | return RTEMS_SUCCESSFUL; |
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169 | } |
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