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source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h @ 29313369

4.104.115

Last change on this file since 29313369 was 29313369, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 04/07/10 at 06:45:59
changes to support GW_LCFM
Property mode set to `100644`
File size: 157.9 KB

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1	/**
2	* @file
3	*
4	* @ingroup mpc55xx
5	*
6	* @brief Register definitions for the MPC55XX microcontroller family
7	*
8	* This file is based on the mpc5566.h header file provided by Freescale Semiconductor, INC.
9	* with some added fields/structures/definitions for MPC5510
10	*/
11
12	/* to get the chip derivate... */
13	#include <bspopts.h>
14
15	/*
16	* Copyright (c) 2008
17	* Embedded Brains GmbH
18	* Obere Lagerstr. 30
19	* D-82178 Puchheim
20	* Germany
21	* rtems@embedded-brains.de
22	*
23	* The license and distribution terms for this file may be found in the file
24	* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
25	*/
26
27	/**************************************************************************/
28	/* FILE NAME: mpc5566.h COPYRIGHT (c) Freescale 2006 */
29	/* VERSION: 1.2 All Rights Reserved */
30	/* */
31	/* DESCRIPTION: */
32	/* This file contain all of the register and bit field definitions for */
33	/* MPC5566. */
34	/========================================================================/
35	/* UPDATE HISTORY */
36	/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
37	/* --- ----------- --------- --------------------- */
38	/* 1.0 S. Mathieson 12/Jul/06 Initial version. */
39	/* 1.1 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */
40	/* Add Flexcan bits WRNEN, SRXDIS, */
41	/* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */
42	/* 1.2 S. Mathieson 10/Aug/06 Removed reference to FlexCAN E */
43	/* SPR: L1CSR0[WAM] & L1CSR0[CORG] Added*/
44	/* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */
45	/* to DPB to align with documentation. */
46	/**************************************************************************/
47
48	#ifndef LIBCPU_POWERPC_MPC55XX_REGS_H
49	#define LIBCPU_POWERPC_MPC55XX_REGS_H
50
51	#include <stdint.h>
52
53	#ifdef __cplusplus
54	extern "C" {
55	#endif
56
57	/****************************************************************************/
58	/* MODULE : PBRIDGE_A Peripheral Bridge */
59	/****************************************************************************/
60	struct PBRIDGE_A_tag {
61	union {
62	uint32_t R;
63	struct {
64	uint32_t MBW0:1;
65	uint32_t MTR0:1;
66	uint32_t MTW0:1;
67	uint32_t MPL0:1;
68	uint32_t MBW1:1;
69	uint32_t MTR1:1;
70	uint32_t MTW1:1;
71	uint32_t MPL1:1;
72	uint32_t MBW2:1;
73	uint32_t MTR2:1;
74	uint32_t MTW2:1;
75	uint32_t MPL2:1;
76	uint32_t MBW3:1;
77	uint32_t MTR3:1;
78	uint32_t MTW3:1;
79	uint32_t MPL3:1;
80
81	uint32_t MBW4:1; /* FEC */
82	uint32_t MTR4:1;
83	uint32_t MTW4:1;
84	uint32_t MPL4:1;
85
86	uint32_t:4;
87
88	uint32_t:4;
89
90	uint32_t:4;
91	} B;
92	} MPCR; /* Master Privilege Control Register */
93
94	uint32_t pbridge_a_reserved2[7];
95
96	union {
97	uint32_t R;
98	struct {
99	uint32_t BW0:1;
100	uint32_t SP0:1;
101	uint32_t WP0:1;
102	uint32_t TP0:1;
103	uint32_t:28;
104	} B;
105	} PACR0;
106
107	uint32_t pbridge_a_reserved3[7];
108
109	union {
110	uint32_t R;
111	struct {
112	uint32_t BW0:1;
113	uint32_t SP0:1;
114	uint32_t WP0:1;
115	uint32_t TP0:1;
116	uint32_t BW1:1;
117	uint32_t SP1:1;
118	uint32_t WP1:1;
119	uint32_t TP1:1;
120	uint32_t BW2:1;
121	uint32_t SP2:1;
122	uint32_t WP2:1;
123	uint32_t TP2:1;
124	uint32_t:4;
125	uint32_t BW4:1;
126	uint32_t SP4:1;
127	uint32_t WP4:1;
128	uint32_t TP4:1;
129	uint32_t:12;
130	} B;
131	} OPACR0;
132
133	union {
134	uint32_t R;
135	struct {
136
137	uint32_t BW0:1; /* EMIOS */
138	uint32_t SP0:1;
139	uint32_t WP0:1;
140	uint32_t TP0:1;
141
142	uint32_t:28;
143	} B;
144	} OPACR1;
145
146	union {
147	uint32_t R;
148	struct {
149	uint32_t BW0:1;
150	uint32_t SP0:1;
151	uint32_t WP0:1;
152	uint32_t TP0:1;
153	uint32_t:4;
154	uint32_t BW2:1;
155	uint32_t SP2:1;
156	uint32_t WP2:1;
157	uint32_t TP2:1;
158	uint32_t BW3:1;
159	uint32_t SP3:1;
160	uint32_t WP3:1;
161	uint32_t TP3:1;
162	uint32_t BW4:1;
163	uint32_t SP4:1;
164	uint32_t WP4:1;
165	uint32_t TP4:1;
166	uint32_t:12;
167	} B;
168	} OPACR2;
169
170	};
171
172	/****************************************************************************/
173	/* MODULE : PBRIDGE_B Peripheral Bridge */
174	/****************************************************************************/
175	struct PBRIDGE_B_tag {
176	union {
177	uint32_t R;
178	struct {
179	uint32_t MBW0:1;
180	uint32_t MTR0:1;
181	uint32_t MTW0:1;
182	uint32_t MPL0:1;
183	uint32_t MBW1:1;
184	uint32_t MTR1:1;
185	uint32_t MTW1:1;
186	uint32_t MPL1:1;
187	uint32_t MBW2:1;
188	uint32_t MTR2:1;
189	uint32_t MTW2:1;
190	uint32_t MPL2:1;
191	uint32_t MBW3:1;
192	uint32_t MTR3:1;
193	uint32_t MTW3:1;
194	uint32_t MPL3:1;
195
196	uint32_t MBW4:1; /* FEC */
197	uint32_t MTR4:1;
198	uint32_t MTW4:1;
199	uint32_t MPL4:1;
200
201	uint32_t:4;
202
203	uint32_t:4;
204
205	uint32_t:4;
206	} B;
207	} MPCR; /* Master Privilege Control Register */
208
209	uint32_t pbridge_b_reserved2[7];
210
211	union {
212	uint32_t R;
213	struct {
214	uint32_t BW0:1;
215	uint32_t SP0:1;
216	uint32_t WP0:1;
217	uint32_t TP0:1;
218	uint32_t BW1:1;
219	uint32_t SP1:1;
220	uint32_t WP1:1;
221	uint32_t TP1:1;
222	uint32_t:24;
223	} B;
224	} PACR0;
225
226	uint32_t pbridge_b_reserved3;
227
228	union {
229	uint32_t R;
230	struct {
231	uint32_t BW0:1;
232	uint32_t SP0:1;
233	uint32_t WP0:1;
234	uint32_t TP0:1;
235	uint32_t BW1:1;
236	uint32_t SP1:1;
237	uint32_t WP1:1;
238	uint32_t TP1:1;
239	uint32_t BW2:1;
240	uint32_t SP2:1;
241	uint32_t WP2:1;
242	uint32_t TP2:1;
243
244	uint32_t BW3:1; /* FEC */
245	uint32_t SP3:1;
246	uint32_t WP3:1;
247	uint32_t TP3:1;
248
249	uint32_t:16;
250
251	} B;
252	} PACR2;
253
254	uint32_t pbridge_b_reserved4[5];
255
256	union {
257	uint32_t R;
258	struct {
259	uint32_t BW0:1;
260	uint32_t SP0:1;
261	uint32_t WP0:1;
262	uint32_t TP0:1;
263	uint32_t:12;
264
265	uint32_t BW4:1; /* DSPI_A */
266	uint32_t SP4:1;
267	uint32_t WP4:1;
268	uint32_t TP4:1;
269
270	uint32_t BW5:1; /* DSPI_B */
271	uint32_t SP5:1;
272	uint32_t WP5:1;
273	uint32_t TP5:1;
274
275	uint32_t BW6:1;
276	uint32_t SP6:1;
277	uint32_t WP6:1;
278	uint32_t TP6:1;
279	uint32_t BW7:1;
280	uint32_t SP7:1;
281	uint32_t WP7:1;
282	uint32_t TP7:1;
283	} B;
284	} OPACR0;
285
286	union {
287	uint32_t R;
288	struct {
289	uint32_t:16;
290	uint32_t BW4:1;
291	uint32_t SP4:1;
292	uint32_t WP4:1;
293	uint32_t TP4:1;
294
295	uint32_t BW5:1; /* ESCI_B */
296	uint32_t SP5:1;
297	uint32_t WP5:1;
298	uint32_t TP5:1;
299
300	uint32_t:8;
301	} B;
302	} OPACR1;
303
304	union {
305	uint32_t R;
306	struct {
307	uint32_t BW0:1;
308	uint32_t SP0:1;
309	uint32_t WP0:1;
310	uint32_t TP0:1;
311
312	uint32_t BW1:1; /* CAN_B */
313	uint32_t SP1:1;
314	uint32_t WP1:1;
315	uint32_t TP1:1;
316
317	uint32_t BW2:1;
318	uint32_t SP2:1;
319	uint32_t WP2:1;
320	uint32_t TP2:1;
321
322	uint32_t BW3:1; /* CAN_D */
323	uint32_t SP3:1;
324	uint32_t WP3:1;
325	uint32_t TP3:1;
326	uint32_t:4;
327
328	uint32_t:12;
329	} B;
330	} OPACR2;
331
332	union {
333	uint32_t R;
334	struct {
335
336	uint32_t:4;
337
338	uint32_t:24;
339	uint32_t BW7:1;
340	uint32_t SP7:1;
341	uint32_t WP7:1;
342	uint32_t TP7:1;
343	} B;
344	} OPACR3;
345
346	};
347	/****************************************************************************/
348	/* MODULE : FMPLL */
349	/****************************************************************************/
350	struct FMPLL_tag {
351	union SYNCR_tag {
352	uint32_t R;
353	struct {
354	uint32_t:1;
355	uint32_t PREDIV:3;
356	uint32_t MFD:5;
357	uint32_t:1;
358	uint32_t RFD:3;
359	uint32_t LOCEN:1;
360	uint32_t LOLRE:1;
361	uint32_t LOCRE:1;
362	uint32_t DISCLK:1;
363	uint32_t LOLIRQ:1;
364	uint32_t LOCIRQ:1;
365	uint32_t RATE:1;
366	uint32_t DEPTH:2;
367	uint32_t EXP:10;
368	} B;
369	} SYNCR; /* not present on MPC551x */
370
371	union {
372	uint32_t R;
373	struct {
374	uint32_t:22;
375	uint32_t LOLF:1;
376	uint32_t LOC:1;
377	uint32_t MODE:1;
378	uint32_t PLLSEL:1;
379	uint32_t PLLREF:1;
380	uint32_t LOCKS:1;
381	uint32_t LOCK:1;
382	uint32_t LOCF:1;
383	uint32_t CALDONE:1;
384	uint32_t CALPASS:1;
385	} B;
386	} SYNSR;
387
388	union ESYNCR1_tag {
389	uint32_t R;
390	struct {
391	uint32_t:1;
392	uint32_t CLKCFG:3;
393	uint32_t:8;
394	uint32_t EPREDIV:4;
395	uint32_t :8;
396	uint32_t EMFD:8;
397	} B;
398	} ESYNCR1; /* present on MPC551x */
399
400	union ESYNCR2_tag{
401	uint32_t R;
402	struct {
403	uint32_t:8;
404	uint32_t LOCEN:1;
405	uint32_t LOLRE:1;
406	uint32_t LOCRE:1;
407	uint32_t LOLIRQ:1;
408	uint32_t LOCIRQ:1;
409	uint32_t:1;
410	uint32_t ERATE:2;
411	uint32_t:5;
412	uint32_t DEPTH:3;
413	uint32_t:2;
414	uint32_t ERFD:6;
415	} B;
416	} ESYNCR2; /* present on MPC551x */
417
418	};
419	/****************************************************************************/
420	/* MODULE : External Bus Interface (EBI) */
421	/****************************************************************************/
422	struct EBI_CS_tag {
423	union { /* Base Register Bank */
424	uint32_t R;
425	struct {
426	uint32_t BA:17;
427	uint32_t:3;
428	uint32_t PS:1;
429	uint32_t:3;
430	uint32_t AD_MUX:1; /* only MPC551x */
431	uint32_t BL:1;
432	uint32_t WEBS:1;
433	uint32_t TBDIP:1;
434	uint32_t:2;
435	uint32_t BI:1;
436	uint32_t V:1;
437	} B;
438	} BR;
439
440	union { /* Option Register Bank */
441	uint32_t R;
442	struct {
443	uint32_t AM:17;
444	uint32_t:7;
445	uint32_t SCY:4;
446	uint32_t:1;
447	uint32_t BSCY:2;
448	uint32_t:1;
449	} B;
450	} OR;
451	};
452
453	struct EBI_CAL_CS_tag {
454	union { /* Calibration Base Register Bank */
455	uint32_t R;
456	struct {
457	uint32_t BA:17;
458	uint32_t:3;
459	uint32_t PS:1;
460	uint32_t:4;
461	uint32_t BL:1;
462	uint32_t WEBS:1;
463	uint32_t TBDIP:1;
464	uint32_t:2;
465	uint32_t BI:1;
466	uint32_t V:1;
467	} B;
468	} BR;
469
470	union { /* Calibration Option Register Bank */
471	uint32_t R;
472	struct {
473	uint32_t AM:17;
474	uint32_t:7;
475	uint32_t SCY:4;
476	uint32_t:1;
477	uint32_t BSCY:2;
478	uint32_t:1;
479	} B;
480	} OR;
481	};
482
483	struct EBI_tag {
484	union { /* Module Configuration Register */
485	uint32_t R;
486	struct {
487	uint32_t:5;
488	uint32_t SIZEEN:1;
489	uint32_t SIZE:2;
490	uint32_t:8;
491	uint32_t ACGE:1;
492	uint32_t EXTM:1;
493	uint32_t EARB:1;
494	uint32_t EARP:2;
495	uint32_t:4;
496	uint32_t MDIS:1;
497	uint32_t:3;
498	uint32_t D16_32:1; /* only for MPC551x */
499	uint32_t ADMUX:1; /* only for MPC551x */
500	uint32_t DBM:1;
501	} B;
502	} MCR;
503
504	uint32_t EBI_reserved1;
505
506	union { /* Transfer Error Status Register */
507	uint32_t R;
508	struct {
509	uint32_t:30;
510	uint32_t TEAF:1;
511	uint32_t BMTF:1;
512	} B;
513	} TESR;
514
515	union { /* Bus Monitor Control Register */
516	uint32_t R;
517	struct {
518	uint32_t:16;
519	uint32_t BMT:8;
520	uint32_t BME:1;
521	uint32_t:7;
522	} B;
523	} BMCR;
524
525	struct EBI_CS_tag CS[4];
526
527	/* Calibration registers */
528	uint32_t EBI_reserved2[4];
529	struct EBI_CAL_CS_tag CAL_CS[4];
530
531	};
532	/****************************************************************************/
533	/* MODULE : FLASH */
534	/****************************************************************************/
535	struct FLASH_tag {
536	union { /* Module Configuration Register */
537	uint32_t R;
538	struct {
539	uint32_t:4;
540	uint32_t SIZE:4;
541	uint32_t:1;
542	uint32_t LAS:3;
543	uint32_t:3;
544	uint32_t MAS:1;
545	uint32_t EER:1;
546	uint32_t RWE:1;
547	uint32_t BBEPE:1;
548	uint32_t EPE:1;
549	uint32_t PEAS:1;
550	uint32_t DONE:1;
551	uint32_t PEG:1;
552
553	uint32_t:2;
554
555	uint32_t STOP:1;
556	uint32_t:1;
557	uint32_t PGM:1;
558	uint32_t PSUS:1;
559	uint32_t ERS:1;
560	uint32_t ESUS:1;
561	uint32_t EHV:1;
562	} B;
563	} MCR;
564
565	union { /* LML Register */
566	uint32_t R;
567	struct {
568	uint32_t LME:1;
569	uint32_t:10;
570	uint32_t SLOCK:1;
571	uint32_t MLOCK:4;
572	uint32_t LLOCK:16;
573	} B;
574	} LMLR;
575
576	union { /* HL Register */
577	uint32_t R;
578	struct {
579	uint32_t HBE:1;
580	uint32_t:3;
581	uint32_t HBLOCK:28;
582	} B;
583	} HLR;
584
585	union { /* SLML Register */
586	uint32_t R;
587	struct {
588	uint32_t SLE:1;
589	uint32_t:10;
590	uint32_t SSLOCK:1;
591	uint32_t SMLOCK:4;
592	uint32_t SLLOCK:16;
593	} B;
594	} SLMLR;
595
596	union { /* LMS Register */
597	uint32_t R;
598	struct {
599	uint32_t:12;
600	uint32_t MSEL:4;
601	uint32_t LSEL:16;
602	} B;
603	} LMSR;
604
605	union {
606	uint32_t R;
607	struct {
608	uint32_t:4;
609	uint32_t HBSEL:28;
610	} B;
611	} HSR;
612
613	union {
614	uint32_t R;
615	struct {
616	uint32_t:10;
617	uint32_t ADDR:19;
618	uint32_t:3;
619	} B;
620	} AR;
621
622	union {
623	uint32_t R;
624	struct {
625
626	uint32_t:11;
627
628	uint32_t M4PFE:1; /* FEC */
629
630	uint32_t M3PFE:1;
631	uint32_t M2PFE:1;
632	uint32_t M1PFE:1;
633	uint32_t M0PFE:1;
634	uint32_t APC:3;
635	uint32_t WWSC:2;
636	uint32_t RWSC:3;
637
638	uint32_t DPFEN:2;
639	uint32_t IPFEN:2;
640
641	uint32_t PFLIM:3;
642	uint32_t BFEN:1;
643	} B;
644	} BIUCR;
645
646	union {
647	uint32_t R;
648	struct {
649
650	uint32_t:22;
651
652	uint32_t M4AP:2; /* FEC */
653
654	uint32_t M3AP:2;
655	uint32_t M2AP:2;
656	uint32_t M1AP:2;
657	uint32_t M0AP:2;
658	} B;
659	} BIUAPR;
660	};
661	/****************************************************************************/
662	/* MODULE : SIU */
663	/****************************************************************************/
664	struct SIU_tag {
665	int32_t SIU_reserved0;
666
667	union { /* MCU ID Register */
668	uint32_t R;
669	struct {
670	uint32_t PARTNUM:16;
671	uint32_t MASKNUM:16;
672	} B;
673	} MIDR;
674	int32_t SIU_reserved00;
675
676	union { /* Reset Status Register */
677	uint32_t R;
678	struct {
679	uint32_t PORS:1;
680	uint32_t ERS:1;
681	uint32_t LLRS:1;
682	uint32_t LCRS:1;
683	uint32_t WDRS:1;
684	uint32_t CRS:1;
685	uint32_t:8;
686	uint32_t SSRS:1;
687	uint32_t SERF:1;
688	uint32_t WKPCFG:1;
689	uint32_t:12;
690	uint32_t BOOTCFG:2;
691	uint32_t RGF:1;
692	} B;
693	} RSR;
694
695	union { /* System Reset Control Register */
696	uint32_t R;
697	struct {
698	uint32_t SSR:1;
699	uint32_t SER:1;
700	uint32_t:14;
701	uint32_t CRE:1;
702	uint32_t:15;
703	} B;
704	} SRCR;
705
706	union SIU_EISR_tag { /* External Interrupt Status Register */
707	uint32_t R;
708	struct {
709	uint32_t:16;
710	uint32_t EIF15:1;
711	uint32_t EIF14:1;
712	uint32_t EIF13:1;
713	uint32_t EIF12:1;
714	uint32_t EIF11:1;
715	uint32_t EIF10:1;
716	uint32_t EIF9:1;
717	uint32_t EIF8:1;
718	uint32_t EIF7:1;
719	uint32_t EIF6:1;
720	uint32_t EIF5:1;
721	uint32_t EIF4:1;
722	uint32_t EIF3:1;
723	uint32_t EIF2:1;
724	uint32_t EIF1:1;
725	uint32_t EIF0:1;
726	} B;
727	} EISR;
728
729	union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
730	uint32_t R;
731	struct {
732	uint32_t:16;
733	uint32_t EIRE15:1;
734	uint32_t EIRE14:1;
735	uint32_t EIRE13:1;
736	uint32_t EIRE12:1;
737	uint32_t EIRE11:1;
738	uint32_t EIRE10:1;
739	uint32_t EIRE9:1;
740	uint32_t EIRE8:1;
741	uint32_t EIRE7:1;
742	uint32_t EIRE6:1;
743	uint32_t EIRE5:1;
744	uint32_t EIRE4:1;
745	uint32_t EIRE3:1;
746	uint32_t EIRE2:1;
747	uint32_t EIRE1:1;
748	uint32_t EIRE0:1;
749	} B;
750	} DIRER;
751
752	union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */
753	uint32_t R;
754	struct {
755	uint32_t:28;
756	uint32_t DIRS3:1;
757	uint32_t DIRS2:1;
758	uint32_t DIRS1:1;
759	uint32_t DIRS0:1;
760	} B;
761	} DIRSR;
762
763	union SIU_OSR_tag { /* Overrun Status Register */
764	uint32_t R;
765	struct {
766	uint32_t:16;
767	uint32_t OVF15:1;
768	uint32_t OVF14:1;
769	uint32_t OVF13:1;
770	uint32_t OVF12:1;
771	uint32_t OVF11:1;
772	uint32_t OVF10:1;
773	uint32_t OVF9:1;
774	uint32_t OVF8:1;
775	uint32_t OVF7:1;
776	uint32_t OVF6:1;
777	uint32_t OVF5:1;
778	uint32_t OVF4:1;
779	uint32_t OVF3:1;
780	uint32_t OVF2:1;
781	uint32_t OVF1:1;
782	uint32_t OVF0:1;
783	} B;
784	} OSR;
785
786	union SIU_ORER_tag { /* Overrun Request Enable Register */
787	uint32_t R;
788	struct {
789	uint32_t:16;
790	uint32_t ORE15:1;
791	uint32_t ORE14:1;
792	uint32_t ORE13:1;
793	uint32_t ORE12:1;
794	uint32_t ORE11:1;
795	uint32_t ORE10:1;
796	uint32_t ORE9:1;
797	uint32_t ORE8:1;
798	uint32_t ORE7:1;
799	uint32_t ORE6:1;
800	uint32_t ORE5:1;
801	uint32_t ORE4:1;
802	uint32_t ORE3:1;
803	uint32_t ORE2:1;
804	uint32_t ORE1:1;
805	uint32_t ORE0:1;
806	} B;
807	} ORER;
808
809	union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
810	uint32_t R;
811	struct {
812	uint32_t:16;
813	uint32_t IREE15:1;
814	uint32_t IREE14:1;
815	uint32_t IREE13:1;
816	uint32_t IREE12:1;
817	uint32_t IREE11:1;
818	uint32_t IREE10:1;
819	uint32_t IREE9:1;
820	uint32_t IREE8:1;
821	uint32_t IREE7:1;
822	uint32_t IREE6:1;
823	uint32_t IREE5:1;
824	uint32_t IREE4:1;
825	uint32_t IREE3:1;
826	uint32_t IREE2:1;
827	uint32_t IREE1:1;
828	uint32_t IREE0:1;
829	} B;
830	} IREER;
831
832	union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
833	uint32_t R;
834	struct {
835	uint32_t:16;
836	uint32_t IFEE15:1;
837	uint32_t IFEE14:1;
838	uint32_t IFEE13:1;
839	uint32_t IFEE12:1;
840	uint32_t IFEE11:1;
841	uint32_t IFEE10:1;
842	uint32_t IFEE9:1;
843	uint32_t IFEE8:1;
844	uint32_t IFEE7:1;
845	uint32_t IFEE6:1;
846	uint32_t IFEE5:1;
847	uint32_t IFEE4:1;
848	uint32_t IFEE3:1;
849	uint32_t IFEE2:1;
850	uint32_t IFEE1:1;
851	uint32_t IFEE0:1;
852	} B;
853	} IFEER;
854
855	union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
856	uint32_t R;
857	struct {
858	uint32_t:28;
859	uint32_t DFL:4;
860	} B;
861	} IDFR;
862
863	int32_t SIU_reserved1[3];
864
865	union SIU_PCR_tag { /* Pad Configuration Registers */
866	uint16_t R;
867	struct {
868	uint16_t:3;
869	uint16_t PA:3;
870	uint16_t OBE:1;
871	uint16_t IBE:1;
872	uint16_t DSC:2;
873	uint16_t ODE:1;
874	uint16_t HYS:1;
875	uint16_t SRC:2;
876	uint16_t WPE:1;
877	uint16_t WPS:1;
878	} B;
879	} PCR[512];
880
881	int16_t SIU_reserved_0[224];
882
883	union { /* GPIO Pin Data Output Registers */
884	uint8_t R;
885	struct {
886	uint8_t:7;
887	uint8_t PDO:1;
888	} B;
889	} GPDO[256];
890
891	int32_t SIU_reserved_3[64];
892
893	union { /* GPIO Pin Data Input Registers */
894	uint8_t R;
895	struct {
896	uint8_t:7;
897	uint8_t PDI:1;
898	} B;
899	} GPDI[256];
900
901	union { /* IMUX Register */
902	uint32_t R;
903	struct {
904	uint32_t TSEL5:2;
905	uint32_t TSEL4:2;
906	uint32_t TSEL3:2;
907	uint32_t TSEL2:2;
908	uint32_t TSEL1:2;
909	uint32_t TSEL0:2;
910	uint32_t:20;
911	} B;
912	} ETISR;
913
914	union { /* IMUX Register */
915	uint32_t R;
916	struct {
917	uint32_t ESEL15:2;
918	uint32_t ESEL14:2;
919	uint32_t ESEL13:2;
920	uint32_t ESEL12:2;
921	uint32_t ESEL11:2;
922	uint32_t ESEL10:2;
923	uint32_t ESEL9:2;
924	uint32_t ESEL8:2;
925	uint32_t ESEL7:2;
926	uint32_t ESEL6:2;
927	uint32_t ESEL5:2;
928	uint32_t ESEL4:2;
929	uint32_t ESEL3:2;
930	uint32_t ESEL2:2;
931	uint32_t ESEL1:2;
932	uint32_t ESEL0:2;
933	} B;
934	} EIISR;
935
936	union { /* IMUX Register */
937	uint32_t R;
938	struct {
939	uint32_t SINSELA:2;
940	uint32_t SSSELA:2;
941	uint32_t SCKSELA:2;
942	uint32_t TRIGSELA:2;
943	uint32_t SINSELB:2;
944	uint32_t SSSELB:2;
945	uint32_t SCKSELB:2;
946	uint32_t TRIGSELB:2;
947	uint32_t SINSELC:2;
948	uint32_t SSSELC:2;
949	uint32_t SCKSELC:2;
950	uint32_t TRIGSELC:2;
951	uint32_t SINSELD:2;
952	uint32_t SSSELD:2;
953	uint32_t SCKSELD:2;
954	uint32_t TRIGSELD:2;
955	} B;
956	} DISR;
957
958	int32_t SIU_reserved2[29];
959
960	union { /* Chip Configuration Register Register */
961	uint32_t R;
962	struct {
963	uint32_t:14;
964	uint32_t MATCH:1;
965	uint32_t DISNEX:1;
966	uint32_t:16;
967	} B;
968	} CCR;
969
970	union { /* External Clock Configuration Register Register */
971	uint32_t R;
972	struct {
973	uint32_t:18;
974	uint32_t ENGDIV:6;
975	uint32_t:4;
976	uint32_t EBTS:1;
977	uint32_t:1;
978	uint32_t EBDF:2;
979	} B;
980	} ECCR;
981
982	union {
983	uint32_t R;
984	} CARH;
985
986	union {
987	uint32_t R;
988	} CARL;
989
990	union {
991	uint32_t R;
992	} CBRH;
993
994	union {
995	uint32_t R;
996	} CBRL;
997
998	};
999	/****************************************************************************/
1000	/* MODULE : EMIOS */
1001	/****************************************************************************/
1002	struct EMIOS_tag {
1003	union EMIOS_MCR_tag {
1004	uint32_t R;
1005	struct {
1006	uint32_t:1;
1007	uint32_t MDIS:1;
1008	uint32_t FRZ:1;
1009	uint32_t GTBE:1;
1010	uint32_t ETB:1;
1011	uint32_t GPREN:1;
1012	uint32_t:6;
1013	uint32_t SRV:4;
1014	uint32_t GPRE:8;
1015	uint32_t:8;
1016	} B;
1017	} MCR; /* Module Configuration Register */
1018
1019	union EMIOS_GFR_tag {
1020	uint32_t R;
1021	struct {
1022	uint32_t:8;
1023	uint32_t F23:1;
1024	uint32_t F22:1;
1025	uint32_t F21:1;
1026	uint32_t F20:1;
1027	uint32_t F19:1;
1028	uint32_t F18:1;
1029	uint32_t F17:1;
1030	uint32_t F16:1;
1031	uint32_t F15:1;
1032	uint32_t F14:1;
1033	uint32_t F13:1;
1034	uint32_t F12:1;
1035	uint32_t F11:1;
1036	uint32_t F10:1;
1037	uint32_t F9:1;
1038	uint32_t F8:1;
1039	uint32_t F7:1;
1040	uint32_t F6:1;
1041	uint32_t F5:1;
1042	uint32_t F4:1;
1043	uint32_t F3:1;
1044	uint32_t F2:1;
1045	uint32_t F1:1;
1046	uint32_t F0:1;
1047	} B;
1048	} GFR; /* Global FLAG Register */
1049
1050	union EMIOS_OUDR_tag {
1051	uint32_t R;
1052	struct {
1053	uint32_t:8;
1054	uint32_t OU23:1;
1055	uint32_t OU22:1;
1056	uint32_t OU21:1;
1057	uint32_t OU20:1;
1058	uint32_t OU19:1;
1059	uint32_t OU18:1;
1060	uint32_t OU17:1;
1061	uint32_t OU16:1;
1062	uint32_t OU15:1;
1063	uint32_t OU14:1;
1064	uint32_t OU13:1;
1065	uint32_t OU12:1;
1066	uint32_t OU11:1;
1067	uint32_t OU10:1;
1068	uint32_t OU9:1;
1069	uint32_t OU8:1;
1070	uint32_t OU7:1;
1071	uint32_t OU6:1;
1072	uint32_t OU5:1;
1073	uint32_t OU4:1;
1074	uint32_t OU3:1;
1075	uint32_t OU2:1;
1076	uint32_t OU1:1;
1077	uint32_t OU0:1;
1078	} B;
1079	} OUDR; /* Output Update Disable Register */
1080
1081	uint32_t emios_reserved[5];
1082
1083	struct EMIOS_CH_tag {
1084	union {
1085	uint32_t R; /* Channel A Data Register */
1086	} CADR;
1087
1088	union {
1089	uint32_t R; /* Channel B Data Register */
1090	} CBDR;
1091
1092	union {
1093	uint32_t R; /* Channel Counter Register */
1094	} CCNTR;
1095
1096	union EMIOS_CCR_tag {
1097	uint32_t R;
1098	struct {
1099	uint32_t FREN:1;
1100	uint32_t ODIS:1;
1101	uint32_t ODISSL:2;
1102	uint32_t UCPRE:2;
1103	uint32_t UCPREN:1;
1104	uint32_t DMA:1;
1105	uint32_t:1;
1106	uint32_t IF:4;
1107	uint32_t FCK:1;
1108	uint32_t FEN:1;
1109	uint32_t:3;
1110	uint32_t FORCMA:1;
1111	uint32_t FORCMB:1;
1112	uint32_t:1;
1113	uint32_t BSL:2;
1114	uint32_t EDSEL:1;
1115	uint32_t EDPOL:1;
1116	uint32_t MODE:7;
1117	} B;
1118	} CCR; /* Channel Control Register */
1119
1120	union EMIOS_CSR_tag {
1121	uint32_t R;
1122	struct {
1123	uint32_t OVR:1;
1124	uint32_t:15;
1125	uint32_t OVFL:1;
1126	uint32_t:12;
1127	uint32_t UCIN:1;
1128	uint32_t UCOUT:1;
1129	uint32_t FLAG:1;
1130	} B;
1131	} CSR; /* Channel Status Register */
1132
1133	union {
1134	uint32_t R; /* Alternate Channel A Data Register */
1135	} ALTCADR;
1136
1137	uint32_t emios_channel_reserved[2];
1138
1139	} CH[24];
1140
1141	};
1142	/****************************************************************************/
1143	/* MODULE :ETPU */
1144	/****************************************************************************/
1145
1146	/*************************Configuration Registers************************/
1147
1148	struct ETPU_tag {
1149	union { /* MODULE CONFIGURATION REGISTER */
1150	uint32_t R;
1151	struct {
1152	uint32_t GEC:1; /* Global Exception Clear */
1153	uint32_t:3;
1154	uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
1155
1156	uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */
1157
1158	uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
1159
1160	uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */
1161
1162	uint32_t:3;
1163	uint32_t SCMSIZE:5; /* Shared Code Memory size */
1164	uint32_t:5;
1165	uint32_t SCMMISF:1; /* SCM MISC Flag */
1166	uint32_t SCMMISEN:1; /* SCM MISC Enable */
1167	uint32_t:2;
1168	uint32_t VIS:1; /* SCM Visability */
1169	uint32_t:5;
1170	uint32_t GTBE:1; /* Global Time Base Enable */
1171	} B;
1172	} MCR;
1173
1174	union { /* COHERENT DUAL-PARAMETER CONTROL */
1175	uint32_t R;
1176	struct {
1177	uint32_t STS:1; /* Start Status bit */
1178	uint32_t CTBASE:5; /* Channel Transfer Base */
1179	uint32_t PBASE:10; /* Parameter Buffer Base Address */
1180	uint32_t PWIDTH:1; /* Parameter Width */
1181	uint32_t PARAM0:7; /* Channel Parameter 0 */
1182	uint32_t WR:1;
1183	uint32_t PARAM1:7; /* Channel Parameter 1 */
1184	} B;
1185	} CDCR;
1186
1187	uint32_t etpu_reserved1;
1188
1189	union { /* MISC Compare Register */
1190	uint32_t R;
1191	} MISCCMPR;
1192
1193	union { /* SCM off-range Date Register */
1194	uint32_t R;
1195	} SCMOFFDATAR;
1196
1197	union { /* ETPU_A Configuration Register */
1198	uint32_t R;
1199	struct {
1200	uint32_t FEND:1; /* Force END */
1201	uint32_t MDIS:1; /* Low power Stop */
1202	uint32_t:1;
1203	uint32_t STF:1; /* Stop Flag */
1204	uint32_t:4;
1205	uint32_t HLTF:1; /* Halt Mode Flag */
1206	uint32_t:4;
1207	uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1208	uint32_t CDFC:2;
1209	uint32_t:9;
1210	uint32_t ETB:5; /* Entry Table Base */
1211	} B;
1212	} ECR_A;
1213
1214	union { /* ETPU_B Configuration Register */
1215	uint32_t R;
1216	struct {
1217	uint32_t FEND:1; /* Force END */
1218	uint32_t MDIS:1; /* Low power Stop */
1219	uint32_t:1;
1220	uint32_t STF:1; /* Stop Flag */
1221	uint32_t:4;
1222	uint32_t HLTF:1; /* Halt Mode Flag */
1223	uint32_t:4;
1224	uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1225	uint32_t CDFC:2;
1226	uint32_t:9;
1227	uint32_t ETB:5; /* Entry Table Base */
1228	} B;
1229	} ECR_B;
1230
1231	uint32_t etpu_reserved4;
1232
1233	union { /* ETPU_A Timebase Configuration Register */
1234	uint32_t R;
1235	struct {
1236	uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1237	uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1238	uint32_t:1;
1239	uint32_t AM:1; /* Angle Mode */
1240	uint32_t:3;
1241	uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1242	uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1243	uint32_t:6;
1244	uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1245	} B;
1246	} TBCR_A;
1247
1248	union { /* ETPU_A TCR1 Visibility Register */
1249	uint32_t R;
1250	} TB1R_A;
1251
1252	union { /* ETPU_A TCR2 Visibility Register */
1253	uint32_t R;
1254	} TB2R_A;
1255
1256	union { /* ETPU_A STAC Configuration Register */
1257	uint32_t R;
1258	struct {
1259	uint32_t REN1:1; /* Resource Enable TCR1 */
1260	uint32_t RSC1:1; /* Resource Control TCR1 */
1261	uint32_t:2;
1262	uint32_t SERVER_ID1:4;
1263	uint32_t:4;
1264	uint32_t SRV1:4; /* Resource Server Slot */
1265	uint32_t REN2:1; /* Resource Enable TCR2 */
1266	uint32_t RSC2:1; /* Resource Control TCR2 */
1267	uint32_t:2;
1268	uint32_t SERVER_ID2:4;
1269	uint32_t:4;
1270	uint32_t SRV2:4; /* Resource Server Slot */
1271	} B;
1272	} REDCR_A;
1273
1274	uint32_t etpu_reserved5[4];
1275
1276	union { /* ETPU_B Timebase Configuration Register */
1277	uint32_t R;
1278	struct {
1279	uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1280	uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1281	uint32_t:1;
1282	uint32_t AM:1; /* Angle Mode */
1283	uint32_t:3;
1284	uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1285	uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1286	uint32_t:6;
1287	uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1288	} B;
1289	} TBCR_B;
1290
1291	union { /* ETPU_B TCR1 Visibility Register */
1292	uint32_t R;
1293	} TB1R_B;
1294
1295	union { /* ETPU_B TCR2 Visibility Register */
1296	uint32_t R;
1297	} TB2R_B;
1298
1299	union { /* ETPU_B STAC Configuration Register */
1300	uint32_t R;
1301	struct {
1302	uint32_t REN1:1; /* Resource Enable TCR1 */
1303	uint32_t RSC1:1; /* Resource Control TCR1 */
1304	uint32_t:2;
1305	uint32_t SERVER_ID1:4;
1306	uint32_t:4;
1307	uint32_t SRV1:4; /* Resource Server Slot */
1308	uint32_t REN2:1; /* Resource Enable TCR2 */
1309	uint32_t RSC2:1; /* Resource Control TCR2 */
1310	uint32_t:2;
1311	uint32_t SERVER_ID2:4;
1312	uint32_t:4;
1313	uint32_t SRV2:4; /* Resource Server Slot */
1314	} B;
1315	} REDCR_B;
1316
1317	uint32_t etpu_reserved7[108];
1318
1319	/***************************Status and Control Registers************************/
1320
1321	union { /* ETPU_A Channel Interrut Status */
1322	uint32_t R;
1323	struct {
1324	uint32_t CIS31:1; /* Channel 31 Interrut Status */
1325	uint32_t CIS30:1; /* Channel 30 Interrut Status */
1326	uint32_t CIS29:1; /* Channel 29 Interrut Status */
1327	uint32_t CIS28:1; /* Channel 28 Interrut Status */
1328	uint32_t CIS27:1; /* Channel 27 Interrut Status */
1329	uint32_t CIS26:1; /* Channel 26 Interrut Status */
1330	uint32_t CIS25:1; /* Channel 25 Interrut Status */
1331	uint32_t CIS24:1; /* Channel 24 Interrut Status */
1332	uint32_t CIS23:1; /* Channel 23 Interrut Status */
1333	uint32_t CIS22:1; /* Channel 22 Interrut Status */
1334	uint32_t CIS21:1; /* Channel 21 Interrut Status */
1335	uint32_t CIS20:1; /* Channel 20 Interrut Status */
1336	uint32_t CIS19:1; /* Channel 19 Interrut Status */
1337	uint32_t CIS18:1; /* Channel 18 Interrut Status */
1338	uint32_t CIS17:1; /* Channel 17 Interrut Status */
1339	uint32_t CIS16:1; /* Channel 16 Interrut Status */
1340	uint32_t CIS15:1; /* Channel 15 Interrut Status */
1341	uint32_t CIS14:1; /* Channel 14 Interrut Status */
1342	uint32_t CIS13:1; /* Channel 13 Interrut Status */
1343	uint32_t CIS12:1; /* Channel 12 Interrut Status */
1344	uint32_t CIS11:1; /* Channel 11 Interrut Status */
1345	uint32_t CIS10:1; /* Channel 10 Interrut Status */
1346	uint32_t CIS9:1; /* Channel 9 Interrut Status */
1347	uint32_t CIS8:1; /* Channel 8 Interrut Status */
1348	uint32_t CIS7:1; /* Channel 7 Interrut Status */
1349	uint32_t CIS6:1; /* Channel 6 Interrut Status */
1350	uint32_t CIS5:1; /* Channel 5 Interrut Status */
1351	uint32_t CIS4:1; /* Channel 4 Interrut Status */
1352	uint32_t CIS3:1; /* Channel 3 Interrut Status */
1353	uint32_t CIS2:1; /* Channel 2 Interrut Status */
1354	uint32_t CIS1:1; /* Channel 1 Interrut Status */
1355	uint32_t CIS0:1; /* Channel 0 Interrut Status */
1356	} B;
1357	} CISR_A;
1358
1359	union { /* ETPU_B Channel Interruput Status */
1360	uint32_t R;
1361	struct {
1362	uint32_t CIS31:1; /* Channel 31 Interrut Status */
1363	uint32_t CIS30:1; /* Channel 30 Interrut Status */
1364	uint32_t CIS29:1; /* Channel 29 Interrut Status */
1365	uint32_t CIS28:1; /* Channel 28 Interrut Status */
1366	uint32_t CIS27:1; /* Channel 27 Interrut Status */
1367	uint32_t CIS26:1; /* Channel 26 Interrut Status */
1368	uint32_t CIS25:1; /* Channel 25 Interrut Status */
1369	uint32_t CIS24:1; /* Channel 24 Interrut Status */
1370	uint32_t CIS23:1; /* Channel 23 Interrut Status */
1371	uint32_t CIS22:1; /* Channel 22 Interrut Status */
1372	uint32_t CIS21:1; /* Channel 21 Interrut Status */
1373	uint32_t CIS20:1; /* Channel 20 Interrut Status */
1374	uint32_t CIS19:1; /* Channel 19 Interrut Status */
1375	uint32_t CIS18:1; /* Channel 18 Interrut Status */
1376	uint32_t CIS17:1; /* Channel 17 Interrut Status */
1377	uint32_t CIS16:1; /* Channel 16 Interrut Status */
1378	uint32_t CIS15:1; /* Channel 15 Interrut Status */
1379	uint32_t CIS14:1; /* Channel 14 Interrut Status */
1380	uint32_t CIS13:1; /* Channel 13 Interrut Status */
1381	uint32_t CIS12:1; /* Channel 12 Interrut Status */
1382	uint32_t CIS11:1; /* Channel 11 Interrut Status */
1383	uint32_t CIS10:1; /* Channel 10 Interrut Status */
1384	uint32_t CIS9:1; /* Channel 9 Interrut Status */
1385	uint32_t CIS8:1; /* Channel 8 Interrut Status */
1386	uint32_t CIS7:1; /* Channel 7 Interrut Status */
1387	uint32_t CIS6:1; /* Channel 6 Interrut Status */
1388	uint32_t CIS5:1; /* Channel 5 Interrut Status */
1389	uint32_t CIS4:1; /* Channel 4 Interrut Status */
1390	uint32_t CIS3:1; /* Channel 3 Interrut Status */
1391	uint32_t CIS2:1; /* Channel 2 Interrut Status */
1392	uint32_t CIS1:1; /* Channel 1 Interrupt Status */
1393	uint32_t CIS0:1; /* Channel 0 Interrupt Status */
1394	} B;
1395	} CISR_B;
1396
1397	uint32_t etpu_reserved9[2];
1398
1399	union { /* ETPU_A Data Transfer Request Status */
1400	uint32_t R;
1401	struct {
1402	uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1403	uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1404	uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1405	uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1406	uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1407	uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1408	uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1409	uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1410	uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1411	uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1412	uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1413	uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1414	uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1415	uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1416	uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1417	uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1418	uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1419	uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1420	uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1421	uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1422	uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1423	uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1424	uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1425	uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1426	uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1427	uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1428	uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1429	uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1430	uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1431	uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1432	uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1433	uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1434	} B;
1435	} CDTRSR_A;
1436
1437	union { /* ETPU_B Data Transfer Request Status */
1438	uint32_t R;
1439	struct {
1440	uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1441	uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1442	uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1443	uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1444	uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1445	uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1446	uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1447	uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1448	uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1449	uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1450	uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1451	uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1452	uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1453	uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1454	uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1455	uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1456	uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1457	uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1458	uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1459	uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1460	uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1461	uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1462	uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1463	uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1464	uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1465	uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1466	uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1467	uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1468	uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1469	uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1470	uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1471	uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1472	} B;
1473	} CDTRSR_B;
1474
1475	uint32_t etpu_reserved11[2];
1476
1477	union { /* ETPU_A Interruput Overflow Status */
1478	uint32_t R;
1479	struct {
1480	uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1481	uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1482	uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1483	uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1484	uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1485	uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1486	uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1487	uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1488	uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1489	uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1490	uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1491	uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1492	uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1493	uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1494	uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1495	uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1496	uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1497	uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1498	uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1499	uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1500	uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1501	uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1502	uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1503	uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1504	uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1505	uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1506	uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1507	uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1508	uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1509	uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1510	uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1511	uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1512	} B;
1513	} CIOSR_A;
1514
1515	union { /* ETPU_B Interruput Overflow Status */
1516	uint32_t R;
1517	struct {
1518	uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1519	uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1520	uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1521	uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1522	uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1523	uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1524	uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1525	uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1526	uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1527	uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1528	uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1529	uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1530	uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1531	uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1532	uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1533	uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1534	uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1535	uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1536	uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1537	uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1538	uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1539	uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1540	uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1541	uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1542	uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1543	uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1544	uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1545	uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1546	uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1547	uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1548	uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1549	uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1550	} B;
1551	} CIOSR_B;
1552
1553	uint32_t etpu_reserved13[2];
1554
1555	union { /* ETPU_A Data Transfer Overflow Status */
1556	uint32_t R;
1557	struct {
1558	uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1559	uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1560	uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1561	uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1562	uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1563	uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1564	uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1565	uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1566	uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1567	uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1568	uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1569	uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1570	uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1571	uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1572	uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1573	uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1574	uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1575	uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1576	uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1577	uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1578	uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1579	uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1580	uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1581	uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1582	uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1583	uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1584	uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1585	uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1586	uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1587	uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1588	uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1589	uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1590	} B;
1591	} CDTROSR_A;
1592
1593	union { /* ETPU_B Data Transfer Overflow Status */
1594	uint32_t R;
1595	struct {
1596	uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1597	uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1598	uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1599	uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1600	uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1601	uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1602	uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1603	uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1604	uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1605	uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1606	uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1607	uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1608	uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1609	uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1610	uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1611	uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1612	uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1613	uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1614	uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1615	uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1616	uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1617	uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1618	uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1619	uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1620	uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1621	uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1622	uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1623	uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1624	uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1625	uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1626	uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1627	uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1628	} B;
1629	} CDTROSR_B;
1630
1631	uint32_t etpu_reserved15[2];
1632
1633	union { /* ETPU_A Channel Interruput Enable */
1634	uint32_t R;
1635	struct {
1636	uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1637	uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1638	uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1639	uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1640	uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1641	uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1642	uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1643	uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1644	uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1645	uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1646	uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1647	uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1648	uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1649	uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1650	uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1651	uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1652	uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1653	uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1654	uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1655	uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1656	uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1657	uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1658	uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1659	uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1660	uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1661	uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1662	uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1663	uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1664	uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1665	uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1666	uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1667	uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1668	} B;
1669	} CIER_A;
1670
1671	union { /* ETPU_B Channel Interruput Enable */
1672	uint32_t R;
1673	struct {
1674	uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1675	uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1676	uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1677	uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1678	uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1679	uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1680	uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1681	uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1682	uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1683	uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1684	uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1685	uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1686	uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1687	uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1688	uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1689	uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1690	uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1691	uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1692	uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1693	uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1694	uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1695	uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1696	uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1697	uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1698	uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1699	uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1700	uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1701	uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1702	uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1703	uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1704	uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1705	uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1706	} B;
1707	} CIER_B;
1708
1709	uint32_t etpu_reserved17[2];
1710
1711	union { /* ETPU_A Channel Data Transfer Request Enable */
1712	uint32_t R;
1713	struct {
1714	uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1715	uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1716	uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1717	uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1718	uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1719	uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1720	uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1721	uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1722	uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1723	uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1724	uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1725	uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1726	uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1727	uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1728	uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1729	uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1730	uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1731	uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1732	uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1733	uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1734	uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1735	uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1736	uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1737	uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1738	uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1739	uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1740	uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1741	uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1742	uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1743	uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1744	uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1745	uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1746	} B;
1747	} CDTRER_A;
1748
1749	union { /* ETPU_B Channel Data Transfer Request Enable */
1750	uint32_t R;
1751	struct {
1752	uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1753	uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1754	uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1755	uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1756	uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1757	uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1758	uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1759	uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1760	uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1761	uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1762	uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1763	uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1764	uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1765	uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1766	uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1767	uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1768	uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1769	uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1770	uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1771	uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1772	uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1773	uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1774	uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1775	uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1776	uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1777	uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1778	uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1779	uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1780	uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1781	uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1782	uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1783	uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1784	} B;
1785	} CDTRER_B;
1786
1787	uint32_t etpu_reserved20[10];
1788	union { /* ETPU_A Channel Pending Service Status */
1789	uint32_t R;
1790	struct {
1791	uint32_t SR31:1; /* Channel 31 Pending Service Status */
1792	uint32_t SR30:1; /* Channel 30 Pending Service Status */
1793	uint32_t SR29:1; /* Channel 29 Pending Service Status */
1794	uint32_t SR28:1; /* Channel 28 Pending Service Status */
1795	uint32_t SR27:1; /* Channel 27 Pending Service Status */
1796	uint32_t SR26:1; /* Channel 26 Pending Service Status */
1797	uint32_t SR25:1; /* Channel 25 Pending Service Status */
1798	uint32_t SR24:1; /* Channel 24 Pending Service Status */
1799	uint32_t SR23:1; /* Channel 23 Pending Service Status */
1800	uint32_t SR22:1; /* Channel 22 Pending Service Status */
1801	uint32_t SR21:1; /* Channel 21 Pending Service Status */
1802	uint32_t SR20:1; /* Channel 20 Pending Service Status */
1803	uint32_t SR19:1; /* Channel 19 Pending Service Status */
1804	uint32_t SR18:1; /* Channel 18 Pending Service Status */
1805	uint32_t SR17:1; /* Channel 17 Pending Service Status */
1806	uint32_t SR16:1; /* Channel 16 Pending Service Status */
1807	uint32_t SR15:1; /* Channel 15 Pending Service Status */
1808	uint32_t SR14:1; /* Channel 14 Pending Service Status */
1809	uint32_t SR13:1; /* Channel 13 Pending Service Status */
1810	uint32_t SR12:1; /* Channel 12 Pending Service Status */
1811	uint32_t SR11:1; /* Channel 11 Pending Service Status */
1812	uint32_t SR10:1; /* Channel 10 Pending Service Status */
1813	uint32_t SR9:1; /* Channel 9 Pending Service Status */
1814	uint32_t SR8:1; /* Channel 8 Pending Service Status */
1815	uint32_t SR7:1; /* Channel 7 Pending Service Status */
1816	uint32_t SR6:1; /* Channel 6 Pending Service Status */
1817	uint32_t SR5:1; /* Channel 5 Pending Service Status */
1818	uint32_t SR4:1; /* Channel 4 Pending Service Status */
1819	uint32_t SR3:1; /* Channel 3 Pending Service Status */
1820	uint32_t SR2:1; /* Channel 2 Pending Service Status */
1821	uint32_t SR1:1; /* Channel 1 Pending Service Status */
1822	uint32_t SR0:1; /* Channel 0 Pending Service Status */
1823	} B;
1824	} CPSSR_A;
1825
1826	union { /* ETPU_B Channel Pending Service Status */
1827	uint32_t R;
1828	struct {
1829	uint32_t SR31:1; /* Channel 31 Pending Service Status */
1830	uint32_t SR30:1; /* Channel 30 Pending Service Status */
1831	uint32_t SR29:1; /* Channel 29 Pending Service Status */
1832	uint32_t SR28:1; /* Channel 28 Pending Service Status */
1833	uint32_t SR27:1; /* Channel 27 Pending Service Status */
1834	uint32_t SR26:1; /* Channel 26 Pending Service Status */
1835	uint32_t SR25:1; /* Channel 25 Pending Service Status */
1836	uint32_t SR24:1; /* Channel 24 Pending Service Status */
1837	uint32_t SR23:1; /* Channel 23 Pending Service Status */
1838	uint32_t SR22:1; /* Channel 22 Pending Service Status */
1839	uint32_t SR21:1; /* Channel 21 Pending Service Status */
1840	uint32_t SR20:1; /* Channel 20 Pending Service Status */
1841	uint32_t SR19:1; /* Channel 19 Pending Service Status */
1842	uint32_t SR18:1; /* Channel 18 Pending Service Status */
1843	uint32_t SR17:1; /* Channel 17 Pending Service Status */
1844	uint32_t SR16:1; /* Channel 16 Pending Service Status */
1845	uint32_t SR15:1; /* Channel 15 Pending Service Status */
1846	uint32_t SR14:1; /* Channel 14 Pending Service Status */
1847	uint32_t SR13:1; /* Channel 13 Pending Service Status */
1848	uint32_t SR12:1; /* Channel 12 Pending Service Status */
1849	uint32_t SR11:1; /* Channel 11 Pending Service Status */
1850	uint32_t SR10:1; /* Channel 10 Pending Service Status */
1851	uint32_t SR9:1; /* Channel 9 Pending Service Status */
1852	uint32_t SR8:1; /* Channel 8 Pending Service Status */
1853	uint32_t SR7:1; /* Channel 7 Pending Service Status */
1854	uint32_t SR6:1; /* Channel 6 Pending Service Status */
1855	uint32_t SR5:1; /* Channel 5 Pending Service Status */
1856	uint32_t SR4:1; /* Channel 4 Pending Service Status */
1857	uint32_t SR3:1; /* Channel 3 Pending Service Status */
1858	uint32_t SR2:1; /* Channel 2 Pending Service Status */
1859	uint32_t SR1:1; /* Channel 1 Pending Service Status */
1860	uint32_t SR0:1; /* Channel 0 Pending Service Status */
1861	} B;
1862	} CPSSR_B;
1863
1864	uint32_t etpu_reserved20a[2];
1865
1866	union { /* ETPU_A Channel Service Status */
1867	uint32_t R;
1868	struct {
1869	uint32_t SS31:1; /* Channel 31 Service Status */
1870	uint32_t SS30:1; /* Channel 30 Service Status */
1871	uint32_t SS29:1; /* Channel 29 Service Status */
1872	uint32_t SS28:1; /* Channel 28 Service Status */
1873	uint32_t SS27:1; /* Channel 27 Service Status */
1874	uint32_t SS26:1; /* Channel 26 Service Status */
1875	uint32_t SS25:1; /* Channel 25 Service Status */
1876	uint32_t SS24:1; /* Channel 24 Service Status */
1877	uint32_t SS23:1; /* Channel 23 Service Status */
1878	uint32_t SS22:1; /* Channel 22 Service Status */
1879	uint32_t SS21:1; /* Channel 21 Service Status */
1880	uint32_t SS20:1; /* Channel 20 Service Status */
1881	uint32_t SS19:1; /* Channel 19 Service Status */
1882	uint32_t SS18:1; /* Channel 18 Service Status */
1883	uint32_t SS17:1; /* Channel 17 Service Status */
1884	uint32_t SS16:1; /* Channel 16 Service Status */
1885	uint32_t SS15:1; /* Channel 15 Service Status */
1886	uint32_t SS14:1; /* Channel 14 Service Status */
1887	uint32_t SS13:1; /* Channel 13 Service Status */
1888	uint32_t SS12:1; /* Channel 12 Service Status */
1889	uint32_t SS11:1; /* Channel 11 Service Status */
1890	uint32_t SS10:1; /* Channel 10 Service Status */
1891	uint32_t SS9:1; /* Channel 9 Service Status */
1892	uint32_t SS8:1; /* Channel 8 Service Status */
1893	uint32_t SS7:1; /* Channel 7 Service Status */
1894	uint32_t SS6:1; /* Channel 6 Service Status */
1895	uint32_t SS5:1; /* Channel 5 Service Status */
1896	uint32_t SS4:1; /* Channel 4 Service Status */
1897	uint32_t SS3:1; /* Channel 3 Service Status */
1898	uint32_t SS2:1; /* Channel 2 Service Status */
1899	uint32_t SS1:1; /* Channel 1 Service Status */
1900	uint32_t SS0:1; /* Channel 0 Service Status */
1901	} B;
1902	} CSSR_A;
1903
1904	union { /* ETPU_B Channel Service Status */
1905	uint32_t R;
1906	struct {
1907	uint32_t SS31:1; /* Channel 31 Service Status */
1908	uint32_t SS30:1; /* Channel 30 Service Status */
1909	uint32_t SS29:1; /* Channel 29 Service Status */
1910	uint32_t SS28:1; /* Channel 28 Service Status */
1911	uint32_t SS27:1; /* Channel 27 Service Status */
1912	uint32_t SS26:1; /* Channel 26 Service Status */
1913	uint32_t SS25:1; /* Channel 25 Service Status */
1914	uint32_t SS24:1; /* Channel 24 Service Status */
1915	uint32_t SS23:1; /* Channel 23 Service Status */
1916	uint32_t SS22:1; /* Channel 22 Service Status */
1917	uint32_t SS21:1; /* Channel 21 Service Status */
1918	uint32_t SS20:1; /* Channel 20 Service Status */
1919	uint32_t SS19:1; /* Channel 19 Service Status */
1920	uint32_t SS18:1; /* Channel 18 Service Status */
1921	uint32_t SS17:1; /* Channel 17 Service Status */
1922	uint32_t SS16:1; /* Channel 16 Service Status */
1923	uint32_t SS15:1; /* Channel 15 Service Status */
1924	uint32_t SS14:1; /* Channel 14 Service Status */
1925	uint32_t SS13:1; /* Channel 13 Service Status */
1926	uint32_t SS12:1; /* Channel 12 Service Status */
1927	uint32_t SS11:1; /* Channel 11 Service Status */
1928	uint32_t SS10:1; /* Channel 10 Service Status */
1929	uint32_t SS9:1; /* Channel 9 Service Status */
1930	uint32_t SS8:1; /* Channel 8 Service Status */
1931	uint32_t SS7:1; /* Channel 7 Service Status */
1932	uint32_t SS6:1; /* Channel 6 Service Status */
1933	uint32_t SS5:1; /* Channel 5 Service Status */
1934	uint32_t SS4:1; /* Channel 4 Service Status */
1935	uint32_t SS3:1; /* Channel 3 Service Status */
1936	uint32_t SS2:1; /* Channel 2 Service Status */
1937	uint32_t SS1:1; /* Channel 1 Service Status */
1938	uint32_t SS0:1; /* Channel 0 Service Status */
1939	} B;
1940	} CSSR_B;
1941
1942	uint32_t etpu_reserved23[90];
1943
1944	/***************************Channels******************************/
1945
1946	struct {
1947	union {
1948	uint32_t R; /* Channel Configuration Register */
1949	struct {
1950	uint32_t CIE:1; /* Channel Interruput Enable */
1951	uint32_t DTRE:1; /* Data Transfer Request Enable */
1952	uint32_t CPR:2; /* Channel Priority */
1953	uint32_t:3;
1954	uint32_t ETCS:1; /* Entry Table Condition Select */
1955	uint32_t:3;
1956	uint32_t CFS:5; /* Channel Function Select */
1957	uint32_t ODIS:1; /* Output disable */
1958	uint32_t OPOL:1; /* output polarity */
1959	uint32_t:3;
1960	uint32_t CPBA:11; /* Channel Parameter Base Address */
1961	} B;
1962	} CR;
1963	union {
1964	uint32_t R; /* Channel Status Control Register */
1965	struct {
1966	uint32_t CIS:1; /* Channel Interruput Status */
1967	uint32_t CIOS:1; /* Channel Interruput Overflow Status */
1968	uint32_t:6;
1969	uint32_t DTRS:1; /* Data Transfer Status */
1970	uint32_t DTROS:1; /* Data Transfer Overflow Status */
1971	uint32_t:6;
1972	uint32_t IPS:1; /* Input Pin State */
1973	uint32_t OPS:1; /* Output Pin State */
1974	uint32_t OBE:1; /* Output Buffer Enable */
1975	uint32_t:11;
1976	uint32_t FM1:1; /* Function mode */
1977	uint32_t FM0:1; /* Function mode */
1978	} B;
1979	} SCR;
1980	union {
1981	uint32_t R; /* Channel Host Service Request Register */
1982	struct {
1983	uint32_t:29; /* Host Service Request */
1984	uint32_t HSR:3;
1985	} B;
1986	} HSRR;
1987	uint32_t etpu_reserved23;
1988	} CHAN[127];
1989
1990	};
1991	/****************************************************************************/
1992	/* MODULE : XBAR CrossBar */
1993	/****************************************************************************/
1994	struct XBAR_tag {
1995	union {
1996	uint32_t R;
1997	struct {
1998	uint32_t:4;
1999
2000	uint32_t:4;
2001
2002	uint32_t:4;
2003
2004	uint32_t:4;
2005
2006	uint32_t:1;
2007	uint32_t MSTR3:3; /* FEC */
2008
2009	uint32_t:1;
2010	uint32_t MSTR2:3;
2011	uint32_t:1;
2012	uint32_t MSTR1:3;
2013	uint32_t:1;
2014	uint32_t MSTR0:3;
2015	} B;
2016	} MPR0; /* Master Priority Register for Slave Port 0 */
2017
2018	uint32_t xbar_reserved1[3];
2019
2020	union {
2021	uint32_t R;
2022	struct {
2023	uint32_t RO:1;
2024	uint32_t:21;
2025	uint32_t ARB:2;
2026	uint32_t:2;
2027	uint32_t PCTL:2;
2028	uint32_t:1;
2029	uint32_t PARK:3;
2030	} B;
2031	} SGPCR0; /* General Purpose Control Register for Slave Port 0 */
2032
2033	uint32_t xbar_reserved2[59];
2034
2035	union {
2036	uint32_t R;
2037	struct {
2038	uint32_t:4;
2039
2040	uint32_t:4;
2041
2042	uint32_t:4;
2043
2044	uint32_t:4;
2045
2046	uint32_t:1;
2047	uint32_t MSTR3:3; /* FEC */
2048
2049	uint32_t:1;
2050	uint32_t MSTR2:3;
2051	uint32_t:1;
2052	uint32_t MSTR1:3;
2053	uint32_t:1;
2054	uint32_t MSTR0:3;
2055	} B;
2056	} MPR1; /* Master Priority Register for Slave Port 1 */
2057
2058	uint32_t xbar_reserved3[3];
2059
2060	union {
2061	uint32_t R;
2062	struct {
2063	uint32_t RO:1;
2064	uint32_t:21;
2065	uint32_t ARB:2;
2066	uint32_t:2;
2067	uint32_t PCTL:2;
2068	uint32_t:1;
2069	uint32_t PARK:3;
2070	} B;
2071	} SGPCR1; /* General Purpose Control Register for Slave Port 1 */
2072
2073	uint32_t xbar_reserved4[123];
2074
2075	union {
2076	uint32_t R;
2077	struct {
2078	uint32_t:4;
2079
2080	uint32_t:4;
2081
2082	uint32_t:4;
2083
2084	uint32_t:4;
2085
2086	uint32_t:1;
2087	uint32_t MSTR3:3; /* FEC */
2088
2089	uint32_t:1;
2090	uint32_t MSTR2:3;
2091	uint32_t:1;
2092	uint32_t MSTR1:3;
2093	uint32_t:1;
2094	uint32_t MSTR0:3;
2095	} B;
2096	} MPR3; /* Master Priority Register for Slave Port 3 */
2097
2098	uint32_t xbar_reserved5[3];
2099
2100	union {
2101	uint32_t R;
2102	struct {
2103	uint32_t RO:1;
2104	uint32_t:21;
2105	uint32_t ARB:2;
2106	uint32_t:2;
2107	uint32_t PCTL:2;
2108	uint32_t:1;
2109	uint32_t PARK:3;
2110	} B;
2111	} SGPCR3; /* General Purpose Control Register for Slave Port 3 */
2112
2113	uint32_t xbar_reserved6[187];
2114
2115	union {
2116	uint32_t R;
2117	struct {
2118	uint32_t:4;
2119
2120	uint32_t:4;
2121
2122	uint32_t:4;
2123
2124	uint32_t:4;
2125
2126	uint32_t:1;
2127	uint32_t MSTR3:3; /* FEC */
2128
2129	uint32_t:1;
2130	uint32_t MSTR2:3;
2131	uint32_t:1;
2132	uint32_t MSTR1:3;
2133	uint32_t:1;
2134	uint32_t MSTR0:3;
2135	} B;
2136	} MPR6; /* Master Priority Register for Slave Port 6 */
2137
2138	uint32_t xbar_reserved7[3];
2139
2140	union {
2141	uint32_t R;
2142	struct {
2143	uint32_t RO:1;
2144	uint32_t:21;
2145	uint32_t ARB:2;
2146	uint32_t:2;
2147	uint32_t PCTL:2;
2148	uint32_t:1;
2149	uint32_t PARK:3;
2150	} B;
2151	} SGPCR6; /* General Purpose Control Register for Slave Port 6 */
2152
2153	uint32_t xbar_reserved8[59];
2154
2155	union {
2156	uint32_t R;
2157	struct {
2158	uint32_t:4;
2159
2160	uint32_t:4;
2161
2162	uint32_t:4;
2163
2164	uint32_t:4;
2165
2166	uint32_t:1;
2167	uint32_t MSTR3:3; /* FEC */
2168
2169	uint32_t:1;
2170	uint32_t MSTR2:3;
2171	uint32_t:1;
2172	uint32_t MSTR1:3;
2173	uint32_t:1;
2174	uint32_t MSTR0:3;
2175	} B;
2176	} MPR7; /* Master Priority Register for Slave Port 7 */
2177
2178	uint32_t xbar_reserved9[3];
2179
2180	union {
2181	uint32_t R;
2182	struct {
2183	uint32_t RO:1;
2184	uint32_t:21;
2185	uint32_t ARB:2;
2186	uint32_t:2;
2187	uint32_t PCTL:2;
2188	uint32_t:1;
2189	uint32_t PARK:3;
2190	} B;
2191	} SGPCR7; /* General Purpose Control Register for Slave Port 7 */
2192
2193	};
2194	/****************************************************************************/
2195	/* MODULE : ECSM */
2196	/****************************************************************************/
2197	struct ECSM_tag {
2198
2199	uint32_t ecsm_reserved1[5];
2200
2201	uint16_t ecsm_reserved2;
2202
2203	union {
2204	uint16_t R;
2205	} SWTCR; /* Software Watchdog Timer Control */
2206
2207	uint8_t ecsm_reserved3[3];
2208
2209	union {
2210	uint8_t R;
2211	} SWTSR; /* SWT Service Register */
2212
2213	uint8_t ecsm_reserved4[3];
2214
2215	union {
2216	uint8_t R;
2217	} SWTIR; /* SWT Interrupt Register */
2218
2219	uint32_t ecsm_reserved5a[1];
2220
2221	union {
2222	uint32_t R;
2223	struct {
2224	uint32_t FSBCR0:1;
2225	uint32_t FSBCR1:1;
2226	uint32_t FSBCR2:1;
2227	uint32_t FSBCR3:1;
2228	uint32_t FSBCR4:1;
2229	uint32_t FSBCR5:1;
2230	uint32_t FSBCR6:1;
2231	uint32_t FSBCR7:1;
2232	uint32_t RBEN:1;
2233	uint32_t WBEN:1;
2234	uint32_t ACCERR:1;
2235	uint32_t:21;
2236	} B;
2237	} FSBMCR; /* FEC System Bus Master Control Register */
2238
2239	uint32_t ecsm_reserved5c[6];
2240
2241	uint8_t ecsm_reserved6[3];
2242
2243	union {
2244	uint8_t R;
2245	struct {
2246	uint8_t:6;
2247	uint8_t ERNCR:1;
2248	uint8_t EFNCR:1;
2249	} B;
2250	} ECR; /* ECC Configuration Register */
2251
2252	uint8_t mcm_reserved8[3];
2253
2254	union {
2255	uint8_t R;
2256	struct {
2257	uint8_t:6;
2258	uint8_t RNCE:1;
2259	uint8_t FNCE:1;
2260	} B;
2261	} ESR; /* ECC Status Register */
2262
2263	uint16_t ecsm_reserved9;
2264
2265	union {
2266	uint16_t R;
2267	struct {
2268	uint16_t:6;
2269	uint16_t FRCNCI:1;
2270	uint16_t FR1NCI:1;
2271	uint16_t:1;
2272	uint16_t ERRBIT:7;
2273	} B;
2274	} EEGR; /* ECC Error Generation Register */
2275
2276	uint32_t ecsm_reserved10;
2277
2278	union {
2279	uint32_t R;
2280	struct {
2281	uint32_t FEAR:32;
2282	} B;
2283	} FEAR; /* Flash ECC Address Register */
2284
2285	uint16_t ecsm_reserved11;
2286
2287	union {
2288	uint8_t R;
2289	struct {
2290	uint8_t:4;
2291	uint8_t FEMR:4;
2292	} B;
2293	} FEMR; /* Flash ECC Master Register */
2294
2295	union {
2296	uint8_t R;
2297	struct {
2298	uint8_t WRITE:1;
2299	uint8_t SIZE:3;
2300	uint8_t PROT0:1;
2301	uint8_t PROT1:1;
2302	uint8_t PROT2:1;
2303	uint8_t PROT3:1;
2304	} B;
2305	} FEAT; /* Flash ECC Attributes Register */
2306
2307	union {
2308	uint32_t R;
2309	struct {
2310	uint32_t FEDH:32;
2311	} B;
2312	} FEDRH; /* Flash ECC Data High Register */
2313
2314	union {
2315	uint32_t R;
2316	struct {
2317	uint32_t FEDL:32;
2318	} B;
2319	} FEDRL; /* Flash ECC Data Low Register */
2320
2321	union {
2322	uint32_t R;
2323	struct {
2324	uint32_t REAR:32;
2325	} B;
2326	} REAR; /* RAM ECC Address */
2327
2328	uint8_t ecsm_reserved12[2];
2329
2330	union {
2331	uint8_t R;
2332	struct {
2333	uint8_t:4;
2334	uint8_t REMR:4;
2335	} B;
2336	} REMR; /* RAM ECC Master */
2337
2338	union {
2339	uint8_t R;
2340	struct {
2341	uint8_t WRITE:1;
2342	uint8_t SIZE:3;
2343	uint8_t PROT0:1;
2344	uint8_t PROT1:1;
2345	uint8_t PROT2:1;
2346	uint8_t PROT3:1;
2347	} B;
2348	} REAT; /* RAM ECC Attributes Register */
2349
2350	union {
2351	uint32_t R;
2352	struct {
2353	uint32_t REDH:32;
2354	} B;
2355	} REDRH; /* RAM ECC Data High Register */
2356
2357	union {
2358	uint32_t R;
2359	struct {
2360	uint32_t REDL:32;
2361	} B;
2362	} REDRL; /* RAMECC Data Low Register */
2363
2364	};
2365	/****************************************************************************/
2366	/* MODULE : eDMA */
2367	/****************************************************************************/
2368	struct EDMA_tag {
2369	union {
2370	uint32_t R;
2371	struct {
2372	uint32_t:16;
2373	uint32_t GRP3PRI:2;
2374	uint32_t GRP2PRI:2;
2375	uint32_t GRP1PRI:2;
2376	uint32_t GRP0PRI:2;
2377	uint32_t:4;
2378	uint32_t ERGA:1;
2379	uint32_t ERCA:1;
2380	uint32_t EDBG:1;
2381	uint32_t EBW:1;
2382	} B;
2383	} CR; /* Control Register */
2384
2385	union {
2386	uint32_t R;
2387	struct {
2388	uint32_t VLD:1;
2389	uint32_t:15;
2390	uint32_t GPE:1;
2391	uint32_t CPE:1;
2392	uint32_t ERRCHN:6;
2393	uint32_t SAE:1;
2394	uint32_t SOE:1;
2395	uint32_t DAE:1;
2396	uint32_t DOE:1;
2397	uint32_t NCE:1;
2398	uint32_t SGE:1;
2399	uint32_t SBE:1;
2400	uint32_t DBE:1;
2401	} B;
2402	} ESR; /* Error Status Register */
2403
2404	union {
2405	uint32_t R;
2406	struct {
2407	uint32_t ERQ63:1;
2408	uint32_t ERQ62:1;
2409	uint32_t ERQ61:1;
2410	uint32_t ERQ60:1;
2411	uint32_t ERQ59:1;
2412	uint32_t ERQ58:1;
2413	uint32_t ERQ57:1;
2414	uint32_t ERQ56:1;
2415	uint32_t ERQ55:1;
2416	uint32_t ERQ54:1;
2417	uint32_t ERQ53:1;
2418	uint32_t ERQ52:1;
2419	uint32_t ERQ51:1;
2420	uint32_t ERQ50:1;
2421	uint32_t ERQ49:1;
2422	uint32_t ERQ48:1;
2423	uint32_t ERQ47:1;
2424	uint32_t ERQ46:1;
2425	uint32_t ERQ45:1;
2426	uint32_t ERQ44:1;
2427	uint32_t ERQ43:1;
2428	uint32_t ERQ42:1;
2429	uint32_t ERQ41:1;
2430	uint32_t ERQ40:1;
2431	uint32_t ERQ39:1;
2432	uint32_t ERQ38:1;
2433	uint32_t ERQ37:1;
2434	uint32_t ERQ36:1;
2435	uint32_t ERQ35:1;
2436	uint32_t ERQ34:1;
2437	uint32_t ERQ33:1;
2438	uint32_t ERQ32:1;
2439	} B;
2440	} ERQRH; /* DMA Enable Request Register High */
2441
2442	union {
2443	uint32_t R;
2444	struct {
2445	uint32_t ERQ31:1;
2446	uint32_t ERQ30:1;
2447	uint32_t ERQ29:1;
2448	uint32_t ERQ28:1;
2449	uint32_t ERQ27:1;
2450	uint32_t ERQ26:1;
2451	uint32_t ERQ25:1;
2452	uint32_t ERQ24:1;
2453	uint32_t ERQ23:1;
2454	uint32_t ERQ22:1;
2455	uint32_t ERQ21:1;
2456	uint32_t ERQ20:1;
2457	uint32_t ERQ19:1;
2458	uint32_t ERQ18:1;
2459	uint32_t ERQ17:1;
2460	uint32_t ERQ16:1;
2461	uint32_t ERQ15:1;
2462	uint32_t ERQ14:1;
2463	uint32_t ERQ13:1;
2464	uint32_t ERQ12:1;
2465	uint32_t ERQ11:1;
2466	uint32_t ERQ10:1;
2467	uint32_t ERQ09:1;
2468	uint32_t ERQ08:1;
2469	uint32_t ERQ07:1;
2470	uint32_t ERQ06:1;
2471	uint32_t ERQ05:1;
2472	uint32_t ERQ04:1;
2473	uint32_t ERQ03:1;
2474	uint32_t ERQ02:1;
2475	uint32_t ERQ01:1;
2476	uint32_t ERQ00:1;
2477	} B;
2478	} ERQRL; /* DMA Enable Request Register Low */
2479
2480	union {
2481	uint32_t R;
2482	struct {
2483	uint32_t EEI63:1;
2484	uint32_t EEI62:1;
2485	uint32_t EEI61:1;
2486	uint32_t EEI60:1;
2487	uint32_t EEI59:1;
2488	uint32_t EEI58:1;
2489	uint32_t EEI57:1;
2490	uint32_t EEI56:1;
2491	uint32_t EEI55:1;
2492	uint32_t EEI54:1;
2493	uint32_t EEI53:1;
2494	uint32_t EEI52:1;
2495	uint32_t EEI51:1;
2496	uint32_t EEI50:1;
2497	uint32_t EEI49:1;
2498	uint32_t EEI48:1;
2499	uint32_t EEI47:1;
2500	uint32_t EEI46:1;
2501	uint32_t EEI45:1;
2502	uint32_t EEI44:1;
2503	uint32_t EEI43:1;
2504	uint32_t EEI42:1;
2505	uint32_t EEI41:1;
2506	uint32_t EEI40:1;
2507	uint32_t EEI39:1;
2508	uint32_t EEI38:1;
2509	uint32_t EEI37:1;
2510	uint32_t EEI36:1;
2511	uint32_t EEI35:1;
2512	uint32_t EEI34:1;
2513	uint32_t EEI33:1;
2514	uint32_t EEI32:1;
2515	} B;
2516	} EEIRH; /* DMA Enable Error Interrupt Register High */
2517
2518	union {
2519	uint32_t R;
2520	struct {
2521	uint32_t EEI31:1;
2522	uint32_t EEI30:1;
2523	uint32_t EEI29:1;
2524	uint32_t EEI28:1;
2525	uint32_t EEI27:1;
2526	uint32_t EEI26:1;
2527	uint32_t EEI25:1;
2528	uint32_t EEI24:1;
2529	uint32_t EEI23:1;
2530	uint32_t EEI22:1;
2531	uint32_t EEI21:1;
2532	uint32_t EEI20:1;
2533	uint32_t EEI19:1;
2534	uint32_t EEI18:1;
2535	uint32_t EEI17:1;
2536	uint32_t EEI16:1;
2537	uint32_t EEI15:1;
2538	uint32_t EEI14:1;
2539	uint32_t EEI13:1;
2540	uint32_t EEI12:1;
2541	uint32_t EEI11:1;
2542	uint32_t EEI10:1;
2543	uint32_t EEI09:1;
2544	uint32_t EEI08:1;
2545	uint32_t EEI07:1;
2546	uint32_t EEI06:1;
2547	uint32_t EEI05:1;
2548	uint32_t EEI04:1;
2549	uint32_t EEI03:1;
2550	uint32_t EEI02:1;
2551	uint32_t EEI01:1;
2552	uint32_t EEI00:1;
2553	} B;
2554	} EEIRL; /* DMA Enable Error Interrupt Register Low */
2555
2556	union {
2557	uint8_t R;
2558	uint8_t B;
2559	} SERQR; /* DMA Set Enable Request Register */
2560
2561	union {
2562	uint8_t R;
2563	uint8_t B;
2564	} CERQR; /* DMA Clear Enable Request Register */
2565
2566	union {
2567	uint8_t R;
2568	uint8_t B;
2569	} SEEIR; /* DMA Set Enable Error Interrupt Register */
2570
2571	union {
2572	uint8_t R;
2573	uint8_t B;
2574	} CEEIR; /* DMA Clear Enable Error Interrupt REgister */
2575
2576	union {
2577	uint8_t R;
2578	uint8_t B;
2579	} CIRQR; /* DMA Clear Interrupt Request Register */
2580
2581	union {
2582	uint8_t R;
2583	uint8_t B;
2584	} CER; /* DMA Clear error Register */
2585
2586	union {
2587	uint8_t R;
2588	uint8_t B;
2589	} SSBR; /* Set Start Bit Register */
2590
2591	union {
2592	uint8_t R;
2593	uint8_t B;
2594	} CDSBR; /* Clear Done Status Bit Register */
2595
2596	union {
2597	uint32_t R;
2598	struct {
2599	uint32_t INT63:1;
2600	uint32_t INT62:1;
2601	uint32_t INT61:1;
2602	uint32_t INT60:1;
2603	uint32_t INT59:1;
2604	uint32_t INT58:1;
2605	uint32_t INT57:1;
2606	uint32_t INT56:1;
2607	uint32_t INT55:1;
2608	uint32_t INT54:1;
2609	uint32_t INT53:1;
2610	uint32_t INT52:1;
2611	uint32_t INT51:1;
2612	uint32_t INT50:1;
2613	uint32_t INT49:1;
2614	uint32_t INT48:1;
2615	uint32_t INT47:1;
2616	uint32_t INT46:1;
2617	uint32_t INT45:1;
2618	uint32_t INT44:1;
2619	uint32_t INT43:1;
2620	uint32_t INT42:1;
2621	uint32_t INT41:1;
2622	uint32_t INT40:1;
2623	uint32_t INT39:1;
2624	uint32_t INT38:1;
2625	uint32_t INT37:1;
2626	uint32_t INT36:1;
2627	uint32_t INT35:1;
2628	uint32_t INT34:1;
2629	uint32_t INT33:1;
2630	uint32_t INT32:1;
2631	} B;
2632	} IRQRH; /* DMA Interrupt Request High */
2633
2634	union {
2635	uint32_t R;
2636	struct {
2637	uint32_t INT31:1;
2638	uint32_t INT30:1;
2639	uint32_t INT29:1;
2640	uint32_t INT28:1;
2641	uint32_t INT27:1;
2642	uint32_t INT26:1;
2643	uint32_t INT25:1;
2644	uint32_t INT24:1;
2645	uint32_t INT23:1;
2646	uint32_t INT22:1;
2647	uint32_t INT21:1;
2648	uint32_t INT20:1;
2649	uint32_t INT19:1;
2650	uint32_t INT18:1;
2651	uint32_t INT17:1;
2652	uint32_t INT16:1;
2653	uint32_t INT15:1;
2654	uint32_t INT14:1;
2655	uint32_t INT13:1;
2656	uint32_t INT12:1;
2657	uint32_t INT11:1;
2658	uint32_t INT10:1;
2659	uint32_t INT09:1;
2660	uint32_t INT08:1;
2661	uint32_t INT07:1;
2662	uint32_t INT06:1;
2663	uint32_t INT05:1;
2664	uint32_t INT04:1;
2665	uint32_t INT03:1;
2666	uint32_t INT02:1;
2667	uint32_t INT01:1;
2668	uint32_t INT00:1;
2669	} B;
2670	} IRQRL; /* DMA Interrupt Request Low */
2671
2672	union {
2673	uint32_t R;
2674	struct {
2675	uint32_t ERR63:1;
2676	uint32_t ERR62:1;
2677	uint32_t ERR61:1;
2678	uint32_t ERR60:1;
2679	uint32_t ERR59:1;
2680	uint32_t ERR58:1;
2681	uint32_t ERR57:1;
2682	uint32_t ERR56:1;
2683	uint32_t ERR55:1;
2684	uint32_t ERR54:1;
2685	uint32_t ERR53:1;
2686	uint32_t ERR52:1;
2687	uint32_t ERR51:1;
2688	uint32_t ERR50:1;
2689	uint32_t ERR49:1;
2690	uint32_t ERR48:1;
2691	uint32_t ERR47:1;
2692	uint32_t ERR46:1;
2693	uint32_t ERR45:1;
2694	uint32_t ERR44:1;
2695	uint32_t ERR43:1;
2696	uint32_t ERR42:1;
2697	uint32_t ERR41:1;
2698	uint32_t ERR40:1;
2699	uint32_t ERR39:1;
2700	uint32_t ERR38:1;
2701	uint32_t ERR37:1;
2702	uint32_t ERR36:1;
2703	uint32_t ERR35:1;
2704	uint32_t ERR34:1;
2705	uint32_t ERR33:1;
2706	uint32_t ERR32:1;
2707	} B;
2708	} ERH; /* DMA Error High */
2709
2710	union {
2711	uint32_t R;
2712	struct {
2713	uint32_t ERR31:1;
2714	uint32_t ERR30:1;
2715	uint32_t ERR29:1;
2716	uint32_t ERR28:1;
2717	uint32_t ERR27:1;
2718	uint32_t ERR26:1;
2719	uint32_t ERR25:1;
2720	uint32_t ERR24:1;
2721	uint32_t ERR23:1;
2722	uint32_t ERR22:1;
2723	uint32_t ERR21:1;
2724	uint32_t ERR20:1;
2725	uint32_t ERR19:1;
2726	uint32_t ERR18:1;
2727	uint32_t ERR17:1;
2728	uint32_t ERR16:1;
2729	uint32_t ERR15:1;
2730	uint32_t ERR14:1;
2731	uint32_t ERR13:1;
2732	uint32_t ERR12:1;
2733	uint32_t ERR11:1;
2734	uint32_t ERR10:1;
2735	uint32_t ERR09:1;
2736	uint32_t ERR08:1;
2737	uint32_t ERR07:1;
2738	uint32_t ERR06:1;
2739	uint32_t ERR05:1;
2740	uint32_t ERR04:1;
2741	uint32_t ERR03:1;
2742	uint32_t ERR02:1;
2743	uint32_t ERR01:1;
2744	uint32_t ERR00:1;
2745	} B;
2746	} ERL; /* DMA Error Low */
2747
2748	uint32_t edma_reserved1[52];
2749
2750	union {
2751	uint8_t R;
2752	struct {
2753	uint8_t ECP:1;
2754	uint8_t:1;
2755	uint8_t GRPPRI:2;
2756	uint8_t CHPRI:4;
2757	} B;
2758	} CPR[64];
2759
2760	uint32_t edma_reserved2[944];
2761
2762	/****************************************************************************/
2763	/* DMA2 Transfer Control Descriptor */
2764	/****************************************************************************/
2765	struct tcd_t {
2766	uint32_t SADDR; /* source address */
2767
2768	/* Source and destination fields */
2769	union tcd_SDF_tag {
2770	uint32_t R;
2771	struct {
2772	uint16_t SMOD:5; /* source address modulo */
2773	uint16_t SSIZE:3; /* source transfer size */
2774	uint16_t DMOD:5; /* destination address modulo */
2775	uint16_t DSIZE:3; /* destination transfer size */
2776	int16_t SOFF; /* signed source address offset */
2777	} B;
2778	} SDF;
2779
2780	uint32_t NBYTES; /* inner (ÂminorÂ) byte count */
2781
2782	int32_t SLAST; /* last destination address adjustment, or
2783	scatter/gather address (if e_sg = 1) */
2784
2785	uint32_t DADDR; /* destination address */
2786
2787	/* CITER and destination fields */
2788	union tcd_CDF_tag {
2789	uint32_t R;
2790	struct {
2791	uint16_t CITERE_LINK:1;
2792	uint16_t CITER:15;
2793	int16_t DOFF; /* signed destination address offset */
2794	} B;
2795	struct {
2796	uint16_t CITERE_LINK:1;
2797	uint16_t CITERLINKCH:6;
2798	uint16_t CITER:9;
2799	int16_t DOFF;
2800	} B_ALT;
2801	} CDF;
2802
2803	int32_t DLAST_SGA;
2804
2805	/* BITER and misc fields */
2806	union tcd_BMF_tag {
2807	uint32_t R;
2808	struct {
2809	uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */
2810	uint32_t BITER:15;
2811	uint32_t BWC:2; /* bandwidth control */
2812	uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */
2813	uint32_t DONE:1; /* channel done */
2814	uint32_t ACTIVE:1; /* channel active */
2815	uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */
2816	uint32_t E_SG:1; /* enable scatter/gather descriptor */
2817	uint32_t D_REQ:1; /* disable ipd_req when done */
2818	uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
2819	uint32_t INT_MAJ:1; /* interrupt on major loop completion */
2820	uint32_t START:1; /* explicit channel start */
2821	} B;
2822	struct {
2823	uint32_t BITERE_LINK:1;
2824	uint32_t BITERLINKCH:6;
2825	uint32_t BITER:9;
2826	uint32_t BWC:2;
2827	uint32_t MAJORLINKCH:6;
2828	uint32_t DONE:1;
2829	uint32_t ACTIVE:1;
2830	uint32_t MAJORE_LINK:1;
2831	uint32_t E_SG:1;
2832	uint32_t D_REQ:1;
2833	uint32_t INT_HALF:1;
2834	uint32_t INT_MAJ:1;
2835	uint32_t START:1;
2836	} B_ALT;
2837	} BMF;
2838	} TCD[64]; /* transfer_control_descriptor */
2839	};
2840
2841	static const struct tcd_t EDMA_TCD_DEFAULT = {
2842	.SADDR = 0,
2843	.SDF = { .R = 0 },
2844	.NBYTES = 0,
2845	.SLAST = 0,
2846	.DADDR = 0,
2847	.CDF = { .R = 0 },
2848	.DLAST_SGA = 0,
2849	.BMF = { .R = 0 }
2850	};
2851
2852	#define EDMA_TCD_BITER_MASK 0x7fff
2853
2854	#define EDMA_TCD_BITER_SIZE DSPI_TCD_BITER_MASK
2855
2856	#define EDMA_TCD_BITER_LINKED_MASK 0x1ff
2857
2858	#define EDMA_TCD_BITER_LINKED_SIZE 512
2859
2860	#define EDMA_TCD_LINK_AND_BITER( link, biter) (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK))
2861
2862	#define EDMA_TCD_BITER_LINK( channel) (EDMA.TCD [(channel)].BMF.B.BITER >> 9)
2863
2864	/****************************************************************************/
2865	/* MODULE : INTC */
2866	/****************************************************************************/
2867	struct INTC_tag {
2868	union {
2869	uint32_t R;
2870	struct {
2871	uint32_t:26;
2872	uint32_t VTES:1;
2873	uint32_t:4;
2874	uint32_t HVEN:1;
2875	} B;
2876	} MCR; /* Module Configuration Register */
2877
2878	int32_t INTC_reserved00;
2879
2880	union {
2881	uint32_t R;
2882	struct {
2883	uint32_t:28;
2884	uint32_t PRI:4;
2885	} B;
2886	} CPR; /* Current Priority Register */
2887
2888	uint32_t intc_reserved1;
2889
2890	union {
2891	uint32_t R;
2892	struct {
2893	uint32_t VTBA:21;
2894	uint32_t INTVEC:9;
2895	uint32_t:2;
2896	} B;
2897	} IACKR; /* Interrupt Acknowledge Register */
2898
2899	uint32_t intc_reserved2;
2900
2901	union {
2902	uint32_t R;
2903	struct {
2904	uint32_t:32;
2905	} B;
2906	} EOIR; /* End of Interrupt Register */
2907
2908	uint32_t intc_reserved3;
2909
2910	union {
2911	uint8_t R;
2912	struct {
2913	uint8_t:6;
2914	uint8_t SET:1;
2915	uint8_t CLR:1;
2916	} B;
2917	} SSCIR[8]; /* Software Set/Clear Interruput Register */
2918
2919	uint32_t intc_reserved4[6];
2920
2921	union {
2922	uint8_t R;
2923	struct {
2924	uint8_t:4;
2925	uint8_t PRI:4;
2926	} B;
2927	} PSR[307]; /* Software Set/Clear Interrupt Register */
2928
2929	};
2930	/****************************************************************************/
2931	/* MODULE : EQADC */
2932	/****************************************************************************/
2933	struct EQADC_tag {
2934	union {
2935	uint32_t R;
2936	struct {
2937	uint32_t:27;
2938	uint32_t ESSIE:2;
2939	uint32_t:1;
2940	uint32_t DBG:2;
2941	} B;
2942	} MCR; /* Module Configuration Register */
2943
2944	int32_t EQADC_reserved00;
2945
2946	union {
2947	uint32_t R;
2948	struct {
2949	uint32_t:6;
2950	uint32_t NMF:26;
2951	} B;
2952	} NMSFR; /* Null Message Send Format Register */
2953
2954	union {
2955	uint32_t R;
2956	struct {
2957	uint32_t:28;
2958	uint32_t DFL:4;
2959	} B;
2960	} ETDFR; /* External Trigger Digital Filter Register */
2961
2962	union {
2963	uint32_t R;
2964	struct {
2965	uint32_t CFPUSH:32;
2966	} B;
2967	} CFPR[6]; /* CFIFO Push Registers */
2968
2969	uint32_t eqadc_reserved1;
2970
2971	uint32_t eqadc_reserved2;
2972
2973	union {
2974	uint32_t R;
2975	struct {
2976	uint32_t:16;
2977	uint32_t RFPOP:16;
2978	} B;
2979	} RFPR[6]; /* Result FIFO Pop Registers */
2980
2981	uint32_t eqadc_reserved3;
2982
2983	uint32_t eqadc_reserved4;
2984
2985	union {
2986	uint16_t R;
2987	struct {
2988	uint16_t:5;
2989	uint16_t SSE:1;
2990	uint16_t CFINV:1;
2991	uint16_t:1;
2992	uint16_t MODE:4;
2993	uint16_t:4;
2994	} B;
2995	} CFCR[6]; /* CFIFO Control Registers */
2996
2997	uint32_t eqadc_reserved5;
2998
2999	union {
3000	uint16_t R;
3001	struct {
3002	uint16_t NCIE:1;
3003	uint16_t TORIE:1;
3004	uint16_t PIE:1;
3005	uint16_t EOQIE:1;
3006	uint16_t CFUIE:1;
3007	uint16_t:1;
3008	uint16_t CFFE:1;
3009	uint16_t CFFS:1;
3010	uint16_t:4;
3011	uint16_t RFOIE:1;
3012	uint16_t:1;
3013	uint16_t RFDE:1;
3014	uint16_t RFDS:1;
3015	} B;
3016	} IDCR[6]; /* Interrupt and DMA Control Registers */
3017
3018	uint32_t eqadc_reserved6;
3019
3020	union {
3021	uint32_t R;
3022	struct {
3023	uint32_t NCF:1;
3024	uint32_t TORF:1;
3025	uint32_t PF:1;
3026	uint32_t EOQF:1;
3027	uint32_t CFUF:1;
3028	uint32_t SSS:1;
3029	uint32_t CFFF:1;
3030	uint32_t:5;
3031	uint32_t RFOF:1;
3032	uint32_t:1;
3033	uint32_t RFDF:1;
3034	uint32_t:1;
3035	uint32_t CFCTR:4;
3036	uint32_t TNXTPTR:4;
3037	uint32_t RFCTR:4;
3038	uint32_t POPNXTPTR:4;
3039	} B;
3040	} FISR[6]; /* FIFO and Interrupt Status Registers */
3041
3042	uint32_t eqadc_reserved7;
3043
3044	uint32_t eqadc_reserved8;
3045
3046	union {
3047	uint16_t R;
3048	struct {
3049	uint16_t:5;
3050	uint16_t TCCF:11;
3051	} B;
3052	} CFTCR[6]; /* CFIFO Transfer Counter Registers */
3053
3054	uint32_t eqadc_reserved9;
3055
3056	union {
3057	uint32_t R;
3058	struct {
3059	uint32_t CFS0:2;
3060	uint32_t CFS1:2;
3061	uint32_t CFS2:2;
3062	uint32_t CFS3:2;
3063	uint32_t CFS4:2;
3064	uint32_t CFS5:2;
3065	uint32_t:5;
3066	uint32_t LCFTCB0:4;
3067	uint32_t TC_LCFTCB0:11;
3068	} B;
3069	} CFSSR0; /* CFIFO Status Register 0 */
3070
3071	union {
3072	uint32_t R;
3073	struct {
3074	uint32_t CFS0:2;
3075	uint32_t CFS1:2;
3076	uint32_t CFS2:2;
3077	uint32_t CFS3:2;
3078	uint32_t CFS4:2;
3079	uint32_t CFS5:2;
3080	uint32_t:5;
3081	uint32_t LCFTCB1:4;
3082	uint32_t TC_LCFTCB1:11;
3083	} B;
3084	} CFSSR1; /* CFIFO Status Register 1 */
3085
3086	union {
3087	uint32_t R;
3088	struct {
3089	uint32_t CFS0:2;
3090	uint32_t CFS1:2;
3091	uint32_t CFS2:2;
3092	uint32_t CFS3:2;
3093	uint32_t CFS4:2;
3094	uint32_t CFS5:2;
3095	uint32_t:4;
3096	uint32_t ECBNI:1;
3097	uint32_t LCFTSSI:4;
3098	uint32_t TC_LCFTSSI:11;
3099	} B;
3100	} CFSSR2; /* CFIFO Status Register 2 */
3101
3102	union {
3103	uint32_t R;
3104	struct {
3105	uint32_t CFS0:2;
3106	uint32_t CFS1:2;
3107	uint32_t CFS2:2;
3108	uint32_t CFS3:2;
3109	uint32_t CFS4:2;
3110	uint32_t CFS5:2;
3111	uint32_t:20;
3112	} B;
3113	} CFSR;
3114
3115	uint32_t eqadc_reserved11;
3116
3117	union {
3118	uint32_t R;
3119	struct {
3120	uint32_t:21;
3121	uint32_t MDT:3;
3122	uint32_t:4;
3123	uint32_t BR:4;
3124	} B;
3125	} SSICR; /* SSI Control Register */
3126
3127	union {
3128	uint32_t R;
3129	struct {
3130	uint32_t RDV:1;
3131	uint32_t:5;
3132	uint32_t RDATA:26;
3133	} B;
3134	} SSIRDR; /* SSI Recieve Data Register */
3135
3136	uint32_t eqadc_reserved12[17];
3137
3138	struct {
3139	union {
3140	uint32_t R;
3141	struct {
3142	uint32_t:32;
3143	} B;
3144	} R[4];
3145
3146	uint32_t eqadc_reserved13[12];
3147
3148	} CF[6];
3149
3150	uint32_t eqadc_reserved14[32];
3151
3152	struct {
3153	union {
3154	uint32_t R;
3155	struct {
3156	uint32_t:32;
3157	} B;
3158	} R[4];
3159
3160	uint32_t eqadc_reserved15[12];
3161
3162	} RF[6];
3163
3164	};
3165	/****************************************************************************/
3166	/* MODULE : DSPI */
3167	/****************************************************************************/
3168	struct DSPI_tag {
3169	union DSPI_MCR_tag {
3170	uint32_t R;
3171	struct {
3172	uint32_t MSTR:1;
3173	uint32_t CONT_SCKE:1;
3174	uint32_t DCONF:2;
3175	uint32_t FRZ:1;
3176	uint32_t MTFE:1;
3177	uint32_t PCSSE:1;
3178	uint32_t ROOE:1;
3179	uint32_t:2;
3180	uint32_t PCSIS5:1;
3181	uint32_t PCSIS4:1;
3182	uint32_t PCSIS3:1;
3183	uint32_t PCSIS2:1;
3184	uint32_t PCSIS1:1;
3185	uint32_t PCSIS0:1;
3186	uint32_t DOZE:1;
3187	uint32_t MDIS:1;
3188	uint32_t DIS_TXF:1;
3189	uint32_t DIS_RXF:1;
3190	uint32_t CLR_TXF:1;
3191	uint32_t CLR_RXF:1;
3192	uint32_t SMPL_PT:2;
3193	uint32_t:7;
3194	uint32_t HALT:1;
3195	} B;
3196	} MCR; /* Module Configuration Register */
3197
3198	uint32_t dspi_reserved1;
3199
3200	union {
3201	uint32_t R;
3202	struct {
3203	uint32_t TCNT:16;
3204	uint32_t:16;
3205	} B;
3206	} TCR;
3207
3208	union DSPI_CTAR_tag {
3209	uint32_t R;
3210	struct {
3211	uint32_t DBR:1;
3212	uint32_t FMSZ:4;
3213	uint32_t CPOL:1;
3214	uint32_t CPHA:1;
3215	uint32_t LSBFE:1;
3216	uint32_t PCSSCK:2;
3217	uint32_t PASC:2;
3218	uint32_t PDT:2;
3219	uint32_t PBR:2;
3220	uint32_t CSSCK:4;
3221	uint32_t ASC:4;
3222	uint32_t DT:4;
3223	uint32_t BR:4;
3224	} B;
3225	} CTAR[8]; /* Clock and Transfer Attributes Registers */
3226
3227	union DSPI_SR_tag {
3228	uint32_t R;
3229	struct {
3230	uint32_t TCF:1;
3231	uint32_t TXRXS:1;
3232	uint32_t:1;
3233	uint32_t EOQF:1;
3234	uint32_t TFUF:1;
3235	uint32_t:1;
3236	uint32_t TFFF:1;
3237	uint32_t:5;
3238	uint32_t RFOF:1;
3239	uint32_t:1;
3240	uint32_t RFDF:1;
3241	uint32_t:1;
3242	uint32_t TXCTR:4;
3243	uint32_t TXNXTPTR:4;
3244	uint32_t RXCTR:4;
3245	uint32_t POPNXTPTR:4;
3246	} B;
3247	} SR; /* Status Register */
3248
3249	union DSPI_RSER_tag {
3250	uint32_t R;
3251	struct {
3252	uint32_t TCFRE:1;
3253	uint32_t:2;
3254	uint32_t EOQFRE:1;
3255	uint32_t TFUFRE:1;
3256	uint32_t:1;
3257	uint32_t TFFFRE:1;
3258	uint32_t TFFFDIRS:1;
3259	uint32_t:4;
3260	uint32_t RFOFRE:1;
3261	uint32_t:1;
3262	uint32_t RFDFRE:1;
3263	uint32_t RFDFDIRS:1;
3264	uint32_t:16;
3265	} B;
3266	} RSER; /* DMA/Interrupt Request Select and Enable Register */
3267
3268	union DSPI_PUSHR_tag {
3269	uint32_t R;
3270	struct {
3271	uint32_t CONT:1;
3272	uint32_t CTAS:3;
3273	uint32_t EOQ:1;
3274	uint32_t CTCNT:1;
3275	uint32_t:4;
3276	uint32_t PCS5:1;
3277	uint32_t PCS4:1;
3278	uint32_t PCS3:1;
3279	uint32_t PCS2:1;
3280	uint32_t PCS1:1;
3281	uint32_t PCS0:1;
3282	uint32_t TXDATA:16;
3283	} B;
3284	} PUSHR; /* PUSH TX FIFO Register */
3285
3286	union DSPI_POPR_tag{
3287	uint32_t R;
3288	struct {
3289	uint32_t:16;
3290	uint32_t RXDATA:16;
3291	} B;
3292	} POPR; /* POP RX FIFO Register */
3293
3294	union {
3295	uint32_t R;
3296	struct {
3297	uint32_t TXCMD:16;
3298	uint32_t TXDATA:16;
3299	} B;
3300	} TXFR[4]; /* Transmit FIFO Registers */
3301
3302	uint32_t DSPI_reserved_txf[12];
3303
3304	union {
3305	uint32_t R;
3306	struct {
3307	uint32_t:16;
3308	uint32_t RXDATA:16;
3309	} B;
3310	} RXFR[4]; /* Transmit FIFO Registers */
3311
3312	uint32_t DSPI_reserved_rxf[12];
3313
3314	union {
3315	uint32_t R;
3316	struct {
3317	uint32_t MTOE:1;
3318	uint32_t:1;
3319	uint32_t MTOCNT:6;
3320	uint32_t:4;
3321	uint32_t TXSS:1;
3322	uint32_t TPOL:1;
3323	uint32_t TRRE:1;
3324	uint32_t CID:1;
3325	uint32_t DCONT:1;
3326	uint32_t DSICTAS:3;
3327	uint32_t:6;
3328	uint32_t DPCS5:1;
3329	uint32_t DPCS4:1;
3330	uint32_t DPCS3:1;
3331	uint32_t DPCS2:1;
3332	uint32_t DPCS1:1;
3333	uint32_t DPCS0:1;
3334	} B;
3335	} DSICR; /* DSI Configuration Register */
3336
3337	union {
3338	uint32_t R;
3339	struct {
3340	uint32_t:16;
3341	uint32_t SER_DATA:16;
3342	} B;
3343	} SDR; /* DSI Serialization Data Register */
3344
3345	union {
3346	uint32_t R;
3347	struct {
3348	uint32_t:16;
3349	uint32_t ASER_DATA:16;
3350	} B;
3351	} ASDR; /* DSI Alternate Serialization Data Register */
3352
3353	union {
3354	uint32_t R;
3355	struct {
3356	uint32_t:16;
3357	uint32_t COMP_DATA:16;
3358	} B;
3359	} COMPR; /* DSI Transmit Comparison Register */
3360
3361	union {
3362	uint32_t R;
3363	struct {
3364	uint32_t:16;
3365	uint32_t DESER_DATA:16;
3366	} B;
3367	} DDR; /* DSI deserialization Data Register */
3368
3369	};
3370	/****************************************************************************/
3371	/* MODULE : eSCI */
3372	/****************************************************************************/
3373	struct ESCI_tag {
3374	union ESCI_CR1_tag {
3375	uint32_t R;
3376	struct {
3377	uint32_t:3;
3378	uint32_t SBR:13;
3379	uint32_t LOOPS:1;
3380	uint32_t SCISDOZ:1;
3381	uint32_t RSRC:1;
3382	uint32_t M:1;
3383	uint32_t WAKE:1;
3384	uint32_t ILT:1;
3385	uint32_t PE:1;
3386	uint32_t PT:1;
3387	uint32_t TIE:1;
3388	uint32_t TCIE:1;
3389	uint32_t RIE:1;
3390	uint32_t ILIE:1;
3391	uint32_t TE:1;
3392	uint32_t RE:1;
3393	uint32_t RWU:1;
3394	uint32_t SBK:1;
3395	} B;
3396	} CR1; /* Control Register 1 */
3397
3398	union ESCI_CR2_tag {
3399	uint16_t R;
3400	struct {
3401	uint16_t MDIS:1;
3402	uint16_t FBR:1;
3403	uint16_t BSTP:1;
3404	uint16_t IEBERR:1;
3405	uint16_t RXDMA:1;
3406	uint16_t TXDMA:1;
3407	uint16_t BRK13:1;
3408	uint16_t:1;
3409	uint16_t BESM13:1;
3410	uint16_t SBSTP:1;
3411	uint16_t:2;
3412	uint16_t ORIE:1;
3413	uint16_t NFIE:1;
3414	uint16_t FEIE:1;
3415	uint16_t PFIE:1;
3416	} B;
3417	} CR2; /* Control Register 2 */
3418
3419	union ESCI_DR_tag {
3420	uint16_t R;
3421	struct {
3422	uint16_t R8:1;
3423	uint16_t T8:1;
3424	uint16_t:6;
3425	uint8_t D;
3426	} B;
3427	} DR; /* Data Register */
3428
3429	union ESCI_SR_tag {
3430	uint32_t R;
3431	struct {
3432	uint32_t TDRE:1;
3433	uint32_t TC:1;
3434	uint32_t RDRF:1;
3435	uint32_t IDLE:1;
3436	uint32_t OR:1;
3437	uint32_t NF:1;
3438	uint32_t FE:1;
3439	uint32_t PF:1;
3440	uint32_t:3;
3441	uint32_t BERR:1;
3442	uint32_t:3;
3443	uint32_t RAF:1;
3444	uint32_t RXRDY:1;
3445	uint32_t TXRDY:1;
3446	uint32_t LWAKE:1;
3447	uint32_t STO:1;
3448	uint32_t PBERR:1;
3449	uint32_t CERR:1;
3450	uint32_t CKERR:1;
3451	uint32_t FRC:1;
3452	uint32_t:7;
3453	uint32_t OVFL:1;
3454	} B;
3455	} SR; /* Status Register */
3456
3457	union {
3458	uint32_t R;
3459	struct {
3460	uint32_t LRES:1;
3461	uint32_t WU:1;
3462	uint32_t WUD0:1;
3463	uint32_t WUD1:1;
3464	uint32_t LDBG:1;
3465	uint32_t DSF:1;
3466	uint32_t PRTY:1;
3467	uint32_t LIN:1;
3468	uint32_t RXIE:1;
3469	uint32_t TXIE:1;
3470	uint32_t WUIE:1;
3471	uint32_t STIE:1;
3472	uint32_t PBIE:1;
3473	uint32_t CIE:1;
3474	uint32_t CKIE:1;
3475	uint32_t FCIE:1;
3476	uint32_t:7;
3477	uint32_t OFIE:1;
3478	uint32_t:8;
3479	} B;
3480	} LCR; /* LIN Control Register */
3481
3482	union {
3483	uint32_t R;
3484	} LTR; /* LIN Transmit Register */
3485
3486	union {
3487	uint32_t R;
3488	} LRR; /* LIN Recieve Register */
3489
3490	union {
3491	uint32_t R;
3492	} LPR; /* LIN CRC Polynom Register */
3493
3494	};
3495	/****************************************************************************/
3496	/* MODULE : FlexCAN */
3497	/****************************************************************************/
3498	struct FLEXCAN2_tag {
3499	union {
3500	uint32_t R;
3501	struct {
3502	uint32_t MDIS:1;
3503	uint32_t FRZ:1;
3504	uint32_t:1;
3505	uint32_t HALT:1;
3506	uint32_t NOTRDY:1;
3507	uint32_t:1;
3508	uint32_t SOFTRST:1;
3509	uint32_t FRZACK:1;
3510	uint32_t:1;
3511	uint32_t:1;
3512
3513	uint32_t WRNEN:1;
3514
3515	uint32_t MDISACK:1;
3516	uint32_t:1;
3517	uint32_t:1;
3518
3519	uint32_t SRXDIS:1;
3520	uint32_t MBFEN:1;
3521	uint32_t:10;
3522
3523	uint32_t MAXMB:6;
3524	} B;
3525	} MCR; /* Module Configuration Register */
3526
3527	union {
3528	uint32_t R;
3529	struct {
3530	uint32_t PRESDIV:8;
3531	uint32_t RJW:2;
3532	uint32_t PSEG1:3;
3533	uint32_t PSEG2:3;
3534	uint32_t BOFFMSK:1;
3535	uint32_t ERRMSK:1;
3536	uint32_t CLKSRC:1;
3537	uint32_t LPB:1;
3538
3539	uint32_t TWRNMSK:1;
3540	uint32_t RWRNMSK:1;
3541	uint32_t:2;
3542
3543	uint32_t SMP:1;
3544	uint32_t BOFFREC:1;
3545	uint32_t TSYN:1;
3546	uint32_t LBUF:1;
3547	uint32_t LOM:1;
3548	uint32_t PROPSEG:3;
3549	} B;
3550	} CR; /* Control Register */
3551
3552	union {
3553	uint32_t R;
3554	} TIMER; /* Free Running Timer */
3555	int32_t FLEXCAN_reserved00;
3556
3557	union {
3558	uint32_t R;
3559	struct {
3560	uint32_t:3;
3561	uint32_t MI:29;
3562	} B;
3563	} RXGMASK; /* RX Global Mask */
3564
3565	union {
3566	uint32_t R;
3567	struct {
3568	uint32_t:3;
3569	uint32_t MI:29;
3570	} B;
3571	} RX14MASK; /* RX 14 Mask */
3572
3573	union {
3574	uint32_t R;
3575	struct {
3576	uint32_t:3;
3577	uint32_t MI:29;
3578	} B;
3579	} RX15MASK; /* RX 15 Mask */
3580
3581	union {
3582	uint32_t R;
3583	struct {
3584	uint32_t:16;
3585	uint32_t RXECNT:8;
3586	uint32_t TXECNT:8;
3587	} B;
3588	} ECR; /* Error Counter Register */
3589
3590	union {
3591	uint32_t R;
3592	struct {
3593	uint32_t:14;
3594
3595	uint32_t TWRNINT:1;
3596	uint32_t RWRNINT:1;
3597
3598	uint32_t BIT1ERR:1;
3599	uint32_t BIT0ERR:1;
3600	uint32_t ACKERR:1;
3601	uint32_t CRCERR:1;
3602	uint32_t FRMERR:1;
3603	uint32_t STFERR:1;
3604	uint32_t TXWRN:1;
3605	uint32_t RXWRN:1;
3606	uint32_t IDLE:1;
3607	uint32_t TXRX:1;
3608	uint32_t FLTCONF:2;
3609	uint32_t:1;
3610	uint32_t BOFFINT:1;
3611	uint32_t ERRINT:1;
3612	uint32_t:1;
3613	} B;
3614	} ESR; /* Error and Status Register */
3615
3616	union {
3617	uint32_t R;
3618	struct {
3619	uint32_t BUF63M:1;
3620	uint32_t BUF62M:1;
3621	uint32_t BUF61M:1;
3622	uint32_t BUF60M:1;
3623	uint32_t BUF59M:1;
3624	uint32_t BUF58M:1;
3625	uint32_t BUF57M:1;
3626	uint32_t BUF56M:1;
3627	uint32_t BUF55M:1;
3628	uint32_t BUF54M:1;
3629	uint32_t BUF53M:1;
3630	uint32_t BUF52M:1;
3631	uint32_t BUF51M:1;
3632	uint32_t BUF50M:1;
3633	uint32_t BUF49M:1;
3634	uint32_t BUF48M:1;
3635	uint32_t BUF47M:1;
3636	uint32_t BUF46M:1;
3637	uint32_t BUF45M:1;
3638	uint32_t BUF44M:1;
3639	uint32_t BUF43M:1;
3640	uint32_t BUF42M:1;
3641	uint32_t BUF41M:1;
3642	uint32_t BUF40M:1;
3643	uint32_t BUF39M:1;
3644	uint32_t BUF38M:1;
3645	uint32_t BUF37M:1;
3646	uint32_t BUF36M:1;
3647	uint32_t BUF35M:1;
3648	uint32_t BUF34M:1;
3649	uint32_t BUF33M:1;
3650	uint32_t BUF32M:1;
3651	} B;
3652	} IMRH; /* Interruput Masks Register */
3653
3654	union {
3655	uint32_t R;
3656	struct {
3657	uint32_t BUF31M:1;
3658	uint32_t BUF30M:1;
3659	uint32_t BUF29M:1;
3660	uint32_t BUF28M:1;
3661	uint32_t BUF27M:1;
3662	uint32_t BUF26M:1;
3663	uint32_t BUF25M:1;
3664	uint32_t BUF24M:1;
3665	uint32_t BUF23M:1;
3666	uint32_t BUF22M:1;
3667	uint32_t BUF21M:1;
3668	uint32_t BUF20M:1;
3669	uint32_t BUF19M:1;
3670	uint32_t BUF18M:1;
3671	uint32_t BUF17M:1;
3672	uint32_t BUF16M:1;
3673	uint32_t BUF15M:1;
3674	uint32_t BUF14M:1;
3675	uint32_t BUF13M:1;
3676	uint32_t BUF12M:1;
3677	uint32_t BUF11M:1;
3678	uint32_t BUF10M:1;
3679	uint32_t BUF09M:1;
3680	uint32_t BUF08M:1;
3681	uint32_t BUF07M:1;
3682	uint32_t BUF06M:1;
3683	uint32_t BUF05M:1;
3684	uint32_t BUF04M:1;
3685	uint32_t BUF03M:1;
3686	uint32_t BUF02M:1;
3687	uint32_t BUF01M:1;
3688	uint32_t BUF00M:1;
3689	} B;
3690	} IMRL; /* Interruput Masks Register */
3691
3692	union {
3693	uint32_t R;
3694	struct {
3695	uint32_t BUF63I:1;
3696	uint32_t BUF62I:1;
3697	uint32_t BUF61I:1;
3698	uint32_t BUF60I:1;
3699	uint32_t BUF59I:1;
3700	uint32_t BUF58I:1;
3701	uint32_t BUF57I:1;
3702	uint32_t BUF56I:1;
3703	uint32_t BUF55I:1;
3704	uint32_t BUF54I:1;
3705	uint32_t BUF53I:1;
3706	uint32_t BUF52I:1;
3707	uint32_t BUF51I:1;
3708	uint32_t BUF50I:1;
3709	uint32_t BUF49I:1;
3710	uint32_t BUF48I:1;
3711	uint32_t BUF47I:1;
3712	uint32_t BUF46I:1;
3713	uint32_t BUF45I:1;
3714	uint32_t BUF44I:1;
3715	uint32_t BUF43I:1;
3716	uint32_t BUF42I:1;
3717	uint32_t BUF41I:1;
3718	uint32_t BUF40I:1;
3719	uint32_t BUF39I:1;
3720	uint32_t BUF38I:1;
3721	uint32_t BUF37I:1;
3722	uint32_t BUF36I:1;
3723	uint32_t BUF35I:1;
3724	uint32_t BUF34I:1;
3725	uint32_t BUF33I:1;
3726	uint32_t BUF32I:1;
3727	} B;
3728	} IFRH; /* Interruput Flag Register */
3729
3730	union {
3731	uint32_t R;
3732	struct {
3733	uint32_t BUF31I:1;
3734	uint32_t BUF30I:1;
3735	uint32_t BUF29I:1;
3736	uint32_t BUF28I:1;
3737	uint32_t BUF27I:1;
3738	uint32_t BUF26I:1;
3739	uint32_t BUF25I:1;
3740	uint32_t BUF24I:1;
3741	uint32_t BUF23I:1;
3742	uint32_t BUF22I:1;
3743	uint32_t BUF21I:1;
3744	uint32_t BUF20I:1;
3745	uint32_t BUF19I:1;
3746	uint32_t BUF18I:1;
3747	uint32_t BUF17I:1;
3748	uint32_t BUF16I:1;
3749	uint32_t BUF15I:1;
3750	uint32_t BUF14I:1;
3751	uint32_t BUF13I:1;
3752	uint32_t BUF12I:1;
3753	uint32_t BUF11I:1;
3754	uint32_t BUF10I:1;
3755	uint32_t BUF09I:1;
3756	uint32_t BUF08I:1;
3757	uint32_t BUF07I:1;
3758	uint32_t BUF06I:1;
3759	uint32_t BUF05I:1;
3760	uint32_t BUF04I:1;
3761	uint32_t BUF03I:1;
3762	uint32_t BUF02I:1;
3763	uint32_t BUF01I:1;
3764	uint32_t BUF00I:1;
3765	} B;
3766	} IFRL; /* Interruput Flag Register */
3767
3768	uint32_t flexcan2_reserved2[19];
3769
3770	struct canbuf_t {
3771	union {
3772	uint32_t R;
3773	struct {
3774	uint32_t:4;
3775	uint32_t CODE:4;
3776	uint32_t:1;
3777	uint32_t SRR:1;
3778	uint32_t IDE:1;
3779	uint32_t RTR:1;
3780	uint32_t LENGTH:4;
3781	uint32_t TIMESTAMP:16;
3782	} B;
3783	} CS;
3784
3785	union {
3786	uint32_t R;
3787	struct {
3788	uint32_t:3;
3789	uint32_t STD_ID:11;
3790	uint32_t EXT_ID:18;
3791	} B;
3792	} ID;
3793
3794	union {
3795	uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
3796	uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
3797	uint32_t W[2]; /* Data buffer in words (32 bits) */
3798	uint32_t R[2]; /* Data buffer in words (32 bits) */
3799	} DATA;
3800
3801	} BUF[64];
3802
3803	uint32_t flexcan2_reserved3[256];
3804
3805	union {
3806	uint32_t R;
3807	struct {
3808	uint32_t:3;
3809	uint32_t MI:29;
3810	} B;
3811	} RXIMR[64]; /* RX Individual Mask Registers */
3812
3813	};
3814	/****************************************************************************/
3815	/* MODULE : FEC */
3816	/****************************************************************************/
3817	struct FEC_tag {
3818
3819	uint32_t fec_reserved_start[0x1];
3820
3821	union {
3822	uint32_t R;
3823	struct {
3824	uint32_t HBERR:1;
3825	uint32_t BABR:1;
3826	uint32_t BABT:1;
3827	uint32_t GRA:1;
3828	uint32_t TXF:1;
3829	uint32_t TXB:1;
3830	uint32_t RXF:1;
3831	uint32_t RXB:1;
3832	uint32_t MII:1;
3833	uint32_t EBERR:1;
3834	uint32_t LC:1;
3835	uint32_t RL:1;
3836	uint32_t UN:1;
3837	uint32_t:19;
3838	} B;
3839	} EIR; /* Interrupt Event Register */
3840
3841	union {
3842	uint32_t R;
3843	struct {
3844	uint32_t HBERRM:1;
3845	uint32_t BABRM:1;
3846	uint32_t BABTM:1;
3847	uint32_t GRAM:1;
3848	uint32_t TXFM:1;
3849	uint32_t TXBM:1;
3850	uint32_t RXFM:1;
3851	uint32_t RXBM:1;
3852	uint32_t MIIM:1;
3853	uint32_t EBERRM:1;
3854	uint32_t LCM:1;
3855	uint32_t RLM:1;
3856	uint32_t UNM:1;
3857	uint32_t:19;
3858	} B;
3859	} EIMR; /* Interrupt Mask Register */
3860
3861	uint32_t fec_reserved_eimr;
3862
3863	union {
3864	uint32_t R;
3865	struct {
3866	uint32_t:7;
3867	uint32_t R_DES_ACTIVE:1;
3868	uint32_t:24;
3869	} B;
3870	} RDAR; /* Receive Descriptor Active Register */
3871
3872	union {
3873	uint32_t R;
3874	struct {
3875	uint32_t:7;
3876	uint32_t X_DES_ACTIVE:1;
3877	uint32_t:24;
3878	} B;
3879	} TDAR; /* Transmit Descriptor Active Register */
3880
3881	uint32_t fec_reserved_tdar[3];
3882
3883	union {
3884	uint32_t R;
3885	struct {
3886	uint32_t:30;
3887	uint32_t ETHER_EN:1;
3888	uint32_t RESET:1;
3889	} B;
3890	} ECR; /* Ethernet Control Register */
3891
3892	uint32_t fec_reserved_ecr[6];
3893
3894	union {
3895	uint32_t R;
3896	struct {
3897	uint32_t ST:2;
3898	uint32_t CP:2;
3899	uint32_t PA:5;
3900	uint32_t RA:5;
3901	uint32_t TA:2;
3902	uint32_t DATA:16;
3903	} B;
3904	} MDATA; /* MII Data Register */
3905
3906	union {
3907	uint32_t R;
3908	struct {
3909	uint32_t:24;
3910	uint32_t DIS_PREAMBLE:1;
3911	uint32_t MII_SPEED:6;
3912	uint32_t:1;
3913	} B;
3914	} MSCR; /* MII Speed Control Register */
3915
3916	uint32_t fec_reserved_mscr[7];
3917
3918	union {
3919	uint32_t R;
3920	struct {
3921	uint32_t MIB_DISABLE:1;
3922	uint32_t MIB_IDLE:1;
3923	uint32_t:30;
3924	} B;
3925	} MIBC; /* MIB Control Register */
3926
3927	uint32_t fec_reserved_mibc[7];
3928
3929	union {
3930	uint32_t R;
3931	struct {
3932	uint32_t:5;
3933	uint32_t MAX_FL:11;
3934	uint32_t:10;
3935	uint32_t FCE:1;
3936	uint32_t BC_REJ:1;
3937	uint32_t PROM:1;
3938	uint32_t MII_MODE:1;
3939	uint32_t DRT:1;
3940	uint32_t LOOP:1;
3941	} B;
3942	} RCR; /* Receive Control Register */
3943
3944	uint32_t fec_reserved_rcr[15];
3945
3946	union {
3947	uint32_t R;
3948	struct {
3949	uint32_t:27;
3950	uint32_t RFC_PAUSE:1;
3951	uint32_t TFC_PAUSE:1;
3952	uint32_t FDEN:1;
3953	uint32_t HBC:1;
3954	uint32_t GTS:1;
3955	} B;
3956	} TCR; /* Transmit Control Register */
3957
3958	uint32_t fec_reserved_tcr[7];
3959
3960	union {
3961	uint32_t R;
3962	struct {
3963	uint32_t PADDR1:32;
3964	} B;
3965	} PALR; /* Physical Address Low Register */
3966
3967	union {
3968	uint32_t R;
3969	struct {
3970	uint32_t PADDR2:16;
3971	uint32_t TYPE:16;
3972	} B;
3973	} PAUR; /* Physical Address High + Type Register */
3974
3975	union {
3976	uint32_t R;
3977	struct {
3978	uint32_t OPCODE:16;
3979	uint32_t PAUSE_DUR:16;
3980	} B;
3981	} OPD; /* Opcode/Pause Duration Register */
3982
3983	uint32_t fec_reserved_opd[10];
3984
3985	union {
3986	uint32_t R;
3987	struct {
3988	uint32_t IADDR1:32;
3989	} B;
3990	} IAUR; /* Descriptor Individual Upper Address Register */
3991
3992	union {
3993	uint32_t R;
3994	struct {
3995	uint32_t IADDR2:32;
3996	} B;
3997	} IALR; /* Descriptor Individual Lower Address Register */
3998
3999	union {
4000	uint32_t R;
4001	struct {
4002	uint32_t GADDR1:32;
4003	} B;
4004	} GAUR; /* Descriptor Group Upper Address Register */
4005
4006	union {
4007	uint32_t R;
4008	struct {
4009	uint32_t GADDR2:32;
4010	} B;
4011	} GALR; /* Descriptor Group Lower Address Register */
4012
4013	uint32_t fec_reserved_galr[7];
4014
4015	union {
4016	uint32_t R;
4017	struct {
4018	uint32_t:30;
4019	uint32_t X_WMRK:2;
4020	} B;
4021	} TFWR; /* FIFO Transmit FIFO Watermark Register */
4022
4023	uint32_t fec_reserved_tfwr;
4024
4025	union {
4026	uint32_t R;
4027	struct {
4028	uint32_t:22;
4029	uint32_t R_BOUND:8;
4030	uint32_t:2;
4031	} B;
4032	} FRBR; /* FIFO Receive Bound Register */
4033
4034	union {
4035	uint32_t R;
4036	struct {
4037	uint32_t:22;
4038	uint32_t R_FSTART:8;
4039	uint32_t:2;
4040	} B;
4041	} FRSR; /* FIFO Receive Start Register */
4042
4043	uint32_t fec_reserved_frsr[11];
4044
4045	union {
4046	uint32_t R;
4047	struct {
4048	uint32_t R_DES_START:30;
4049	uint32_t:2;
4050	} B;
4051	} ERDSR; /* Receive Descriptor Ring Start Register */
4052
4053	union {
4054	uint32_t R;
4055	struct {
4056	uint32_t X_DES_START:30;
4057	uint32_t:2;
4058	} B;
4059	} ETDSR; /* Transmit Descriptor Ring Start Register */
4060
4061	union {
4062	uint32_t R;
4063	struct {
4064	uint32_t:21;
4065	uint32_t R_BUF_SIZE:7;
4066	uint32_t:4;
4067	} B;
4068	} EMRBR; /* Receive Buffer Size Register */
4069
4070	uint32_t fec_reserved_emrbr[29];
4071
4072	union {
4073	uint32_t R;
4074	} RMON_T_DROP; /* Count of frames not counted correctly */
4075
4076	union {
4077	uint32_t R;
4078	} RMON_T_PACKETS; /* RMON Tx packet count */
4079
4080	union {
4081	uint32_t R;
4082	} RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */
4083
4084	union {
4085	uint32_t R;
4086	} RMON_T_MC_PKT; /* RMON Tx Multicast Packets */
4087
4088	union {
4089	uint32_t R;
4090	} RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */
4091
4092	union {
4093	uint32_t R;
4094	} RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */
4095
4096	union {
4097	uint32_t R;
4098	} RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */
4099
4100	union {
4101	uint32_t R;
4102	} RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */
4103
4104	union {
4105	uint32_t R;
4106	} RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */
4107
4108	union {
4109	uint32_t R;
4110	} RMON_T_COL; /* RMON Tx collision count */
4111
4112	union {
4113	uint32_t R;
4114	} RMON_T_P64; /* RMON Tx 64 byte packets */
4115
4116	union {
4117	uint32_t R;
4118	} RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */
4119
4120	union {
4121	uint32_t R;
4122	} RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */
4123
4124	union {
4125	uint32_t R;
4126	} RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */
4127
4128	union {
4129	uint32_t R;
4130	} RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */
4131
4132	union {
4133	uint32_t R;
4134	} RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */
4135
4136	union {
4137	uint32_t R;
4138	} RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */
4139
4140	union {
4141	uint32_t R;
4142	} RMON_T_OCTETS; /* RMON Tx Octets */
4143
4144	union {
4145	uint32_t R;
4146	} IEEE_T_DROP; /* Count of frames not counted correctly */
4147
4148	union {
4149	uint32_t R;
4150	} IEEE_T_FRAME_OK; /* Frames Transmitted OK */
4151
4152	union {
4153	uint32_t R;
4154	} IEEE_T_1COL; /* Frames Transmitted with Single Collision */
4155
4156	union {
4157	uint32_t R;
4158	} IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */
4159
4160	union {
4161	uint32_t R;
4162	} IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */
4163
4164	union {
4165	uint32_t R;
4166	} IEEE_T_LCOL; /* Frames Transmitted with Late Collision */
4167
4168	union {
4169	uint32_t R;
4170	} IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */
4171
4172	union {
4173	uint32_t R;
4174	} IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */
4175
4176	union {
4177	uint32_t R;
4178	} IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */
4179
4180	union {
4181	uint32_t R;
4182	} IEEE_T_SQE; /* Frames Transmitted with SQE Error */
4183
4184	union {
4185	uint32_t R;
4186	} IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */
4187
4188	union {
4189	uint32_t R;
4190	} IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */
4191
4192	uint32_t fec_reserved_rmon_t_octets_ok[2];
4193
4194	union {
4195	uint32_t R;
4196	} RMON_R_DROP; /* Count of frames not counted correctly */
4197
4198	union {
4199	uint32_t R;
4200	} RMON_R_PACKETS; /* RMON Rx packet count */
4201
4202	union {
4203	uint32_t R;
4204	} RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */
4205
4206	union {
4207	uint32_t R;
4208	} RMON_R_MC_PKT; /* RMON Rx Multicast Packets */
4209
4210	union {
4211	uint32_t R;
4212	} RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */
4213
4214	union {
4215	uint32_t R;
4216	} RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */
4217
4218	union {
4219	uint32_t R;
4220	} RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */
4221
4222	union {
4223	uint32_t R;
4224	} RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */
4225
4226	union {
4227	uint32_t R;
4228	} RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */
4229
4230	uint32_t fec_reserved_rmon_r_jab;
4231
4232	union {
4233	uint32_t R;
4234	} RMON_R_P64; /* RMON Rx 64 byte packets */
4235
4236	union {
4237	uint32_t R;
4238	} RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */
4239
4240	union {
4241	uint32_t R;
4242	} RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */
4243
4244	union {
4245	uint32_t R;
4246	} RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */
4247
4248	union {
4249	uint32_t R;
4250	} RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */
4251
4252	union {
4253	uint32_t R;
4254	} RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */
4255
4256	union {
4257	uint32_t R;
4258	} RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */
4259
4260	union {
4261	uint32_t R;
4262	} RMON_R_OCTETS; /* RMON Rx Octets */
4263
4264	union {
4265	uint32_t R;
4266	} IEEE_R_DROP; /* Count of frames not counted correctly */
4267
4268	union {
4269	uint32_t R;
4270	} IEEE_R_FRAME_OK; /* Frames Received OK */
4271
4272	union {
4273	uint32_t R;
4274	} IEEE_R_CRC; /* Frames Received with CRC Error */
4275
4276	union {
4277	uint32_t R;
4278	} IEEE_R_ALIGN; /* Frames Received with Alignment Error */
4279
4280	union {
4281	uint32_t R;
4282	} IEEE_R_MACERR; /* Receive Fifo Overflow count */
4283
4284	union {
4285	uint32_t R;
4286	} IEEE_R_FDXFC; /* Flow Control Pause frames received */
4287
4288	union {
4289	uint32_t R;
4290	} IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */
4291
4292	};
4293
4294	/****************************************************************************/
4295	/* MMU */
4296	/****************************************************************************/
4297	struct MMU_tag {
4298	union {
4299	uint32_t R;
4300	struct {
4301	uint32_t : 2;
4302	uint32_t TLBSEL : 2;
4303	uint32_t : 7;
4304	uint32_t ESEL : 5;
4305	uint32_t : 11;
4306	uint32_t NV : 5;
4307	} B;
4308	} MAS0;
4309
4310	union {
4311	uint32_t R;
4312	struct {
4313	uint32_t VALID : 1;
4314	uint32_t IPROT : 1;
4315	uint32_t : 6;
4316	uint32_t TID : 8;
4317	uint32_t : 3;
4318	uint32_t TS : 1;
4319	uint32_t TSIZ : 4;
4320	uint32_t : 8;
4321	} B;
4322	} MAS1;
4323
4324	union {
4325	uint32_t R;
4326	struct {
4327	uint32_t EPN : 20;
4328	uint32_t : 7;
4329	uint32_t W : 1;
4330	uint32_t I : 1;
4331	uint32_t M : 1;
4332	uint32_t G : 1;
4333	uint32_t E : 1;
4334	} B;
4335	} MAS2;
4336
4337	union {
4338	uint32_t R;
4339	struct {
4340	uint32_t RPN : 20;
4341	uint32_t : 2;
4342	uint32_t U0 : 1;
4343	uint32_t U1 : 1;
4344	uint32_t U2 : 1;
4345	uint32_t U3 : 1;
4346	uint32_t UX : 1;
4347	uint32_t SX : 1;
4348	uint32_t UW : 1;
4349	uint32_t SW : 1;
4350	uint32_t UR : 1;
4351	uint32_t SR : 1;
4352	} B;
4353	} MAS3;
4354
4355	union {
4356	uint32_t R;
4357	struct {
4358	uint32_t : 2;
4359	uint32_t TLBSELD : 2;
4360	uint32_t : 10;
4361	uint32_t TIDSELD : 2;
4362	uint32_t : 4;
4363	uint32_t TSIZED : 4;
4364	uint32_t : 3;
4365	uint32_t WD : 1;
4366	uint32_t ID : 1;
4367	uint32_t MD : 1;
4368	uint32_t GD : 1;
4369	uint32_t ED : 1;
4370	} B;
4371	} MAS4;
4372
4373	union {
4374	uint32_t R;
4375	struct {
4376	uint32_t : 8;
4377	uint32_t SPID : 8;
4378	uint32_t : 15;
4379	uint32_t SAS : 1;
4380	} B;
4381	} MAS6;
4382	};
4383
4384	static const struct MMU_tag MMU_DEFAULT = {
4385	.MAS0 = { .R = 0x10000000 },
4386	.MAS1 = { .R = 0 },
4387	.MAS2 = { .R = 0 },
4388	.MAS3 = { .R = 0 },
4389	.MAS4 = { .R = 0 },
4390	.MAS6 = { .R = 0 }
4391	};
4392
4393	#if ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517))
4394	/* Define memories */
4395
4396	#define SRAM_START 0x40000000
4397	#define SRAM_SIZE 0x14000
4398	#define SRAM_END (SRAM_START+SRAM_SIZE-1)
4399
4400	#define FLASH_START 0x00000000
4401	#define FLASH_SIZE 0x180000
4402	#define FLASH_END (FLASH_START+FLASH_SIZE-1)
4403
4404	/* Define instances of modules */
4405	#define EDMA ((volatile struct EDMA_tag ) 0xFFF44000)
4406	#define INTC ((volatile struct INTC_tag ) 0xFFF48000)
4407
4408	#define EQADC ((volatile struct EQADC_tag ) 0xFFF80000)
4409	#define SOFTMLB ((volatile struct SOFTMLB_tag ) 0xFFF84000)
4410	#define I2C_A ((volatile struct I2C_tag ) 0xFFF88000)
4411
4412	#define DSPI_A ((volatile struct DSPI_tag ) 0xFFF90000)
4413	#define DSPI_B ((volatile struct DSPI_tag ) 0xFFF94000)
4414	#define DSPI_C ((volatile struct DSPI_tag ) 0xFFF98000)
4415	#define DSPI_D ((volatile struct DSPI_tag ) 0xFFF9C000)
4416
4417	#define ESCI_A ((volatile struct ESCI_tag ) 0xFFFA0000)
4418	#define ESCI_B ((volatile struct ESCI_tag ) 0xFFFA4000)
4419	#define ESCI_C ((volatile struct ESCI_tag ) 0xFFFA8000)
4420	#define ESCI_D ((volatile struct ESCI_tag ) 0xFFFAC000)
4421	#define ESCI_E ((volatile struct ESCI_tag ) 0xFFFB0000)
4422	#define ESCI_F ((volatile struct ESCI_tag ) 0xFFFB4000)
4423	#define ESCI_G ((volatile struct ESCI_tag ) 0xFFFB8000)
4424	#define ESCI_H ((volatile struct ESCI_tag ) 0xFFFBC000)
4425
4426	#define CAN_A ((volatile struct FLEXCAN2_tag ) 0xFFFC0000)
4427	#define CAN_B ((volatile struct FLEXCAN2_tag ) 0xFFFC4000)
4428	#define CAN_C ((volatile struct FLEXCAN2_tag ) 0xFFFC8000)
4429	#define CAN_D ((volatile struct FLEXCAN2_tag ) 0xFFFCC000)
4430	#define CAN_E ((volatile struct FLEXCAN2_tag ) 0xFFFD0000)
4431	#define CAN_F ((volatile struct FLEXCAN2_tag ) 0xFFFD4000)
4432
4433	#define EMIOS ((volatile struct EMIOS_tag ) 0xFFFE4000)
4434	#define SIU ((volatile struct SIU_tag ) 0xFFFE8000)
4435	#define CRP ((volatile struct CRP_tag ) 0xFFFEC000)
4436
4437	#define FMPLL ((volatile struct FMPLL_tag ) 0xFFFF0000)
4438	#define EBI ((volatile struct EBI_tag ) 0xFFFF4000)
4439	#define FLASH ((volatile struct FLASH_tag ) 0xFFFF8000)
4440
4441	#else /* ((MPC55XX_CHIP_DERIVATE >= 5510) && (MPC55XX_CHIP_DERIVATE <= 5517)) */
4442	/* Define memories */
4443
4444	#define SRAM_START 0x40000000
4445	#define SRAM_SIZE 0x20000
4446	#define SRAM_END (SRAM_START+SRAM_SIZE-1)
4447
4448	#define FLASH_START 0x0
4449	#define FLASH_SIZE 0x300000
4450	#define FLASH_END 0x2FFFFF
4451
4452	/* Define instances of modules */
4453	#define PBRIDGE_A ((volatile struct PBRIDGE_A_tag ) 0xC3F00000)
4454	#define FMPLL ((volatile struct FMPLL_tag ) 0xC3F80000)
4455	#define EBI ((volatile struct EBI_tag ) 0xC3F84000)
4456	#define FLASH ((volatile struct FLASH_tag ) 0xC3F88000)
4457	#define SIU ((volatile struct SIU_tag ) 0xC3F90000)
4458
4459	#define EMIOS ((volatile struct EMIOS_tag ) 0xC3FA0000)
4460	#define ETPU ((volatile struct ETPU_tag ) 0xC3FC0000)
4461	#define ETPU_DATA_RAM ((volatile uint32_t ) 0xC3FC8000)
4462	#define ETPU_DATA_RAM_EXT ((volatile uint32_t ) 0xC3FCC000)
4463	#define ETPU_DATA_RAM_END 0xC3FC8FFC
4464	#define CODE_RAM ((volatile uint32_t ) 0xC3FD0000)
4465	#define ETPU_CODE_RAM ((volatile uint32_t ) 0xC3FD0000)
4466
4467	#define PBRIDGE_B ((volatile struct PBRIDGE_B_tag ) 0xFFF00000)
4468	#define XBAR ((volatile struct XBAR_tag ) 0xFFF04000)
4469	#define ECSM ((volatile struct ECSM_tag ) 0xFFF40000)
4470	#define EDMA ((volatile struct EDMA_tag ) 0xFFF44000)
4471	#define INTC ((volatile struct INTC_tag ) 0xFFF48000)
4472
4473	#define EQADC ((volatile struct EQADC_tag ) 0xFFF80000)
4474
4475	#define DSPI_A ((volatile struct DSPI_tag ) 0xFFF90000)
4476	#define DSPI_B ((volatile struct DSPI_tag ) 0xFFF94000)
4477	#define DSPI_C ((volatile struct DSPI_tag ) 0xFFF98000)
4478	#define DSPI_D ((volatile struct DSPI_tag ) 0xFFF9C000)
4479
4480	#define ESCI_A ((volatile struct ESCI_tag ) 0xFFFB0000)
4481	#define ESCI_B ((volatile struct ESCI_tag ) 0xFFFB4000)
4482
4483	#define CAN_A ((volatile struct FLEXCAN2_tag ) 0xFFFC0000)
4484	#define CAN_B ((volatile struct FLEXCAN2_tag ) 0xFFFC4000)
4485	#define CAN_C ((volatile struct FLEXCAN2_tag ) 0xFFFC8000)
4486	#define CAN_D ((volatile struct FLEXCAN2_tag ) 0xFFFCC000)
4487
4488	#define FEC ((volatile struct FEC_tag ) 0xFFF4C000)
4489	#endif
4490
4491	#define MPC55XX_ZERO_FLAGS { .R = 0 }
4492
4493	#ifdef __cplusplus
4494	}
4495	#endif /* __cplusplus */
4496
4497	#endif /* LIBCPU_POWERPC_MPC55XX_REGS_H */
4498
4499	/*********************************************************************
4500	*
4501	* Copyright:
4502	* Freescale Semiconductor, INC. All Rights Reserved.
4503	* You are hereby granted a copyright license to use, modify, and
4504	* distribute the SOFTWARE so long as this entire notice is
4505	* retained without alteration in any modified and/or redistributed
4506	* versions, and that such modified versions are clearly identified
4507	* as such. No licenses are granted by implication, estoppel or
4508	* otherwise under any patents or trademarks of Freescale
4509	* Semiconductor, Inc. This software is provided on an "AS IS"
4510	* basis and without warranty.
4511	*
4512	* To the maximum extent permitted by applicable law, Freescale
4513	* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
4514	* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
4515	* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
4516	* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
4517	* AND ANY ACCOMPANYING WRITTEN MATERIALS.
4518	*
4519	* To the maximum extent permitted by applicable law, IN NO EVENT
4520	* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
4521	* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
4522	* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
4523	* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
4524	*
4525	* Freescale Semiconductor assumes no responsibility for the
4526	* maintenance and support of this software
4527	*
4528	********************************************************************/

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