| 1 | /** |
|---|
| 2 | * @file |
|---|
| 3 | * |
|---|
| 4 | * @ingroup mpc55xx |
|---|
| 5 | * |
|---|
| 6 | * @brief Register definitions. |
|---|
| 7 | */ |
|---|
| 8 | |
|---|
| 9 | /* |
|---|
| 10 | * Copyright (c) 2008 |
|---|
| 11 | * Embedded Brains GmbH |
|---|
| 12 | * Obere Lagerstr. 30 |
|---|
| 13 | * D-82178 Puchheim |
|---|
| 14 | * Germany |
|---|
| 15 | * rtems@embedded-brains.de |
|---|
| 16 | * |
|---|
| 17 | * The license and distribution terms for this file may be found in the file |
|---|
| 18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
|---|
| 19 | */ |
|---|
| 20 | |
|---|
| 21 | #ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H |
|---|
| 22 | #define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H |
|---|
| 23 | |
|---|
| 24 | #include <bspopts.h> |
|---|
| 25 | /* |
|---|
| 26 | * Register addresses |
|---|
| 27 | */ |
|---|
| 28 | #if ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517)) |
|---|
| 29 | |
|---|
| 30 | #define FMPLL_SYNSR 0xFFFF0004 |
|---|
| 31 | #define FMPLL_ESYNCR1 0xFFFF0008 |
|---|
| 32 | #define FMPLL_ESYNCR2 0xFFFF000C |
|---|
| 33 | #define FLASH_BIUCR 0xFFFF801C |
|---|
| 34 | #define SIU_ECCR 0xFFFE8984 |
|---|
| 35 | #define SIU_SYSCLK 0xFFFE89A0 |
|---|
| 36 | #define SIU_SRCR 0xFFFE8010 |
|---|
| 37 | |
|---|
| 38 | /* |
|---|
| 39 | * Definitions for SIU_SYSCLK |
|---|
| 40 | */ |
|---|
| 41 | #define SIU_SYSCLK_SYSCLKSEL_MASK 0xC0000000 |
|---|
| 42 | #define SIU_SYSCLK_SYSCLKSEL_IRC 0x00000000 |
|---|
| 43 | #define SIU_SYSCLK_SYSCLKSEL_XOSC 0x40000000 |
|---|
| 44 | #define SIU_SYSCLK_SYSCLKSEL_PLL 0x80000000 |
|---|
| 45 | |
|---|
| 46 | #else /* ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/ |
|---|
| 47 | |
|---|
| 48 | #define FMPLL_SYNCR 0xC3F80000 |
|---|
| 49 | #define FMPLL_SYNSR 0xC3F80004 |
|---|
| 50 | #define FLASH_BIUCR 0xC3F8801C |
|---|
| 51 | #define SIU_ECCR 0xC3F90984 |
|---|
| 52 | #define SIU_SRCR 0xC3F90010 |
|---|
| 53 | |
|---|
| 54 | #endif /*((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/ |
|---|
| 55 | /* |
|---|
| 56 | * Special purpose registers |
|---|
| 57 | */ |
|---|
| 58 | |
|---|
| 59 | #define BUCSR 1013 |
|---|
| 60 | |
|---|
| 61 | /* |
|---|
| 62 | * Branch Unit Control and Status Register (BUCSR) |
|---|
| 63 | */ |
|---|
| 64 | |
|---|
| 65 | #define BUCSR_BBFI 0x00000200 |
|---|
| 66 | #define BUCSR_BPEN 0x00000001 |
|---|
| 67 | |
|---|
| 68 | /* |
|---|
| 69 | * Definitions for FMPLL_SYNCR (FMPLL Synthesizer Control Register) |
|---|
| 70 | */ |
|---|
| 71 | |
|---|
| 72 | /* Fields used for PREDIV (Pre-Divider bits [1:3]) */ |
|---|
| 73 | #define FMPLL_SYNCR_PREDIV_0 0x00000000 |
|---|
| 74 | |
|---|
| 75 | /* Fields used for MFD (Muliplication Factor Divider bits [4:8]) */ |
|---|
| 76 | #define FMPLL_SYNCR_MFD_0 0x00000000 |
|---|
| 77 | #define FMPLL_SYNCR_MFD_2 0x01000000 |
|---|
| 78 | #define FMPLL_SYNCR_MFD_4 0x02000000 |
|---|
| 79 | #define FMPLL_SYNCR_MFD_6 0x03000000 |
|---|
| 80 | #define FMPLL_SYNCR_MFD_8 0x04000000 |
|---|
| 81 | #define FMPLL_SYNCR_MFD_10 0x05000000 |
|---|
| 82 | #define FMPLL_SYNCR_MFD_12 0x06000000 |
|---|
| 83 | |
|---|
| 84 | /* Fields used for RFD (Reduced Frequency Divider bits [10:12]) */ |
|---|
| 85 | #define FMPLL_SYNCR_RFD_0 0x00000000 |
|---|
| 86 | #define FMPLL_SYNCR_RFD_1 0x00080000 |
|---|
| 87 | #define FMPLL_SYNCR_RFD_2 0x00100000 |
|---|
| 88 | #define FMPLL_SYNCR_RFD_3 0x00180000 |
|---|
| 89 | #define FMPLL_SYNCR_RFD_4 0x00200000 |
|---|
| 90 | #define FMPLL_SYNCR_RFD_5 0x00280000 |
|---|
| 91 | #define FMPLL_SYNCR_RFD_6 0x00300000 |
|---|
| 92 | #define FMPLL_SYNCR_RFD_7 0x00380000 |
|---|
| 93 | |
|---|
| 94 | /* Fields for LOCEN (Loss-of-clock enable bit [13]) */ |
|---|
| 95 | #define FMPLL_SYNCR_LOCEN 0x00040000 |
|---|
| 96 | |
|---|
| 97 | /* Fields for LOLRE (Loss-of-lock reset enable bit [14]) */ |
|---|
| 98 | #define FMPLL_SYNCR_LOLRE 0x00020000 |
|---|
| 99 | |
|---|
| 100 | /* Fields for LOCRE (Loss-of-clock reset enable bit [15]) */ |
|---|
| 101 | #define FMPLL_SYNCR_LOCRE 0x00010000 |
|---|
| 102 | |
|---|
| 103 | /* Fields for DISCLK (Disable CLKOUT bit [16]) */ |
|---|
| 104 | #define FMPLL_SYNCR_DISCLK 0x00008000 |
|---|
| 105 | |
|---|
| 106 | /* Fields for LOLIRQ (Loss-of-lock interrupt request bit [17]) */ |
|---|
| 107 | #define FMPLL_SYNCR_LOLIRQ 0x00004000 |
|---|
| 108 | |
|---|
| 109 | /* Fields for LOCIRQ (Loss-of-clock interrupt request bit [18]) */ |
|---|
| 110 | #define FMPLL_SYNCR_LOCIRQ 0x00002000 |
|---|
| 111 | |
|---|
| 112 | /* Fields for RATE (Modulation rate bit [19]) */ |
|---|
| 113 | #define FMPLL_SYNCR_RATE_FREF 0x00001000 |
|---|
| 114 | |
|---|
| 115 | /* Fields for DEPTH (Modulation depth percentage bits [20:21]) */ |
|---|
| 116 | #define FMPLL_SYNCR_DEPTH_0 0x00000000 |
|---|
| 117 | #define FMPLL_SYNCR_DEPTH_1 0x00000400 |
|---|
| 118 | #define FMPLL_SYNCR_DEPTH_2 0x00000800 |
|---|
| 119 | |
|---|
| 120 | /* Fields for EXP (Expected difference bits [22:31]) */ |
|---|
| 121 | #define FMPLL_SYNCR_EXP_0 0x00000000 |
|---|
| 122 | |
|---|
| 123 | /* |
|---|
| 124 | * Definitions for the FMPLL_SYNSR (Synthesizer Status Register) |
|---|
| 125 | */ |
|---|
| 126 | |
|---|
| 127 | /* Fields for LOLF (Loss-of-lock flag bit [22]) */ |
|---|
| 128 | #define FMPLL_SYNSR_LOLF 0x00000200 |
|---|
| 129 | |
|---|
| 130 | /* Fields for LOCK (Lock status bit [28]) */ |
|---|
| 131 | #define FMPLL_SYNSR_LOCK 0x00000008 |
|---|
| 132 | |
|---|
| 133 | /* Fields for LOCF (Loss-of-clock flag bit [29]) */ |
|---|
| 134 | #define FMPLL_SYNSR_LOCF 0x00000004 |
|---|
| 135 | |
|---|
| 136 | /* |
|---|
| 137 | * Definitions for the SIU_SRCR (System Reset Control Register) |
|---|
| 138 | */ |
|---|
| 139 | |
|---|
| 140 | /* Fields for SSR (software system reset bit [0]) */ |
|---|
| 141 | #define SIU_SRCR_SSR 0x80000000 |
|---|
| 142 | |
|---|
| 143 | /* Fields for SER (external system reset bit [1]) */ |
|---|
| 144 | #define SIU_SRCR_SER 0x40000000 |
|---|
| 145 | |
|---|
| 146 | /* Fields for CRE (checkstop reset enable bit [16]) */ |
|---|
| 147 | #define SIU_SRCR_CRE 0x00008000 |
|---|
| 148 | |
|---|
| 149 | /* |
|---|
| 150 | * Definitions for FLASH_BIUCR (Flash BIU Control Register) |
|---|
| 151 | */ |
|---|
| 152 | |
|---|
| 153 | /* Fields for Flash Bus Interface Control */ |
|---|
| 154 | /* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */ |
|---|
| 155 | |
|---|
| 156 | /* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */ |
|---|
| 157 | #define FLASH_BUICR_EBI_PREFTCH 0x00080000 |
|---|
| 158 | |
|---|
| 159 | /* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */ |
|---|
| 160 | #define FLASH_BUICR_EDMA_PREFTCH 0x00040000 |
|---|
| 161 | |
|---|
| 162 | /* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */ |
|---|
| 163 | #define FLASH_BUICR_NEX_PREFTCH 0x00020000 |
|---|
| 164 | |
|---|
| 165 | /* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */ |
|---|
| 166 | #define FLASH_BUICR_CPU_PREFTCH 0x00010000 |
|---|
| 167 | |
|---|
| 168 | /* Fields for APC (access pipelining control bits [16:18]) */ |
|---|
| 169 | #define FLASH_BUICR_APC_1 0x00002000 |
|---|
| 170 | #define FLASH_BUICR_APC_2 0x00004000 |
|---|
| 171 | #define FLASH_BUICR_APC_3 0x00006000 |
|---|
| 172 | #define FLASH_BUICR_APC_4 0x00008000 |
|---|
| 173 | #define FLASH_BUICR_APC_5 0x0000A000 |
|---|
| 174 | #define FLASH_BUICR_APC_6 0x0000C000 |
|---|
| 175 | #define FLASH_BUICR_APC_NO 0x0000E000 |
|---|
| 176 | |
|---|
| 177 | /* Fields for WWSC (write wait state control bits [19:20]) */ |
|---|
| 178 | #define FLASH_BUICR_WWSC_1 0x00000800 |
|---|
| 179 | #define FLASH_BUICR_WWSC_2 0x00001000 |
|---|
| 180 | #define FLASH_BUICR_WWSC_3 0x00001800 |
|---|
| 181 | |
|---|
| 182 | /* Fields for RWSC (read wait state control bits [21:23]) */ |
|---|
| 183 | #define FLASH_BUICR_RWSC_0 0x00000000 |
|---|
| 184 | #define FLASH_BUICR_RWSC_1 0x00000100 |
|---|
| 185 | #define FLASH_BUICR_RWSC_2 0x00000200 |
|---|
| 186 | #define FLASH_BUICR_RWSC_3 0x00000300 |
|---|
| 187 | #define FLASH_BUICR_RWSC_4 0x00000400 |
|---|
| 188 | #define FLASH_BUICR_RWSC_5 0x00000500 |
|---|
| 189 | #define FLASH_BUICR_RWSC_6 0x00000600 |
|---|
| 190 | #define FLASH_BUICR_RWSC_7 0x00000700 |
|---|
| 191 | |
|---|
| 192 | /* Fields for DPFEN (data prefetch enable bits [24:25]) */ |
|---|
| 193 | #define FLASH_BUICR_DPFEN_0 0x00000000 |
|---|
| 194 | #define FLASH_BUICR_DPFEN_1 0x00000040 |
|---|
| 195 | #define FLASH_BUICR_DPFEN_3 0x000000C0 |
|---|
| 196 | |
|---|
| 197 | /* Fields for IPFEN (instruction prefetch enable bits [26:27]) */ |
|---|
| 198 | #define FLASH_BUICR_IPFEN_0 0x00000000 |
|---|
| 199 | #define FLASH_BUICR_IPFEN_1 0x00000010 |
|---|
| 200 | #define FLASH_BUICR_IPFEN_3 0x00000030 |
|---|
| 201 | |
|---|
| 202 | /* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */ |
|---|
| 203 | #define FLASH_BUICR_PFLIM_0 0x00000000 |
|---|
| 204 | #define FLASH_BUICR_PFLIM_1 0x00000002 |
|---|
| 205 | #define FLASH_BUICR_PFLIM_2 0x00000004 |
|---|
| 206 | #define FLASH_BUICR_PFLIM_3 0x00000006 |
|---|
| 207 | #define FLASH_BUICR_PFLIM_4 0x00000008 |
|---|
| 208 | #define FLASH_BUICR_PFLIM_5 0x0000000A |
|---|
| 209 | #define FLASH_BUICR_PFLIM_6 0x0000000C |
|---|
| 210 | |
|---|
| 211 | /* Fields for BFEN (enable line read buffer hits bit [31]) */ |
|---|
| 212 | #define FLASH_BUICR_BFEN 0x00000001 |
|---|
| 213 | |
|---|
| 214 | #endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */ |
|---|
![[RTEMS Logo]](/images/logo.png){kind=logo}
