source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h @ f3237a3c

4.115
Last change on this file since f3237a3c was f3237a3c, checked in by Sebastian Huber <sebastian.huber@…>, on 08/25/14 at 07:30:53

bsp/mpc55xx: Add defines for MPC5668
  • Property mode set to 100644
File size: 15.7 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief IRQ
7 */
8
9/*
10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_POWERPC_IRQ_H
24#define LIBBSP_POWERPC_IRQ_H
25
26#include <rtems/irq-extension.h>
27#include <rtems/irq.h>
28
29#include <bspopts.h>
30
31#ifdef __cplusplus
32extern "C" {
33#endif /* __cplusplus */
34
35/*
36 * Interrupt numbers
37 */
38
39#define MPC55XX_IRQ_INVALID 0x10000U
40#define MPC55XX_IRQ_MIN 0U
41
42/* Software interrupts */
43#define MPC55XX_IRQ_SOFTWARE_MIN 0U
44#define MPC55XX_IRQ_SOFTWARE_MAX 7U
45#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v)
46#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
47#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
48
49#if MPC55XX_CHIP_FAMILY == 551
50  #define MPC55XX_IRQ_MAX 293U
51
52  /* eDMA */
53  #define MPC55XX_IRQ_EDMA_ERROR(group) \
54    ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
55  #define MPC55XX_IRQ_EDMA(ch) \
56    ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
57
58  /* I2C */
59  #define MPC55XX_IRQ_I2C(mod) \
60    ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID)
61
62  /* SIU external interrupts */
63  #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
64  #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
65  #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
66  #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
67  #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
68
69  /* PIT */
70  #define MPC55XX_IRQ_RTI 148U
71  #define MPC55XX_IRQ_PIT(timer) (148U + (timer))
72
73  /* eTPU */
74  #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID
75
76  /* DSPI */
77  #define MPC55XX_IRQ_DSPI_BASE(mod) \
78    ((mod) == 0 ? 117U : \
79      ((mod) == 1 ? 122U : \
80        ((mod) == 2 ? 274U : \
81          ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID))))
82
83  /* eMIOS */
84  #define MPC55XX_IRQ_EMIOS(ch) \
85    ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID)
86
87  /* eQADC */
88  #define MPC55XX_IRQ_EQADC_BASE(mod) \
89    ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID)
90
91  /* eSCI */
92  #define MPC55XX_IRQ_ESCI(mod) \
93    ((mod) == 0 ? 113U : \
94      ((mod) == 1 ? 114U : \
95        ((mod) == 2 ? 115U : \
96          ((mod) == 3 ? 116U : \
97            ((mod) == 4 ? 270U : \
98              ((mod) == 5 ? 271U : \
99                ((mod) == 6 ? 272U : \
100                  ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID))))))))
101
102  /* FlexCAN */
103  #define MPC55XX_IRQ_CAN_BASE(mod) \
104    ((mod) == 0 ? 127U : \
105      ((mod) == 1 ? 157U : \
106        ((mod) == 2 ? 178U : \
107          ((mod) == 3 ? 199U : \
108            ((mod) == 4 ? 220U : \
109              ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID))))))
110
111  /* FlexRay */
112  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
113    ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
114#elif MPC55XX_CHIP_FAMILY == 564
115  #define MPC55XX_IRQ_MAX 255U
116
117  /* eDMA */
118  #define MPC55XX_IRQ_EDMA_ERROR(group) \
119    ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
120  #define MPC55XX_IRQ_EDMA(ch) \
121    ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
122
123  /* SWT */
124  #define MPC55XX_IRQ_SWT_0 28U
125  #define MPC55XX_IRQ_SWT_1 29U
126
127  /* STM */
128  #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U)
129
130  /* ECSM */
131  #define MPC55XX_IRQ_ECSM_FAS 9U
132  #define MPC55XX_IRQ_ECSM_NCE 35U
133  #define MPC55XX_IRQ_ECSM_COR 36U
134
135  /* MC */
136  #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U
137  #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U
138  #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U
139  #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U
140  #define MPC55XX_IRQ_MC_RGM_FRAE 56U
141
142  /* XOSC */
143  #define MPC55XX_IRQ_XOSC 57U
144
145  /* PIT */
146  #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
147    ((ch) == 3 ? 127U : ((ch) + 59U))
148
149  /* SIU external interrupts */
150  #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U
151  #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U
152  #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U
153  #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U
154
155  /* ADC */
156  #define MPC55XX_IRQ_ADC_BASE(mod) \
157    ((mod) == 0 ? 62U : \
158      ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID))
159
160  /* DSPI */
161  #define MPC55XX_IRQ_DSPI_BASE(mod) \
162    ((mod) == 0 ? 74U : \
163      ((mod) == 1 ? 94U : \
164        ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID)))
165
166  /* FlexCAN */
167  #define MPC55XX_IRQ_CAN_BASE(mod) \
168    ((mod) == 0 ? 65U : \
169      ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID))
170
171  /* FlexPWM */
172  #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \
173    ((mod) == 0 ? 179U : \
174      ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID))
175
176  /* FlexRay */
177  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
178    ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID)
179
180  /* LINFlexD */
181  #define MPC55XX_IRQ_LINFLEX_BASE(mod) \
182    ((mod) == 0 ? 79U : \
183      ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID))
184
185  /* eTimer */
186  #define MPC55XX_IRQ_ETIMER_BASE(mod) \
187    ((mod) == 0 ? 157U : \
188      ((mod) == 1 ? 168U : \
189        ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID)))
190
191  /* CTU */
192  #define MPC55XX_IRQ_CTU_MRS 193U
193  #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U)
194  #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U)
195  #define MPC55XX_IRQ_CTU_ADC 206U
196  #define MPC55XX_IRQ_CTU_ERR 207U
197
198  /* SEMA */
199  #define MPC55XX_IRQ_SEMA_0 247U
200  #define MPC55XX_IRQ_SEMA_1 248U
201
202  /* FCCU */
203  #define MPC55XX_IRQ_FCCU_ALRM 250U
204  #define MPC55XX_IRQ_FCCU_CFG_TO 251U
205  #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U
206  #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U
207
208  /* PMU */
209  #define MPC55XX_IRQ_PMU 254U
210
211  /* SWG */
212  #define MPC55XX_IRQ_SWG 255U
213#elif MPC55XX_CHIP_FAMILY == 566
214  #define MPC55XX_IRQ_MAX 315U
215
216  /* eDMA */
217  #define MPC55XX_IRQ_EDMA_ERROR(group) \
218    ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
219  #define MPC55XX_IRQ_EDMA(ch) \
220    ((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
221
222  /* PIT */
223  #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
224    ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID)
225
226  /* SIU external interrupts */
227  #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
228  #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
229  #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
230  #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
231
232  /* eMIOS */
233  #define MPC55XX_IRQ_EMIOS(ch) \
234    ((unsigned) (ch) < 24U ? 58U + (ch) : \
235      ((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID))
236
237  /* eSCI */
238  #define MPC55XX_IRQ_ESCI(mod) \
239    ((unsigned) (mod) < 4U ? 113U + (mod) : \
240      ((unsigned) (mod) < 8U ? 270U + (mod) : \
241        ((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID)))
242#else
243  #if MPC55XX_CHIP_FAMILY == 555
244    #define MPC55XX_IRQ_MAX 307U
245  #elif MPC55XX_CHIP_FAMILY == 556
246    #define MPC55XX_IRQ_MAX 360U
247  #elif MPC55XX_CHIP_FAMILY == 567
248    #define MPC55XX_IRQ_MAX 479U
249  #else
250    #error "unsupported chip type"
251  #endif
252
253  /* eDMA */
254  #define MPC55XX_IRQ_EDMA_ERROR(group) \
255    ((group) == 0 ? 10U : \
256      ((group) == 1 ? 210U : \
257        ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID)))
258  #define MPC55XX_IRQ_EDMA(ch) \
259    ((unsigned) (ch) < 32U ? 11U + (ch) : \
260      ((unsigned) (ch) < 64U ? 179U + (ch) : \
261        ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID)))
262
263  /* I2C */
264  #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID
265
266  /* SIU external interrupts */
267  #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
268  #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
269  #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
270  #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
271  #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
272
273  /* PIT */
274  #define MPC55XX_IRQ_RTI 305U
275  #define MPC55XX_IRQ_PIT(ch) (301U + (ch))
276
277  /* eTPU */
278  #define MPC55XX_IRQ_ETPU_BASE(mod) \
279    ((mod) == 0 ? 67U : \
280      ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID))
281
282  /* DSPI */
283  #define MPC55XX_IRQ_DSPI_BASE(mod) \
284    ((mod) == 0 ? 275U : \
285      ((mod) == 1 ? 131U : \
286        ((mod) == 2 ? 136U : \
287          ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID))))
288
289  /* eMIOS */
290  #define MPC55XX_IRQ_EMIOS(ch) \
291    ((unsigned) (ch) < 16U ? 51U + (ch) : \
292      ((unsigned) (ch) < 24U ? 186U + (ch) : \
293        ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID)))
294
295  /* eQADC */
296  #define MPC55XX_IRQ_EQADC_BASE(mod) \
297    ((mod) == 0 ? 100U : \
298      ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID))
299
300  /* eSCI */
301  #define MPC55XX_IRQ_ESCI(mod) \
302    ((mod) == 0 ? 146U : \
303      ((mod) == 1 ? 149U : \
304        ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID)))
305
306  /* FlexCAN */
307  #define MPC55XX_IRQ_CAN_BASE(mod) \
308    ((mod) == 0 ? 152U : \
309      ((mod) == 1 ? 280U : \
310        ((mod) == 2 ? 173U : \
311          ((mod) == 3 ? 308U : \
312            ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID)))))
313
314  /* FlexRay */
315  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
316    ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID)
317#endif
318
319#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
320
321/* ADC */
322#define MPC55XX_IRQ_ADC_EOC(mod) \
323  (MPC55XX_IRQ_ADC_BASE(mod) + 0U)
324#define MPC55XX_IRQ_ADC_ER(mod) \
325  (MPC55XX_IRQ_ADC_BASE(mod) + 1U)
326#define MPC55XX_IRQ_ADC_WD(mod) \
327  (MPC55XX_IRQ_ADC_BASE(mod) + 2U)
328
329/* eTimer */
330#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \
331  (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch))
332#define MPC55XX_IRQ_ETIMER_WTIF(mod) \
333  (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U)
334#define MPC55XX_IRQ_ETIMER_RCF(mod) \
335  (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U)
336
337/* eTPU */
338#define MPC55XX_IRQ_ETPU(mod) \
339  (MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
340#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \
341  (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch))
342
343/* DSPI */
344#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U)
345#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U)
346#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U)
347#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U)
348#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U)
349
350/* eQADC */
351#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \
352  (MPC55XX_IRQ_EQADC_BASE(mod) + 0U)
353#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \
354  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U)
355#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \
356  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U)
357#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \
358  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U)
359#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \
360  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U)
361#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \
362  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U)
363
364/* FlexCAN */
365#if MPC55XX_CHIP_FAMILY == 564
366  #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
367  #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
368  #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
369  #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
370  #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
371  #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
372  #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
373#else
374  #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
375  #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
376  #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
377  #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
378  #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
379  #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
380  #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
381  #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
382  #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
383  #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
384  #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
385  #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
386  #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
387  #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
388  #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
389  #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
390  #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
391  #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
392  #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
393  #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
394#endif
395
396/* FlexPWM */
397#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U)
398#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U)
399#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U)
400#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U)
401#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U)
402
403/* FlexRay */
404#if MPC55XX_CHIP_FAMILY == 564
405  #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
406  #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
407  #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
408  #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
409  #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
410  #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
411  #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
412  #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
413  #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U)
414  #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U)
415#else
416  #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
417  #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
418  #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
419  #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
420  #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
421  #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
422  #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
423  #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
424#endif
425
426/* LINFlexD */
427#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U)
428#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U)
429#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U)
430
431/* Checks */
432#define MPC55XX_IRQ_IS_VALID(v) \
433  ((v) >= MPC55XX_IRQ_MIN && \
434   (v) <= MPC55XX_IRQ_MAX)
435#define MPC55XX_IRQ_IS_SOFTWARE(v) \
436  ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \
437   (v) <= MPC55XX_IRQ_SOFTWARE_MAX)
438
439/*
440 * Interrupt controller
441 */
442
443#define MPC55XX_INTC_MIN_PRIORITY 1U
444#define MPC55XX_INTC_MAX_PRIORITY 15U
445#define MPC55XX_INTC_DISABLED_PRIORITY 0U
446#define MPC55XX_INTC_INVALID_PRIORITY (MPC55XX_INTC_MAX_PRIORITY + 1)
447#define MPC55XX_INTC_DEFAULT_PRIORITY (MPC55XX_INTC_MIN_PRIORITY + 1)
448#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \
449  ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY)
450
451rtems_status_code mpc55xx_interrupt_handler_install(
452  rtems_vector_number vector,
453  const char *info,
454  rtems_option options,
455  unsigned priority,
456  rtems_interrupt_handler handler,
457  void *arg
458);
459
460rtems_status_code mpc55xx_intc_get_priority(
461  rtems_vector_number vector,
462  unsigned *priority
463);
464
465rtems_status_code mpc55xx_intc_set_priority(
466  rtems_vector_number vector,
467  unsigned priority
468);
469
470rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector);
471
472rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector);
473
474/**
475 * @addtogroup bsp_interrupt
476 *
477 * @{
478 */
479
480#define BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN
481
482#define BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX
483
484#ifdef BSP_INTERRUPT_HANDLER_TABLE_SIZE
485  #define BSP_INTERRUPT_USE_INDEX_TABLE
486  #define BSP_INTERRUPT_NO_HEAP_USAGE
487#endif
488
489/** @} */
490
491/* Legacy API */
492#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch)
493#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch)
494
495#ifdef __cplusplus
496};
497#endif /* __cplusplus */
498
499#endif /* LIBBSP_POWERPC_IRQ_H */
Note: See TracBrowser for help on using the repository browser.