source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

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1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief IRQ
7 */
8
9/*
10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_POWERPC_IRQ_H
24#define LIBBSP_POWERPC_IRQ_H
25
26#include <rtems/irq-extension.h>
27#include <rtems/irq.h>
28
29#include <bspopts.h>
30
31#ifdef __cplusplus
32extern "C" {
33#endif /* __cplusplus */
34
35/*
36 * Interrupt numbers
37 */
38
39#define MPC55XX_IRQ_INVALID 0x10000U
40#define MPC55XX_IRQ_MIN 0U
41
42/* Software interrupts */
43#define MPC55XX_IRQ_SOFTWARE_MIN 0U
44#define MPC55XX_IRQ_SOFTWARE_MAX 7U
45#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v)
46#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
47#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
48
49#if MPC55XX_CHIP_FAMILY == 551
50  #define MPC55XX_IRQ_MAX 293U
51
52  /* eDMA */
53  #define MPC55XX_IRQ_EDMA_ERROR(group) \
54    ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
55  #define MPC55XX_IRQ_EDMA(ch) \
56    ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
57
58  /* I2C */
59  #define MPC55XX_IRQ_I2C(mod) \
60    ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID)
61
62  /* SIU external interrupts */
63  #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
64  #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
65  #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
66  #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
67  #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
68
69  /* PIT */
70  #define MPC55XX_IRQ_RTI 148U
71  #define MPC55XX_IRQ_PIT(timer) (148U + (timer))
72
73  /* eTPU */
74  #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID
75
76  /* DSPI */
77  #define MPC55XX_IRQ_DSPI_BASE(mod) \
78    ((mod) == 0 ? 117U : \
79      ((mod) == 1 ? 122U : \
80        ((mod) == 2 ? 274U : \
81          ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID))))
82
83  /* eMIOS */
84  #define MPC55XX_IRQ_EMIOS(ch) \
85    ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID)
86
87  /* eQADC */
88  #define MPC55XX_IRQ_EQADC_BASE(mod) \
89    ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID)
90
91  /* eSCI */
92  #define MPC55XX_IRQ_ESCI(mod) \
93    ((mod) == 0 ? 113U : \
94      ((mod) == 1 ? 114U : \
95        ((mod) == 2 ? 115U : \
96          ((mod) == 3 ? 116U : \
97            ((mod) == 4 ? 270U : \
98              ((mod) == 5 ? 271U : \
99                ((mod) == 6 ? 272U : \
100                  ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID))))))))
101
102  /* FlexCAN */
103  #define MPC55XX_IRQ_CAN_BASE(mod) \
104    ((mod) == 0 ? 127U : \
105      ((mod) == 1 ? 157U : \
106        ((mod) == 2 ? 178U : \
107          ((mod) == 3 ? 199U : \
108            ((mod) == 4 ? 220U : \
109              ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID))))))
110
111  /* FlexRay */
112  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
113    ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
114#elif MPC55XX_CHIP_FAMILY == 564
115  #define MPC55XX_IRQ_MAX 255U
116
117  /* eDMA */
118  #define MPC55XX_IRQ_EDMA_ERROR(group) \
119    ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
120  #define MPC55XX_IRQ_EDMA(ch) \
121    ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
122
123  /* SWT */
124  #define MPC55XX_IRQ_SWT_0 28U
125  #define MPC55XX_IRQ_SWT_1 29U
126
127  /* STM */
128  #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U)
129
130  /* ECSM */
131  #define MPC55XX_IRQ_ECSM_FAS 9U
132  #define MPC55XX_IRQ_ECSM_NCE 35U
133  #define MPC55XX_IRQ_ECSM_COR 36U
134
135  /* MC */
136  #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U
137  #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U
138  #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U
139  #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U
140  #define MPC55XX_IRQ_MC_RGM_FRAE 56U
141
142  /* XOSC */
143  #define MPC55XX_IRQ_XOSC 57U
144
145  /* PIT */
146  #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
147    ((ch) == 3 ? 127U : ((ch) + 59U))
148
149  /* SIU external interrupts */
150  #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U
151  #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U
152  #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U
153  #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U
154
155  /* ADC */
156  #define MPC55XX_IRQ_ADC_BASE(mod) \
157    ((mod) == 0 ? 62U : \
158      ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID))
159
160  /* DSPI */
161  #define MPC55XX_IRQ_DSPI_BASE(mod) \
162    ((mod) == 0 ? 74U : \
163      ((mod) == 1 ? 94U : \
164        ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID)))
165
166  /* FlexCAN */
167  #define MPC55XX_IRQ_CAN_BASE(mod) \
168    ((mod) == 0 ? 65U : \
169      ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID))
170
171  /* FlexPWM */
172  #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \
173    ((mod) == 0 ? 179U : \
174      ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID))
175
176  /* FlexRay */
177  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
178    ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID)
179
180  /* LINFlexD */
181  #define MPC55XX_IRQ_LINFLEX_BASE(mod) \
182    ((mod) == 0 ? 79U : \
183      ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID))
184
185  /* eTimer */
186  #define MPC55XX_IRQ_ETIMER_BASE(mod) \
187    ((mod) == 0 ? 157U : \
188      ((mod) == 1 ? 168U : \
189        ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID)))
190
191  /* CTU */
192  #define MPC55XX_IRQ_CTU_MRS 193U
193  #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U)
194  #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U)
195  #define MPC55XX_IRQ_CTU_ADC 206U
196  #define MPC55XX_IRQ_CTU_ERR 207U
197
198  /* SEMA */
199  #define MPC55XX_IRQ_SEMA_0 247U
200  #define MPC55XX_IRQ_SEMA_1 248U
201
202  /* FCCU */
203  #define MPC55XX_IRQ_FCCU_ALRM 250U
204  #define MPC55XX_IRQ_FCCU_CFG_TO 251U
205  #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U
206  #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U
207
208  /* PMU */
209  #define MPC55XX_IRQ_PMU 254U
210
211  /* SWG */
212  #define MPC55XX_IRQ_SWG 255U
213#elif MPC55XX_CHIP_FAMILY == 566
214  #define MPC55XX_IRQ_MAX 315U
215
216  /* eDMA */
217  #define MPC55XX_IRQ_EDMA_ERROR(group) \
218    ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
219  #define MPC55XX_IRQ_EDMA(ch) \
220    ((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
221
222  /* PIT */
223  #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
224    ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID)
225
226  /* eMIOS */
227  #define MPC55XX_IRQ_EMIOS(ch) \
228    ((unsigned) (ch) < 24U ? 58U + (ch) : \
229      ((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID))
230
231  /* eSCI */
232  #define MPC55XX_IRQ_ESCI(mod) \
233    ((unsigned) (mod) < 4U ? 113U + (mod) : \
234      ((unsigned) (mod) < 8U ? 270U + (mod) : \
235        ((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID)))
236#else
237  #if MPC55XX_CHIP_FAMILY == 555
238    #define MPC55XX_IRQ_MAX 307U
239  #elif MPC55XX_CHIP_FAMILY == 556
240    #define MPC55XX_IRQ_MAX 360U
241  #elif MPC55XX_CHIP_FAMILY == 567
242    #define MPC55XX_IRQ_MAX 479U
243  #else
244    #error "unsupported chip type"
245  #endif
246
247  /* eDMA */
248  #define MPC55XX_IRQ_EDMA_ERROR(group) \
249    ((group) == 0 ? 10U : \
250      ((group) == 1 ? 210U : \
251        ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID)))
252  #define MPC55XX_IRQ_EDMA(ch) \
253    ((unsigned) (ch) < 32U ? 11U + (ch) : \
254      ((unsigned) (ch) < 64U ? 179U + (ch) : \
255        ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID)))
256
257  /* I2C */
258  #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID
259
260  /* SIU external interrupts */
261  #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
262  #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
263  #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
264  #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
265  #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
266
267  /* PIT */
268  #define MPC55XX_IRQ_RTI 305U
269  #define MPC55XX_IRQ_PIT(ch) (301U + (ch))
270
271  /* eTPU */
272  #define MPC55XX_IRQ_ETPU_BASE(mod) \
273    ((mod) == 0 ? 67U : \
274      ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID))
275
276  /* DSPI */
277  #define MPC55XX_IRQ_DSPI_BASE(mod) \
278    ((mod) == 0 ? 275U : \
279      ((mod) == 1 ? 131U : \
280        ((mod) == 2 ? 136U : \
281          ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID))))
282
283  /* eMIOS */
284  #define MPC55XX_IRQ_EMIOS(ch) \
285    ((unsigned) (ch) < 16U ? 51U + (ch) : \
286      ((unsigned) (ch) < 24U ? 186U + (ch) : \
287        ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID)))
288
289  /* eQADC */
290  #define MPC55XX_IRQ_EQADC_BASE(mod) \
291    ((mod) == 0 ? 100U : \
292      ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID))
293
294  /* eSCI */
295  #define MPC55XX_IRQ_ESCI(mod) \
296    ((mod) == 0 ? 146U : \
297      ((mod) == 1 ? 149U : \
298        ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID)))
299
300  /* FlexCAN */
301  #define MPC55XX_IRQ_CAN_BASE(mod) \
302    ((mod) == 0 ? 152U : \
303      ((mod) == 1 ? 280U : \
304        ((mod) == 2 ? 173U : \
305          ((mod) == 3 ? 308U : \
306            ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID)))))
307
308  /* FlexRay */
309  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
310    ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID)
311#endif
312
313#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
314
315/* ADC */
316#define MPC55XX_IRQ_ADC_EOC(mod) \
317  (MPC55XX_IRQ_ADC_BASE(mod) + 0U)
318#define MPC55XX_IRQ_ADC_ER(mod) \
319  (MPC55XX_IRQ_ADC_BASE(mod) + 1U)
320#define MPC55XX_IRQ_ADC_WD(mod) \
321  (MPC55XX_IRQ_ADC_BASE(mod) + 2U)
322
323/* eTimer */
324#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \
325  (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch))
326#define MPC55XX_IRQ_ETIMER_WTIF(mod) \
327  (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U)
328#define MPC55XX_IRQ_ETIMER_RCF(mod) \
329  (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U)
330
331/* eTPU */
332#define MPC55XX_IRQ_ETPU(mod) \
333  (MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
334#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \
335  (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch))
336
337/* DSPI */
338#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U)
339#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U)
340#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U)
341#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U)
342#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U)
343
344/* eQADC */
345#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \
346  (MPC55XX_IRQ_EQADC_BASE(mod) + 0U)
347#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \
348  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U)
349#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \
350  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U)
351#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \
352  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U)
353#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \
354  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U)
355#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \
356  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U)
357
358/* FlexCAN */
359#if MPC55XX_CHIP_FAMILY == 564
360  #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
361  #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
362  #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
363  #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
364  #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
365  #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
366  #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
367#else
368  #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
369  #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
370  #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
371  #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
372  #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
373  #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
374  #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
375  #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
376  #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
377  #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
378  #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
379  #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
380  #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
381  #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
382  #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
383  #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
384  #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
385  #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
386  #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
387  #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
388#endif
389
390/* FlexPWM */
391#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U)
392#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U)
393#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U)
394#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U)
395#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U)
396
397/* FlexRay */
398#if MPC55XX_CHIP_FAMILY == 564
399  #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
400  #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
401  #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
402  #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
403  #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
404  #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
405  #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
406  #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
407  #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U)
408  #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U)
409#else
410  #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
411  #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
412  #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
413  #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
414  #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
415  #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
416  #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
417  #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
418#endif
419
420/* LINFlexD */
421#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U)
422#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U)
423#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U)
424
425/* Checks */
426#define MPC55XX_IRQ_IS_VALID(v) \
427  ((v) >= MPC55XX_IRQ_MIN && \
428   (v) <= MPC55XX_IRQ_MAX)
429#define MPC55XX_IRQ_IS_SOFTWARE(v) \
430  ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \
431   (v) <= MPC55XX_IRQ_SOFTWARE_MAX)
432
433/*
434 * Interrupt controller
435 */
436
437#define MPC55XX_INTC_MIN_PRIORITY 1U
438#define MPC55XX_INTC_MAX_PRIORITY 15U
439#define MPC55XX_INTC_DISABLED_PRIORITY 0U
440#define MPC55XX_INTC_INVALID_PRIORITY (MPC55XX_INTC_MAX_PRIORITY + 1)
441#define MPC55XX_INTC_DEFAULT_PRIORITY (MPC55XX_INTC_MIN_PRIORITY + 1)
442#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \
443  ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY)
444
445rtems_status_code mpc55xx_interrupt_handler_install(
446  rtems_vector_number vector,
447  const char *info,
448  rtems_option options,
449  unsigned priority,
450  rtems_interrupt_handler handler,
451  void *arg
452);
453
454rtems_status_code mpc55xx_intc_get_priority(
455  rtems_vector_number vector,
456  unsigned *priority
457);
458
459rtems_status_code mpc55xx_intc_set_priority(
460  rtems_vector_number vector,
461  unsigned priority
462);
463
464rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector);
465
466rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector);
467
468/**
469 * @addtogroup bsp_interrupt
470 *
471 * @{
472 */
473
474#define BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN
475
476#define BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX
477
478#ifdef BSP_INTERRUPT_HANDLER_TABLE_SIZE
479  #define BSP_INTERRUPT_USE_INDEX_TABLE
480  #define BSP_INTERRUPT_NO_HEAP_USAGE
481#endif
482
483/** @} */
484
485/* Legacy API */
486#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch)
487#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch)
488
489#ifdef __cplusplus
490};
491#endif /* __cplusplus */
492
493#endif /* LIBBSP_POWERPC_IRQ_H */
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