source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h @ 97fa2f1b

4.115
Last change on this file since 97fa2f1b was 97fa2f1b, checked in by Sebastian Huber <sebastian.huber@…>, on 08/31/11 at 15:50:30

2011-08-31 Sebastian Huber <sebastian.huber@…>

  • mpc55xx/include/fsl-mpc551x.h, mpc55xx/include/fsl-mpc555x.h, mpc55xx/include/fsl-mpc556x.h, mpc55xx/include/fsl-mpc567x.h, mpc55xx/include/regs-edma.h, mpc55xx/include/regs-mmu.h: New files.
  • Makefile.am, M preinstall.am: Reflect changes above.
  • mpc55xx/dspi/dspi.c: Update due to API changes.
  • mpc55xx/include/edma.h, mpc55xx/edma/edma.c: Rework to support multiple eDMA modules. Removed complex error interrupt handling.
  • mpc55xx/include/esci.h, mpc55xx/esci/esci.c: Support interrupt mode and printk(). Use configure options.
  • mpc55xx/include/irq.h: More defines. API changes.
  • mpc55xx/include/mpc55xx.h: API changes.
  • mpc55xx/include/reg-defs.h: Added register defines.
  • mpc55xx/include/regs.h: Use new register header files.
  • mpc55xx/include/siu.h: Fixed includes.
  • mpc55xx/misc/fmpll.S, mpc55xx/misc/copy.S, mpc55xx/misc/flash.S: Changed sections. API changes. Support MPC5674F.
  • Property mode set to 100644
File size: 9.7 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief IRQ
7 */
8
9/*
10 * Copyright (c) 2008, 2010
11 * Embedded Brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * rtems@embedded-brains.de
16 *
17 * The license and distribution terms for this file may be found in the file
18 * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19 */
20
21#ifndef LIBBSP_POWERPC_IRQ_H
22#define LIBBSP_POWERPC_IRQ_H
23
24#include <rtems/irq-extension.h>
25#include <rtems/irq.h>
26
27#include <bspopts.h>
28
29#ifdef __cplusplus
30extern "C" {
31#endif /* __cplusplus */
32
33/*
34 * Interrupt numbers
35 */
36
37#define MPC55XX_IRQ_INVALID 0x10000U
38#define MPC55XX_IRQ_MIN 0U
39
40/* Software interrupts */
41#define MPC55XX_IRQ_SOFTWARE_MIN 0U
42#define MPC55XX_IRQ_SOFTWARE_MAX 7U
43#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v)
44#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
45#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
46
47#if MPC55XX_CHIP_TYPE / 10 == 551
48  #define MPC55XX_IRQ_MAX 293U
49
50  /* eDMA */
51  #define MPC55XX_IRQ_EDMA_ERROR(group) \
52    ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
53  #define MPC55XX_IRQ_EDMA(ch) \
54    ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
55
56  /* I2C */
57  #define MPC55XX_IRQ_I2C(mod) \
58    ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID)
59
60  /* SIU external interrupts */
61  #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
62  #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
63  #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
64  #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
65  #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
66
67  /* PIT */
68  #define MPC55XX_IRQ_RTI 148U
69  #define MPC55XX_IRQ_PIT(timer) (148U + (timer))
70
71  /* eTPU */
72  #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID
73
74  /* DSPI */
75  #define MPC55XX_IRQ_DSPI_BASE(mod) \
76    ((mod) == 0 ? 117U : \
77      ((mod) == 1 ? 122U : \
78        ((mod) == 2 ? 274U : \
79          ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID))))
80
81  /* eMIOS */
82  #define MPC55XX_IRQ_EMIOS(ch) \
83    ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID)
84
85  /* eQADC */
86  #define MPC55XX_IRQ_EQADC_BASE(mod) \
87    ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID)
88
89  /* eSCI */
90  #define MPC55XX_IRQ_ESCI_BASE(mod) \
91    ((mod) == 0 ? 113U : \
92      ((mod) == 1 ? 114U : \
93        ((mod) == 2 ? 115U : \
94          ((mod) == 3 ? 116U : \
95            ((mod) == 4 ? 270U : \
96              ((mod) == 5 ? 271U : \
97                ((mod) == 6 ? 272U : \
98                  ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID))))))))
99
100  /* FlexCAN */
101  #define MPC55XX_IRQ_CAN_BASE(mod) \
102    ((mod) == 0 ? 127U : \
103      ((mod) == 1 ? 157U : \
104        ((mod) == 2 ? 178U : \
105          ((mod) == 3 ? 199U : \
106            ((mod) == 4 ? 220U : \
107              ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID))))))
108
109  /* FlexRay */
110  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
111    ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
112#else
113  #if MPC55XX_CHIP_TYPE / 10 == 555
114    #define MPC55XX_IRQ_MAX 307U
115  #elif MPC55XX_CHIP_TYPE / 10 == 556
116    #define MPC55XX_IRQ_MAX 360U
117  #elif MPC55XX_CHIP_TYPE / 10 == 567
118    #define MPC55XX_IRQ_MAX 479U
119  #else
120    #error "unsupported chip type"
121  #endif
122
123  /* eDMA */
124  #define MPC55XX_IRQ_EDMA_ERROR(group) \
125    ((group) == 0 ? 10U : \
126      ((group) == 1 ? 210U : \
127        ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID)))
128  #define MPC55XX_IRQ_EDMA(ch) \
129    ((unsigned) (ch) < 32U ? 11U + (ch) : \
130      ((unsigned) (ch) < 64U ? 179U + (ch) : \
131        ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID)))
132
133  /* I2C */
134  #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID
135
136  /* SIU external interrupts */
137  #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
138  #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
139  #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
140  #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
141  #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
142
143  /* PIT */
144  #define MPC55XX_IRQ_RTI 305U
145  #define MPC55XX_IRQ_PIT(ch) (301U + (ch))
146
147  /* eTPU */
148  #define MPC55XX_IRQ_ETPU_BASE(mod) \
149    ((mod) == 0 ? 67U : \
150      ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID))
151
152  /* DSPI */
153  #define MPC55XX_IRQ_DSPI_BASE(mod) \
154    ((mod) == 0 ? 275U : \
155      ((mod) == 1 ? 131U : \
156        ((mod) == 2 ? 136U : \
157          ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID))))
158
159  /* eMIOS */
160  #define MPC55XX_IRQ_EMIOS(ch) \
161    ((unsigned) (ch) < 16U ? 51U + (ch) : \
162      ((unsigned) (ch) < 24U ? 186U + (ch) : \
163        ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID)))
164
165  /* eQADC */
166  #define MPC55XX_IRQ_EQADC_BASE(mod) \
167    ((mod) == 0 ? 100U : \
168      ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID))
169
170  /* eSCI */
171  #define MPC55XX_IRQ_ESCI_BASE(mod) \
172    ((mod) == 0 ? 146U : \
173      ((mod) == 1 ? 149U : \
174        ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID)))
175
176  /* FlexCAN */
177  #define MPC55XX_IRQ_CAN_BASE(mod) \
178    ((mod) == 0 ? 152U : \
179      ((mod) == 1 ? 280U : \
180        ((mod) == 2 ? 173U : \
181          ((mod) == 3 ? 308U : \
182            ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID)))))
183
184  /* FlexRay */
185  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
186    ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID)
187#endif
188
189#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
190
191/* eTPU */
192#define MPC55XX_IRQ_ETPU(mod) \
193  (MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
194#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \
195  (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch))
196
197/* DSPI */
198#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U)
199#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U)
200#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U)
201#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U)
202#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U)
203
204/* eQADC */
205#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \
206  (MPC55XX_IRQ_EQADC_BASE(mod) + 0U)
207#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \
208  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U)
209#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \
210  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U)
211#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \
212  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U)
213#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \
214  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U)
215#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \
216  (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U)
217
218/* eSCI */
219#define MPC55XX_IRQ_ESCI(mod) (MPC55XX_IRQ_ESCI_BASE(mod) + 0U)
220
221/* FlexCAN */
222#define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN(mod) + 0U)
223#define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN(mod) + 1U)
224#define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN(mod) + 3U)
225#define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN(mod) + 4U)
226#define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN(mod) + 5U)
227#define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN(mod) + 6U)
228#define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN(mod) + 7U)
229#define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN(mod) + 8U)
230#define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN(mod) + 9U)
231#define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN(mod) + 10U)
232#define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN(mod) + 12U)
233#define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN(mod) + 12U)
234#define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN(mod) + 13U)
235#define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN(mod) + 14U)
236#define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN(mod) + 15U)
237#define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN(mod) + 16U)
238#define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN(mod) + 17U)
239#define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN(mod) + 18U)
240#define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN(mod) + 19U)
241#define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN(mod) + 20U)
242
243/* FlexRay */
244#define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
245#define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
246#define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
247#define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
248#define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
249#define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
250#define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
251#define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
252
253/* Checks */
254#define MPC55XX_IRQ_IS_VALID(v) \
255  ((v) >= MPC55XX_IRQ_MIN && \
256   (v) <= MPC55XX_IRQ_MAX)
257#define MPC55XX_IRQ_IS_SOFTWARE(v) \
258  ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \
259   (v) <= MPC55XX_IRQ_SOFTWARE_MAX)
260
261/*
262 * Interrupt controller
263 */
264
265#define MPC55XX_INTC_MIN_PRIORITY 1U
266#define MPC55XX_INTC_MAX_PRIORITY 15U
267#define MPC55XX_INTC_DISABLED_PRIORITY 0U
268#define MPC55XX_INTC_INVALID_PRIORITY (MPC55XX_INTC_MAX_PRIORITY + 1)
269#define MPC55XX_INTC_DEFAULT_PRIORITY (MPC55XX_INTC_MIN_PRIORITY + 1)
270#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \
271  ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY)
272
273rtems_status_code mpc55xx_interrupt_handler_install(
274  rtems_vector_number vector,
275  const char *info,
276  rtems_option options,
277  unsigned priority,
278  rtems_interrupt_handler handler,
279  void *arg
280);
281
282rtems_status_code mpc55xx_intc_get_priority(
283  rtems_vector_number vector,
284  unsigned *priority
285);
286
287rtems_status_code mpc55xx_intc_set_priority(
288  rtems_vector_number vector,
289  unsigned priority
290);
291
292rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector);
293
294rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector);
295
296/**
297 * @addtogroup bsp_interrupt
298 *
299 * @{
300 */
301
302#define BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN
303
304#define BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX
305
306#define BSP_INTERRUPT_USE_INDEX_TABLE
307
308#define BSP_INTERRUPT_NO_HEAP_USAGE
309
310#ifdef BSP_INTERRUPT_USE_INDEX_TABLE
311  #define BSP_INTERRUPT_HANDLER_TABLE_SIZE 63
312  typedef uint8_t bsp_interrupt_handler_index_type;
313#endif
314
315/** @} */
316
317/* Legacy API */
318#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch)
319#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch)
320
321#ifdef __cplusplus
322};
323#endif /* __cplusplus */
324
325#endif /* LIBBSP_POWERPC_IRQ_H */
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