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source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc567x.h @ e2d3e37

4.115

Last change on this file since e2d3e37 was e2d3e37, checked in by Sebastian Huber <sebastian.huber@…>, on 10/10/11 at 08:22:27

2011-10-10 Sebastian Huber <sebastian.huber@…>

PR 1928/bsps:

mpc55xx/include/fsl-mpc567x.h: Revert previous change.
mpc55xx/misc/flash_support.c: Enable this file only for MPC55XX.

Property mode set to 100644

File size: 244.0 KB

Line
1	/*
2	* Modifications of the original file provided by Freescale are:
3	*
4	* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
5	*
6	* embedded brains GmbH
7	* Obere Lagerstr. 30
8	* 82178 Puchheim
9	* Germany
10	* <info@embedded-brains.de>
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	*
21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32	*/
33
34	/**************************************************************************/
35	/* FILE NAME: mpc5674f.h COPYRIGHT (c) Freescale 2009 */
36	/* VERSION: 1.04 All Rights Reserved */
37	/* */
38	/* DESCRIPTION: */
39	/* This file contains all of the register and bit field definitions for */
40	/* MPC5674F. */
41	/========================================================================/
42	/* UPDATE HISTORY */
43	/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
44	/* --- ----------- --------- --------------------- */
45	/* NOTE: Branch pulled at version 0.87 for mpc5674_c.h version 1.00 */
46	/* 1.00 B. Terry Corrected DECFILT addresses and added */
47	/* 4 additional filters for Rev. 2 */
48	/* 1.01 B. Terry 16/Nov/09 Corrected bit definitions in SIUDIV */
49	/* register. */
50	/* 1.02 B. Terry 19/Nov/09 Added ISEL8, ISEL9, ISEL10, and ISEL11 */
51	/* regs to SIU tag. (Mamba 2 features) */
52	/* 1.03 B. Terry 19/Nov/09 Renamed ISEL10 and ISEL11 to DECFIL1 */
53	/* and DECFIL2 to match RM. */
54	/* 1.04 B. Terry 22/Jan/10 Updated bitfields of MPU RGDx Word2 */
55	/* register to reflect Mamba 2. Added */
56	/* MXCR and MXSR registers to DecFilt. */
57	/* Removed pre-release rev history. */
58	/**************************************************************************/
59
60	#ifndef _MPC5674F_H_
61	#define _MPC5674F_H_
62
63	#include <stdint.h>
64
65	#include <mpc55xx/regs-edma.h>
66
67	#ifdef __cplusplus
68	extern "C" {
69	#endif
70
71	#ifdef __MWERKS__
72	#pragma push
73	#pragma ANSI_strict off
74	#endif
75
76	/****************************************************************************/
77	/* MODULE : PBRIDGE_A Peripheral Bridge */
78	/****************************************************************************/
79
80	struct PBRIDGE_A_tag {
81
82	union { /* Master Privilege Control Register 0*/
83	uint32_t R;
84	struct {
85	uint32_t MBW0:1; /* z7 Core */
86	uint32_t MTR0:1;
87	uint32_t MTW0:1;
88	uint32_t MPL0:1;
89	uint32_t MBW1:1; /* Nexus */
90	uint32_t MTR1:1;
91	uint32_t MTW1:1;
92	uint32_t MPL1:1;
93	uint32_t MBW2:1; /* Reserved */
94	uint32_t MTR2:1;
95	uint32_t MTW2:1;
96	uint32_t MPL2:1;
97	uint32_t MBW3:1; /* Reserved */
98	uint32_t MTR3:1;
99	uint32_t MTW3:1;
100	uint32_t MPL3:1;
101	uint32_t MBW4:1; /* eDMA A */
102	uint32_t MTR4:1;
103	uint32_t MTW4:1;
104	uint32_t MPL4:1;
105	uint32_t MBW5:1; /* eDMA B */
106	uint32_t MTR5:1;
107	uint32_t MTW5:1;
108	uint32_t MPL5:1;
109	uint32_t MBW6:1; /* FLEXRAY */
110	uint32_t MTR6:1;
111	uint32_t MTW6:1;
112	uint32_t MPL6:1;
113	uint32_t MBW7:1; /* EBI */
114	uint32_t MTR7:1;
115	uint32_t MTW7:1;
116	uint32_t MPL7:1;
117	} B;
118	} MPCR;
119
120	union { /* Master Privilege Control Register 1 */
121	uint32_t R;
122	struct {
123	uint32_t:32; /* reserved */
124	} B;
125	} MPCR1;
126
127	uint32_t PBRIDGE_A_reserved0008[6]; /* 0x0008-0x001F */
128
129	union { /* Peripheral Access Control Register 0 */
130	uint32_t R;
131	struct {
132	uint32_t BW0:1; /* PBRIDGE_A */
133	uint32_t SP0:1;
134	uint32_t WP0:1;
135	uint32_t TP0:1;
136	uint32_t:4; /* Reserved */
137	uint32_t:4; /* Reserved */
138	uint32_t:4; /* Reserved */
139	uint32_t:4; /* Reserved */
140	uint32_t:4; /* Reserved */
141	uint32_t:4; /* Reserved */
142	uint32_t:4; /* Reserved */
143	} B;
144	} PACR0;
145
146	uint32_t PBRIDGE_A_reserved0024[7]; /* 0x0024-0x003F */
147
148	union { /* Off-Platform Peripheral Access Control Register 0 */
149	uint32_t R;
150	struct {
151	uint32_t BW0:1; /* FMPLL */
152	uint32_t SP0:1;
153	uint32_t WP0:1;
154	uint32_t TP0:1;
155	uint32_t BW1:1; /* EBI control */
156	uint32_t SP1:1;
157	uint32_t WP1:1;
158	uint32_t TP1:1;
159	uint32_t BW2:1; /* Flash A control */
160	uint32_t SP2:1;
161	uint32_t WP2:1;
162	uint32_t TP2:1;
163	uint32_t BW3:1; /* Flash B control */
164	uint32_t SP3:1;
165	uint32_t WP3:1;
166	uint32_t TP3:1;
167	uint32_t BW4:1; /* SIU */
168	uint32_t SP4:1;
169	uint32_t WP4:1;
170	uint32_t TP4:1;
171	uint32_t:4; /* Reserved */
172	uint32_t:4; /* Reserved */
173	uint32_t:4; /* Reserved */
174	} B;
175	} OPACR0;
176
177	union { /* Off-Platform Peripheral Access Control Register 1 */
178	uint32_t R;
179	struct {
180	uint32_t BW0:1; /* EMIOS */
181	uint32_t SP0:1;
182	uint32_t WP0:1;
183	uint32_t TP0:1;
184	uint32_t:4; /* Reserved */
185	uint32_t:4; /* Reserved */
186	uint32_t:4; /* Reserved */
187	uint32_t:4; /* Reserved */
188	uint32_t:4; /* Reserved */
189	uint32_t:4; /* Reserved */
190	uint32_t BW7:1; /* PMC */
191	uint32_t SP7:1;
192	uint32_t WP7:1;
193	uint32_t TP7:1;
194	} B;
195	} OPACR1;
196
197	union { /* Off-Platform Peripheral Access Control Register 2 */
198	uint32_t R;
199	struct {
200	uint32_t BW0:1; /* eTPU */
201	uint32_t SP0:1;
202	uint32_t WP0:1;
203	uint32_t TP0:1;
204	uint32_t:4; /* Reserved */
205	uint32_t BW2:1; /* eTPU PRAM */
206	uint32_t SP2:1;
207	uint32_t WP2:1;
208	uint32_t TP2:1;
209	uint32_t BW3:1; /* eTPU PRAM mirror */
210	uint32_t SP3:1;
211	uint32_t WP3:1;
212	uint32_t TP3:1;
213	uint32_t BW4:1; /* eTPU SCM */
214	uint32_t SP4:1;
215	uint32_t WP4:1;
216	uint32_t TP4:1;
217	uint32_t BW5:1; /* eTPU SCM */
218	uint32_t SP5:1;
219	uint32_t WP5:1;
220	uint32_t TP5:1;
221	uint32_t:4; /* Reserved */
222	uint32_t:4; /* Reserved */
223	} B;
224	} OPACR2;
225
226	union { /* Off-Platform Peripheral Access Control Register 3 */
227	uint32_t R;
228	struct {
229	uint32_t:4; /* Reserved */
230	uint32_t:4; /* Reserved */
231	uint32_t:4; /* Reserved */
232	uint32_t:4; /* Reserved */
233	uint32_t BW4:1; /* PIT/RTI */
234	uint32_t SP4:1;
235	uint32_t WP4:1;
236	uint32_t TP4:1;
237	uint32_t:4; /* Reserved */
238	uint32_t:4; /* Reserved */
239	uint32_t:4; /* Reserved */
240	} B;
241	} OPACR3;
242
243	uint32_t PBRIDGE_A_reserved0050[4076]; /* 0x0050-0x3FFF */
244
245	};
246
247	/****************************************************************************/
248	/* MODULE : PBRIDGE_B Peripheral Bridge */
249	/****************************************************************************/
250
251	struct PBRIDGE_B_tag {
252
253	union { /* Master Privilege Control Register 0 */
254	uint32_t R;
255	struct {
256	uint32_t MBW0:1; /* z7 Core */
257	uint32_t MTR0:1;
258	uint32_t MTW0:1;
259	uint32_t MPL0:1;
260	uint32_t MBW1:1; /* Nexus */
261	uint32_t MTR1:1;
262	uint32_t MTW1:1;
263	uint32_t MPL1:1;
264	uint32_t MBW2:1; /* Reserved */
265	uint32_t MTR2:1;
266	uint32_t MTW2:1;
267	uint32_t MPL2:1;
268	uint32_t MBW3:1; /* Reserved */
269	uint32_t MTR3:1;
270	uint32_t MTW3:1;
271	uint32_t MPL3:1;
272	uint32_t MBW4:1; /* eDMA A */
273	uint32_t MTR4:1;
274	uint32_t MTW4:1;
275	uint32_t MPL4:1;
276	uint32_t MBW5:1; /* eDMA B */
277	uint32_t MTR5:1;
278	uint32_t MTW5:1;
279	uint32_t MPL5:1;
280	uint32_t MBW6:1; /* FLEXRAY */
281	uint32_t MTR6:1;
282	uint32_t MTW6:1;
283	uint32_t MPL6:1;
284	uint32_t MBW7:1; /* EBI */
285	uint32_t MTR7:1;
286	uint32_t MTW7:1;
287	uint32_t MPL7:1;
288	} B;
289	} MPCR;
290
291	union { /* Master Privilege Control Register 1 */
292	uint32_t R;
293	struct {
294	uint32_t:32; /* Reserved */
295
296	} B;
297	} MPCR1;
298
299	uint32_t PBRIDGE_B_reserved0008[6]; /* 0x0008-0x001F */
300
301	union { /* Peripheral Access Control Register 0 */
302	uint32_t R;
303	struct {
304	uint32_t BW0:1; /* PBRIDGE B */
305	uint32_t SP0:1;
306	uint32_t WP0:1;
307	uint32_t TP0:1;
308	uint32_t BW1:1; /* XBAR */
309	uint32_t SP1:1;
310	uint32_t WP1:1;
311	uint32_t TP1:1;
312	uint32_t:4; /* Reserved */
313	uint32_t:4; /* Reserved */
314	uint32_t BW4:1; /* MPU */
315	uint32_t SP4:1;
316	uint32_t WP4:1;
317	uint32_t TP4:1;
318	uint32_t:4; /* Reserved */
319	uint32_t:4; /* Reserved */
320	uint32_t:4; /* Reserved */
321	} B;
322	} PACR0;
323
324	union { /* Peripheral Access Control Register 1 */
325	uint32_t R;
326	struct {
327	uint32_t:4; /* Reserved */
328	uint32_t:4; /* Reserved */
329	uint32_t:4; /* Reserved */
330	uint32_t:4; /* Reserved */
331	uint32_t:4; /* Reserved */
332	uint32_t:4; /* Reserved */
333	uint32_t BW6:1; /* SWT */
334	uint32_t SP6:1;
335	uint32_t WP6:1;
336	uint32_t TP6:1;
337	uint32_t BW7:1; /* STM */
338	uint32_t SP7:1;
339	uint32_t WP7:1;
340	uint32_t TP7:1;
341	} B;
342	} PACR1;
343
344	union { /* Peripheral Access Control Register 2 */
345	uint32_t R;
346	struct {
347	uint32_t BW0:1; /* ECSM */
348	uint32_t SP0:1;
349	uint32_t WP0:1;
350	uint32_t TP0:1;
351	uint32_t BW1:1; /* eDMA A */
352	uint32_t SP1:1;
353	uint32_t WP1:1;
354	uint32_t TP1:1;
355	uint32_t BW2:1; /* INTC */
356	uint32_t SP2:1;
357	uint32_t WP2:1;
358	uint32_t TP2:1;
359	uint32_t:4; /* Reserved */
360	uint32_t:4; /* Reserved */
361	uint32_t BW5:1; /* eDMA B */
362	uint32_t SP5:1;
363	uint32_t WP5:1;
364	uint32_t TP5:1;
365	uint32_t:4; /* Reserved */
366	uint32_t:4; /* Reserved */
367	} B;
368	} PACR2;
369
370	uint32_t PBRIDGE_B_reserved002C[5]; /* 0x002C-0x003F */
371
372	union { /* Off-Platform Peripheral Access Control Register 0 */
373	uint32_t R;
374	struct {
375	uint32_t BW0:1; /* eQADC A */
376	uint32_t SP0:1;
377	uint32_t WP0:1;
378	uint32_t TP0:1;
379	uint32_t BW1:1; /* eQADC B */
380	uint32_t SP1:1;
381	uint32_t WP1:1;
382	uint32_t TP1:1;
383	uint32_t BW2:1; /* Decimation Filters A, B, C, D */
384	uint32_t SP2:1;
385	uint32_t WP2:1;
386	uint32_t TP2:1;
387	uint32_t:4; /* Reserved */
388	uint32_t BW4:1; /* DSPI_A */
389	uint32_t SP4:1;
390	uint32_t WP4:1;
391	uint32_t TP4:1;
392	uint32_t BW5:1; /* DSPI_B */
393	uint32_t SP5:1;
394	uint32_t WP5:1;
395	uint32_t TP5:1;
396	uint32_t BW6:1; /* DSPI_C */
397	uint32_t SP6:1;
398	uint32_t WP6:1;
399	uint32_t TP6:1;
400	uint32_t BW7:1; /* DSPI_D */
401	uint32_t SP7:1;
402	uint32_t WP7:1;
403	uint32_t TP7:1;
404	} B;
405	} OPACR0;
406
407	union { /* Off-Platform Peripheral Access Control Register 1 */
408	uint32_t R;
409	struct {
410	uint32_t:4; /* Reserved */
411	uint32_t:4; /* Reserved */
412	uint32_t:4; /* Reserved */
413	uint32_t:4; /* Reserved */
414	uint32_t BW4:1; /* ESCI_A */
415	uint32_t SP4:1;
416	uint32_t WP4:1;
417	uint32_t TP4:1;
418	uint32_t BW5:1; /* ESCI_B */
419	uint32_t SP5:1;
420	uint32_t WP5:1;
421	uint32_t TP5:1;
422	uint32_t BW6:1; /* ESCI_C */
423	uint32_t SP6:1;
424	uint32_t WP6:1;
425	uint32_t TP6:1;
426	uint32_t:4; /* Reserved */
427	} B;
428	} OPACR1;
429
430	union { /* Off-Platform Peripheral Access Control Register 2 */
431	uint32_t R;
432	struct {
433	uint32_t BW0:1; /* FlexCAN_A */
434	uint32_t SP0:1;
435	uint32_t WP0:1;
436	uint32_t TP0:1;
437	uint32_t BW1:1; /* FlexCAN_B */
438	uint32_t SP1:1;
439	uint32_t WP1:1;
440	uint32_t TP1:1;
441	uint32_t BW2:1; /* FlexCAN_C */
442	uint32_t SP2:1;
443	uint32_t WP2:1;
444	uint32_t TP2:1;
445	uint32_t BW3:1; /* FlexCAN_D */
446	uint32_t SP3:1;
447	uint32_t WP3:1;
448	uint32_t TP3:1;
449	uint32_t:4; /* Reserved */
450	uint32_t:4; /* Reserved */
451	uint32_t:4; /* Reserved */
452	uint32_t:4; /* Reserved */
453	} B;
454	} OPACR2;
455
456	union { /* Off-Platform Peripheral Access Control Register 3 */
457	uint32_t R;
458	struct {
459	uint32_t BW0:1; /* FlexRAY */
460	uint32_t SP0:1;
461	uint32_t WP0:1;
462	uint32_t TP0:1;
463	uint32_t:4; /* Reserved */
464	uint32_t:4; /* Reserved */
465	uint32_t BW3:1; /* Temp Sensor */
466	uint32_t SP3:1;
467	uint32_t WP3:1;
468	uint32_t TP3:1;
469	uint32_t:4; /* Reserved */
470	uint32_t:4; /* Reserved */
471	uint32_t:4; /* Reserved */
472	uint32_t BW7:1; /* BAM */
473	uint32_t SP7:1;
474	uint32_t WP7:1;
475	uint32_t TP7:1;
476	} B;
477	} OPACR3;
478
479	uint32_t PBRIDGE_B_reserved0050[4076]; /* 0x0050-0x3FFF */
480
481	};
482
483	/****************************************************************************/
484	/* MODULE : FMPLL */
485	/****************************************************************************/
486
487	struct FMPLL_tag {
488
489	uint32_t FMPLL_reserved0000; /* 0x0000-0x0003 */
490
491	union FMPLL_SYNSR_tag { /* FMPLL Synthesizer Status Register */
492	uint32_t R;
493	struct {
494	uint32_t:22;
495	uint32_t LOLF:1;
496	uint32_t LOC:1;
497	uint32_t MODE:1;
498	uint32_t PLLSEL:1;
499	uint32_t PLLREF:1;
500	uint32_t LOCKS:1;
501	uint32_t LOCK:1;
502	uint32_t LOCF:1;
503	uint32_t CALDONE:1;
504	uint32_t CALPASS:1;
505	} B;
506	} SYNSR;
507
508	union FMPLL_ESYNCR1_tag {/* FMPLL Enhanced Synthesizer Control Register 1 */
509	uint32_t R;
510	struct {
511	uint32_t:1;
512	uint32_t CLKCFG:3;
513	uint32_t:8;
514	uint32_t EPREDIV:4;
515	uint32_t :8;
516	uint32_t EMFD:8;
517	} B;
518	} ESYNCR1;
519
520	union FMPLL_ESYNCR2_tag {/* FMPLL Enhanced Synthesizer Control Register 2 */
521	uint32_t R;
522	struct {
523	uint32_t:8;
524	uint32_t LOCEN:1;
525	uint32_t LOLRE:1;
526	uint32_t LOCRE:1;
527	uint32_t LOLIRQ:1;
528	uint32_t LOCIRQ:1;
529	uint32_t:1;
530	uint32_t ERATE:2;
531	uint32_t CLKCFG_DIS:1;
532	uint32_t:4;
533	uint32_t EDEPTH:3;
534	uint32_t:2;
535	uint32_t ERFD:6;
536	} B;
537	} ESYNCR2;
538
539	uint32_t FMPLL_reserved0010[4092]; /* 0x0010-0x3FFF */
540
541	};
542
543	/****************************************************************************/
544	/* MODULE : External Bus Interface (EBI) */
545	/****************************************************************************/
546
547	struct EBI_CS_tag {
548	uint32_t ebi_cs_reserved [2];
549	};
550
551	struct EBI_CAL_CS_tag {
552	union { /* Calibration Base Register Bank */
553	uint32_t R;
554	struct {
555	uint32_t BA:17;
556	uint32_t:3;
557	uint32_t PS:1;
558	uint32_t:3;
559	uint32_t AD_MUX:1;
560	uint32_t BL:1;
561	uint32_t WEBS:1;
562	uint32_t TBDIP:1;
563	uint32_t:1;
564	uint32_t SETA:1;
565	uint32_t BI:1;
566	uint32_t V:1;
567	} B;
568	} BR;
569
570	union { /* Calibration Option Register Bank */
571	uint32_t R;
572	struct {
573	uint32_t AM:17;
574	uint32_t:7;
575	uint32_t SCY:4;
576	uint32_t:1;
577	uint32_t BSCY:2;
578	uint32_t:1;
579	} B;
580	} OR;
581	};
582
583	struct EBI_tag {
584
585	union { /* Module Configuration Register */
586	uint32_t R;
587	struct {
588	uint32_t:16;
589	uint32_t ACGE:1;
590	uint32_t:8;
591	uint32_t MDIS:1;
592	uint32_t:3;
593	uint32_t D16_31:1;
594	uint32_t AD_MUX:1;
595	uint32_t DBM:1;
596	} B;
597	} MCR;
598
599	uint32_t EBI_reserved0004; /* 0x0004-0x0007 */
600
601	union { /* Transfer Error Status Register */
602	uint32_t R;
603	struct {
604	uint32_t:30;
605	uint32_t TEAF:1;
606	uint32_t BMTF:1;
607	} B;
608	} TESR;
609
610	union { /* Bus Monitor Control Register */
611	uint32_t R;
612	struct {
613	uint32_t:16;
614	uint32_t BMT:8;
615	uint32_t BME:1;
616	uint32_t:7;
617	} B;
618	} BMCR;
619
620	/* Base/Option registers */
621	struct EBI_CS_tag CS[4];
622
623	uint32_t EBI_reserved0030[4]; /* 0x0030-0x003F */
624
625	/* Calibration registers */
626	struct EBI_CAL_CS_tag CAL_CS[4];
627
628	uint32_t EBI_reserved0060[4000]; /* 0x0060-0x3FFF */
629
630	};
631
632	/****************************************************************************/
633	/* MODULE : FLASH */
634	/****************************************************************************/
635
636	struct FLASH_tag {
637
638	union { /* Module Configuration Register */
639	uint32_t R;
640	struct {
641	uint32_t:5;
642	uint32_t SIZE:3;
643	uint32_t:1;
644	uint32_t LAS:3;
645	uint32_t:3;
646	uint32_t MAS:1;
647	uint32_t EER:1;
648	uint32_t RWE:1;
649	uint32_t SBC:1;
650	uint32_t:1;
651	uint32_t PEAS:1;
652	uint32_t DONE:1;
653	uint32_t PEG:1;
654	uint32_t:4;
655	uint32_t PGM:1;
656	uint32_t PSUS:1;
657	uint32_t ERS:1;
658	uint32_t ESUS:1;
659	uint32_t EHV:1;
660	} B;
661	} MCR;
662
663	union LMLR_tag { /* Low/Mid Address Space Block Locking Register */
664	uint32_t R;
665	struct {
666	uint32_t LME:1;
667	uint32_t:10;
668	uint32_t SLOCK:1;
669	uint32_t:2;
670	uint32_t MLOCK:2;
671	uint32_t:6;
672	uint32_t LLOCK:10;
673	} B;
674	} LMLR; /* Legacy naming - refer to LML in Reference Manual */
675
676	union HLR_tag { /* High Address Space Block Locking Register */
677	uint32_t R;
678	struct {
679	uint32_t HBE:1;
680	uint32_t:25;
681	uint32_t HBLOCK:6; /* Legacy naming - refer to HLOCK in Reference Manual */
682	} B;
683	} HLR; /* Legacy naming - refer to HBL in Reference Manual */
684
685	union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */
686	uint32_t R;
687	struct {
688	uint32_t SLE:1;
689	uint32_t:10;
690	uint32_t SSLOCK:1;
691	uint32_t:2;
692	uint32_t SMLOCK:2;
693	uint32_t:6;
694	uint32_t SLLOCK:10;
695	} B;
696	} SLMLR; /* Legacy naming - refer to SLL in Reference Manual */
697
698	union { /* Low/Mid Address Space Block Select Register */
699	uint32_t R;
700	struct {
701	uint32_t:14;
702	uint32_t MSEL:2;
703	uint32_t:6;
704	uint32_t LSEL:10;
705	} B;
706	} LMSR; /* Legacy naming - refer to LMS in Reference Manual */
707
708	union { /* High Address Space Block Select Register */
709	uint32_t R;
710	struct {
711	uint32_t:26;
712	uint32_t HBSEL:6; /* Legacy naming - refer to HSEL in Reference Manual */
713	} B;
714	} HSR; /* Legacy naming - refer to HBS in Reference Manual */
715
716	union { /* Address Register */
717	uint32_t R;
718	struct {
719	uint32_t SAD:1;
720	uint32_t:13;
721	uint32_t ADDR:15;
722	uint32_t:3;
723	} B;
724	} AR; /* Legacy naming - refer to ADR in Reference Manual */
725
726	union { /* Platform Flash Configuration Register 1 */
727	uint32_t R;
728	struct {
729	uint32_t:7;
730	uint32_t M8PFE:1; /* z7 Nexus */
731	uint32_t:1; /* EBI Testing - Reserved */
732	uint32_t M6PFE:1; /* FlexRay */
733	uint32_t M5PFE:1; /* eDMA_B */
734	uint32_t M4PFE:1; /* eDMA_A */
735	uint32_t:1; /* Reserved */
736	uint32_t:1; /* Reserved */
737	uint32_t:1; /* Reserved */
738	uint32_t M0PFE:1; /* z7 Core */
739	uint32_t APC:3;
740	uint32_t WWSC:2;
741	uint32_t RWSC:3;
742	uint32_t:1;
743	uint32_t DPFEN:1;
744	uint32_t:1;
745	uint32_t IPFEN:1;
746	uint32_t:1;
747	uint32_t PFLIM:2;
748	uint32_t BFEN:1;
749	} B;
750	} BIUCR; /* Legacy naming - PFCR1 */
751
752	union { /Platform Flash Access Protection Register /
753	uint32_t R;
754	struct {
755	uint32_t:14;
756	uint32_t M8AP:2; /* z7 Nexus */
757	uint32_t:2; /* EBI Testing - Reserved */
758	uint32_t M6AP:2; /* FlexRay */
759	uint32_t M5AP:2; /* eDMA_B */
760	uint32_t M4AP:2; /* eDMA_A */
761	uint32_t:2; /* Reserved */
762	uint32_t:2; /* Reserved */
763	uint32_t:2; /* Reserved */
764	uint32_t M0AP:2; /* z7 Core */
765	} B;
766	} BIUAPR; /* Legacy naming - refer to PFAPR in Reference Manual */
767
768	union { /* Platform Flash Configuration Register 2 */
769	uint32_t R;
770	struct {
771	uint32_t LBCFG:2;
772	uint32_t:30;
773	} B;
774	} BIUCR2;
775
776	uint32_t FLASH_reserved0028[4086]; /* 0x0028-0x3FFF */
777	};
778
779	/****************************************************************************/
780	/* MODULE : SIU */
781	/****************************************************************************/
782	struct SIU_tag {
783	int32_t SIU_reserved0000 /* 0x0000-0x0003 */;
784
785	union { /* MCU ID Register */
786	uint32_t R;
787	struct {
788	uint32_t PARTNUM:16;
789	uint32_t PKG:4;
790	uint32_t:4;
791	uint32_t MAJOR_REV:4;
792	uint32_t MINOR_REV:4;
793	} B;
794	} MIDR;
795
796	int32_t SIU_reserved0008; /* 0x0008-0x000B */
797
798	union { /* Reset Status Register */
799	uint32_t R;
800	struct {
801	uint32_t PORS:1;
802	uint32_t ERS:1;
803	uint32_t LLRS:1;
804	uint32_t LCRS:1;
805	uint32_t WDRS:1;
806	uint32_t CRS:1;
807	uint32_t SWTRS:1;
808	uint32_t:7;
809	uint32_t SSRS:1;
810	uint32_t SERF:1;
811	uint32_t WKPCFG:1;
812	uint32_t:11;
813	uint32_t ABR:1;
814	uint32_t BOOTCFG:2;
815	uint32_t RGF:1;
816	} B;
817	} RSR;
818
819	union { /* System Reset Control Register */
820	uint32_t R;
821	struct {
822	uint32_t SSR:1;
823	uint32_t SER:1;
824	uint32_t:30; // Removed CRE bit
825	} B;
826	} SRCR;
827
828	union SIU_EISR_tag { /* External Interrupt Status Register */
829	uint32_t R;
830	struct {
831	uint32_t NMI:1;
832	uint32_t:15;
833	uint32_t EIF15:1;
834	uint32_t EIF14:1;
835	uint32_t EIF13:1;
836	uint32_t EIF12:1;
837	uint32_t EIF11:1;
838	uint32_t EIF10:1;
839	uint32_t EIF9:1;
840	uint32_t EIF8:1;
841	uint32_t EIF7:1;
842	uint32_t EIF6:1;
843	uint32_t EIF5:1;
844	uint32_t EIF4:1;
845	uint32_t EIF3:1;
846	uint32_t EIF2:1;
847	uint32_t EIF1:1;
848	uint32_t EIF0:1;
849	} B;
850	} EISR;
851
852	union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
853	uint32_t R;
854	struct {
855	uint32_t NMISEL8:1;
856	uint32_t:7;
857	uint32_t NMISEL0:1;
858	uint32_t:7;
859	uint32_t EIRE15:1;
860	uint32_t EIRE14:1;
861	uint32_t EIRE13:1;
862	uint32_t EIRE12:1;
863	uint32_t EIRE11:1;
864	uint32_t EIRE10:1;
865	uint32_t EIRE9:1;
866	uint32_t EIRE8:1;
867	uint32_t EIRE7:1;
868	uint32_t EIRE6:1;
869	uint32_t EIRE5:1;
870	uint32_t EIRE4:1;
871	uint32_t EIRE3:1;
872	uint32_t EIRE2:1;
873	uint32_t EIRE1:1;
874	uint32_t EIRE0:1;
875	} B;
876	} DIRER;
877
878	union SIU_DIRSR_tag { /* DMA/Interrupt Request Select Register */
879	uint32_t R;
880	struct {
881	uint32_t:28;
882	uint32_t DIRS3:1;
883	uint32_t DIRS2:1;
884	uint32_t DIRS1:1;
885	uint32_t DIRS0:1;
886	} B;
887	} DIRSR;
888
889	union { /* Overrun Status Register */
890	uint32_t R;
891	struct {
892	uint32_t:16;
893	uint32_t OVF15:1;
894	uint32_t OVF14:1;
895	uint32_t OVF13:1;
896	uint32_t OVF12:1;
897	uint32_t OVF11:1;
898	uint32_t OVF10:1;
899	uint32_t OVF9:1;
900	uint32_t OVF8:1;
901	uint32_t OVF7:1;
902	uint32_t OVF6:1;
903	uint32_t OVF5:1;
904	uint32_t OVF4:1;
905	uint32_t OVF3:1;
906	uint32_t OVF2:1;
907	uint32_t OVF1:1;
908	uint32_t OVF0:1;
909	} B;
910	} OSR;
911
912	union SIU_ORER_tag { /* Overrun Request Enable Register */
913	uint32_t R;
914	struct {
915	uint32_t:16;
916	uint32_t ORE15:1;
917	uint32_t ORE14:1;
918	uint32_t ORE13:1;
919	uint32_t ORE12:1;
920	uint32_t ORE11:1;
921	uint32_t ORE10:1;
922	uint32_t ORE9:1;
923	uint32_t ORE8:1;
924	uint32_t ORE7:1;
925	uint32_t ORE6:1;
926	uint32_t ORE5:1;
927	uint32_t ORE4:1;
928	uint32_t ORE3:1;
929	uint32_t ORE2:1;
930	uint32_t ORE1:1;
931	uint32_t ORE0:1;
932	} B;
933	} ORER;
934
935	union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
936	uint32_t R;
937	struct {
938	uint32_t IREE_NMI8:1;
939	uint32_t:7;
940	uint32_t IREE_NMI0:1;
941	uint32_t:7;
942	uint32_t IREE15:1;
943	uint32_t IREE14:1;
944	uint32_t IREE13:1;
945	uint32_t IREE12:1;
946	uint32_t IREE11:1;
947	uint32_t IREE10:1;
948	uint32_t IREE9:1;
949	uint32_t IREE8:1;
950	uint32_t IREE7:1;
951	uint32_t IREE6:1;
952	uint32_t IREE5:1;
953	uint32_t IREE4:1;
954	uint32_t IREE3:1;
955	uint32_t IREE2:1;
956	uint32_t IREE1:1;
957	uint32_t IREE0:1;
958	} B;
959	} IREER;
960
961	union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
962	uint32_t R;
963	struct {
964	uint32_t IFEE_NMI8:1;
965	uint32_t:7;
966	uint32_t IFEE_NMI0:1;
967	uint32_t:7;
968	uint32_t IFEE15:1;
969	uint32_t IFEE14:1;
970	uint32_t IFEE13:1;
971	uint32_t IFEE12:1;
972	uint32_t IFEE11:1;
973	uint32_t IFEE10:1;
974	uint32_t IFEE9:1;
975	uint32_t IFEE8:1;
976	uint32_t IFEE7:1;
977	uint32_t IFEE6:1;
978	uint32_t IFEE5:1;
979	uint32_t IFEE4:1;
980	uint32_t IFEE3:1;
981	uint32_t IFEE2:1;
982	uint32_t IFEE1:1;
983	uint32_t IFEE0:1;
984	} B;
985	} IFEER;
986
987	union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
988	uint32_t R;
989	struct {
990	uint32_t:28;
991	uint32_t DFL:4;
992	} B;
993	} IDFR;
994
995	union { /* External IRQ Filtered Input Register */
996	uint32_t R;
997	struct {
998	uint32_t FI31:1;
999	uint32_t FI30:1;
1000	uint32_t FI29:1;
1001	uint32_t FI28:1;
1002	uint32_t FI27:1;
1003	uint32_t FI26:1;
1004	uint32_t FI25:1;
1005	uint32_t FI24:1;
1006	uint32_t FI23:1;
1007	uint32_t FI22:1;
1008	uint32_t FI21:1;
1009	uint32_t FI20:1;
1010	uint32_t FI19:1;
1011	uint32_t FI18:1;
1012	uint32_t FI17:1;
1013	uint32_t FI16:1;
1014	uint32_t FI15:1;
1015	uint32_t FI14:1;
1016	uint32_t FI13:1;
1017	uint32_t FI12:1;
1018	uint32_t FI11:1;
1019	uint32_t FI10:1;
1020	uint32_t FI9:1;
1021	uint32_t FI8:1;
1022	uint32_t FI7:1;
1023	uint32_t FI6:1;
1024	uint32_t FI5:1;
1025	uint32_t FI4:1;
1026	uint32_t FI3:1;
1027	uint32_t FI2:1;
1028	uint32_t FI1:1;
1029	uint32_t FI0:1;
1030	} B;
1031	} IFIR;
1032
1033	int32_t SIU_reserved0038[2]; /* 0x0038-0x003F */
1034
1035	union SIU_PCR_tag { /* Pad Configuration Registers */
1036	uint16_t R;
1037	struct {
1038	uint16_t:3;
1039	uint16_t PA:3;
1040	uint16_t OBE:1;
1041	uint16_t IBE:1;
1042	uint16_t DSC:2;
1043	uint16_t ODE:1;
1044	uint16_t HYS:1;
1045	uint16_t SRC:2;
1046	uint16_t WPE:1;
1047	uint16_t WPS:1;
1048	} B;
1049	} PCR[512];
1050
1051	int16_t SIU_reserved0440[224]; /* 0x0440-0x05FF */
1052
1053	union { /* GPIO Pin Data Output Registers */
1054	uint8_t R;
1055	struct {
1056	uint8_t:7;
1057	uint8_t PDO:1;
1058	} B;
1059	} GPDO[512];
1060
1061	union { /* GPIO Pin Data Input Registers */
1062	uint8_t R;
1063	struct {
1064	uint8_t:7;
1065	uint8_t PDI:1;
1066	} B;
1067	} GPDI[256];
1068
1069	uint32_t SIU_reserved0900; /* 0x0900-0x0903 */
1070
1071	union { /* External IRQ Input Select Register */
1072	uint32_t R;
1073	struct {
1074	uint32_t ESEL15:2;
1075	uint32_t ESEL14:2;
1076	uint32_t ESEL13:2;
1077	uint32_t ESEL12:2;
1078	uint32_t ESEL11:2;
1079	uint32_t ESEL10:2;
1080	uint32_t ESEL9:2;
1081	uint32_t ESEL8:2;
1082	uint32_t ESEL7:2;
1083	uint32_t ESEL6:2;
1084	uint32_t ESEL5:2;
1085	uint32_t ESEL4:2;
1086	uint32_t ESEL3:2;
1087	uint32_t ESEL2:2;
1088	uint32_t ESEL1:2;
1089	uint32_t ESEL0:2;
1090	} B;
1091	} EIISR;
1092
1093	union { /* DSPI Input Select Register */
1094	uint32_t R;
1095	struct {
1096	uint32_t SINSELA:2;
1097	uint32_t SSSELA:2;
1098	uint32_t SCKSELA:2;
1099	uint32_t TRIGSELA:2;
1100	uint32_t SINSELB:2;
1101	uint32_t SSSELB:2;
1102	uint32_t SCKSELB:2;
1103	uint32_t TRIGSELB:2;
1104	uint32_t SINSELC:2;
1105	uint32_t SSSELC:2;
1106	uint32_t SCKSELC:2;
1107	uint32_t TRIGSELC:2;
1108	uint32_t SINSELD:2;
1109	uint32_t SSSELD:2;
1110	uint32_t SCKSELD:2;
1111	uint32_t TRIGSELD:2;
1112	} B;
1113	} DISR;
1114
1115	int32_t SIU_reserved090C; /* 0x090C-0x090F */
1116
1117	union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1118	uint32_t R;
1119	struct {
1120	uint32_t:1;
1121	uint32_t CTSEL5_0:7;
1122	uint32_t:1;
1123	uint32_t CTSEL4_0:7;
1124	uint32_t:1;
1125	uint32_t CTSEL3_0:7;
1126	uint32_t:1;
1127	uint32_t CTSEL2_0:7;
1128	} B;
1129	} ISEL4;
1130
1131	union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1132	uint32_t R;
1133	struct {
1134	uint32_t:1;
1135	uint32_t CTSEL1_0:7;
1136	uint32_t:1;
1137	uint32_t CTSEL0_0:7;
1138	uint32_t:16;
1139	} B;
1140	} ISEL5;
1141
1142	union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1143	uint32_t R;
1144	struct {
1145	uint32_t:1;
1146	uint32_t CTSEL5_1:7;
1147	uint32_t:1;
1148	uint32_t CTSEL4_1:7;
1149	uint32_t:1;
1150	uint32_t CTSEL3_1:7;
1151	uint32_t:1;
1152	uint32_t CTSEL2_1:7;
1153	} B;
1154	} ISEL6;
1155
1156	union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1157	uint32_t R;
1158	struct {
1159	uint32_t:1;
1160	uint32_t CTSEL1_1:7;
1161	uint32_t:1;
1162	uint32_t CTSEL0_1:7;
1163	uint32_t:16;
1164	} B;
1165	} ISEL7;
1166
1167	union { /* eTPU Input Select Register */
1168	uint32_t R;
1169	struct {
1170	uint32_t:11;
1171	uint32_t ETPU29:1;
1172	uint32_t:3;
1173	uint32_t ETPU28:1;
1174	uint32_t:3;
1175	uint32_t ETPU27:1;
1176	uint32_t:3;
1177	uint32_t ETPU26:1;
1178	uint32_t:3;
1179	uint32_t ETPU25:1;
1180	uint32_t:3;
1181	uint32_t ETPU24:1;
1182	} B;
1183	} ISEL8;
1184
1185	union { /* eQADC Advanced Trigger Select */
1186	uint32_t R;
1187	struct {
1188	uint32_t:27;
1189	uint32_t ETSEL0A:5;
1190	} B;
1191	} ISEL9;
1192
1193	union { /* DecFilter Integrator Control */
1194	uint32_t R;
1195	struct {
1196	uint32_t ZSELA:4;
1197	uint32_t HSELA:4;
1198	uint32_t ZSELB:4;
1199	uint32_t HSELB:4;
1200	uint32_t ZSELC:4;
1201	uint32_t HSELC:4;
1202	uint32_t ZSELD:4;
1203	uint32_t HSELD:4;
1204	} B;
1205	} DECFIL1;
1206
1207	union { /* DecFilter Integrator Control */
1208	uint32_t R;
1209	struct {
1210	uint32_t ZSELE:4;
1211	uint32_t HSELE:4;
1212	uint32_t ZSELF:4;
1213	uint32_t HSELF:4;
1214	uint32_t ZSELG:4;
1215	uint32_t HSELG:4;
1216	uint32_t ZSELH:4;
1217	uint32_t HSELH:4;
1218	} B;
1219	} DECFIL2;
1220
1221
1222	int32_t SIU_reserved0920[20]; /* 0x0930-0x097F */
1223
1224	union { /* Chip Configuration Register Register */
1225	uint32_t R;
1226	struct {
1227	uint32_t:14;
1228	uint32_t MATCH:1;
1229	uint32_t DISNEX:1;
1230	uint32_t:16;
1231	} B;
1232	} CCR;
1233
1234	union { /* External Clock Configuration Register Register */
1235	uint32_t R;
1236	struct {
1237	uint32_t:16;
1238	uint32_t ENGDIV:8;
1239	uint32_t ECSS:1;
1240	uint32_t:3;
1241	uint32_t EBTS:1;
1242	uint32_t:1;
1243	uint32_t EBDF:2;
1244	} B;
1245	} ECCR;
1246
1247	union { /* Compare A Register High */
1248	uint32_t R;
1249	struct {
1250	uint32_t CMPAH:32;
1251	} B;
1252	} CARH;
1253
1254	union { /* Compare A Register Low */
1255	uint32_t R;
1256	struct {
1257	uint32_t CMPAL:32;
1258	} B;
1259	} CARL;
1260
1261	union { /* Compare B Register High */
1262	uint32_t R;
1263	struct {
1264	uint32_t CMPBH:32;
1265	} B;
1266	} CBRH;
1267
1268	union { /* Compare B Register Low */
1269	uint32_t R;
1270	struct {
1271	uint32_t CMPBL:32;
1272	} B;
1273	} CBRL;
1274
1275	int32_t SIU_reserved0998[2]; /* 0x0998-0x099F */
1276
1277	union { /* System Clock Register */
1278	uint32_t R;
1279	struct {
1280	uint32_t:22;
1281	uint32_t IPCLKDIV:2;
1282	uint32_t:3;
1283	uint32_t BYPASS:1;
1284	uint32_t SYSCLKDIV:2;
1285	uint32_t:2;
1286	} B;
1287	} SYSDIV;
1288
1289	union { /* Halt Register */
1290	uint32_t R;
1291	struct {
1292	uint32_t CPUSTP:1; /* CPU and Platform stop request */
1293	uint32_t:4; /* Reserved */
1294	uint32_t TPUSTP:1; /* eTPU_A stop request */
1295	uint32_t NPCSTP:1; /* Nexus stop request */
1296	uint32_t EBISTP:1; /* EBI stop request*/
1297	uint32_t ADCSTP:1; /* eQADC stop request */
1298	uint32_t:1; /* Reserved */
1299	uint32_t MIOSSTP:1; /* eMIOS stop request */
1300	uint32_t DFILSTP:1; /* Decimation filter stop request */
1301	uint32_t:1; /* Reserved */
1302	uint32_t PITSTP:1; /* PIT stop request */
1303	uint32_t:2; /* Reserved */
1304	uint32_t CNDSTP:1; /* FlexCAN D stop request */
1305	uint32_t CNCSTP:1; /* FlexCAN C stop request */
1306	uint32_t CNBSTP:1; /* FlexCAN B stop request */
1307	uint32_t CNASTP:1; /* FlexCAN A stop request */
1308	uint32_t SPIDSTP:1; /* DSPI D stop request */
1309	uint32_t SPICSTP:1; /* DSPI C stop request */
1310	uint32_t SPIBSTP:1; /* DSPI B stop request */
1311	uint32_t SPIASTP:1; /* DSPI C stop request */
1312	uint32_t:5; /* Reserved */
1313	uint32_t SCICSTP:1; /* eSCI C stop request */
1314	uint32_t SCIBSTP:1; /* eSCI B stop request */
1315	uint32_t SCIASTP:1; /* eSCI A stop request */
1316	} B;
1317	} HLT;
1318
1319	union { /* Halt Acknowledge Register */
1320	uint32_t R;
1321	struct {
1322	uint32_t CPUACK:1; /* CPU and Platform stop acknowledge */
1323	uint32_t:4; /* Reserved */
1324	uint32_t TPUACK:1; /* eTPU_A stop acknowledge */
1325	uint32_t NPCACK:1; /* Nexus stop acknowledge */
1326	uint32_t EBIACK:1; /* EBI stop acknowledge*/
1327	uint32_t ADCACK:1; /* eQADC stop acknowledge */
1328	uint32_t:1; /* Reserved */
1329	uint32_t MIOSACK:1; /* eMIOS stop acknowledge */
1330	uint32_t DFILACK:1; /* Decimation filter stop acknowledge */
1331	uint32_t:1; /* Reserved */
1332	uint32_t PITACK:1; /* PIT stop acknowledge */
1333	uint32_t:2; /* Reserved */
1334	uint32_t CNDACK:1; /* FlexCAN D stop acknowledge */
1335	uint32_t CNCACK:1; /* FlexCAN C stop acknowledge */
1336	uint32_t CNBACK:1; /* FlexCAN B stop acknowledge */
1337	uint32_t CNAACK:1; /* FlexCAN A stop acknowledge */
1338	uint32_t SPIDACK:1; /* DSPI D stop acknowledge */
1339	uint32_t SPICACK:1; /* DSPI C stop acknowledge */
1340	uint32_t SPIBACK:1; /* DSPI B stop acknowledge */
1341	uint32_t SPIAACK:1; /* DSPI C stop acknowledge */
1342	uint32_t:5; /* Reserved */
1343	uint32_t SCICACK:1; /* eSCI C stop acknowledge */
1344	uint32_t SCIBACK:1; /* eSCI B stop acknowledge */
1345	uint32_t SCIAACK:1; /* eSCI A stop acknowledge */
1346	} B;
1347	} HLTACK;
1348
1349	int32_t SIU_reserved09AC[21]; /* 0x09AC-0x09FF */
1350
1351	int32_t SIU_reserved0A00[128]; /* 0x0A00-0x0BFF */
1352
1353	union { /* Parallel GPIO Pin Data Output Register */
1354	uint32_t R;
1355	struct {
1356	uint32_t PGPDO0:1;
1357	uint32_t PGPDO1:1;
1358	uint32_t PGPDO2:1;
1359	uint32_t PGPDO3:1;
1360	uint32_t PGPDO4:1;
1361	uint32_t PGPDO5:1;
1362	uint32_t PGPDO6:1;
1363	uint32_t PGPDO7:1;
1364	uint32_t PGPDO8:1;
1365	uint32_t PGPDO9:1;
1366	uint32_t PGPDO10:1;
1367	uint32_t PGPDO11:1;
1368	uint32_t PGPDO12:1;
1369	uint32_t PGPDO13:1;
1370	uint32_t PGPDO14:1;
1371	uint32_t PGPDO15:1;
1372	uint32_t PGPDO16:1;
1373	uint32_t PGPDO17:1;
1374	uint32_t PGPDO18:1;
1375	uint32_t PGPDO19:1;
1376	uint32_t PGPDO20:1;
1377	uint32_t PGPDO21:1;
1378	uint32_t PGPDO22:1;
1379	uint32_t PGPDO23:1;
1380	uint32_t PGPDO24:1;
1381	uint32_t PGPDO25:1;
1382	uint32_t PGPDO26:1;
1383	uint32_t PGPDO27:1;
1384	uint32_t PGPDO28:1;
1385	uint32_t PGPDO29:1;
1386	uint32_t PGPDO30:1;
1387	uint32_t PGPDO31:1;
1388	} B;
1389	} PGPDO[16];
1390
1391	union { /* Parallel GPIO Pin Data Input Register */
1392	uint32_t R;
1393	struct {
1394	uint32_t PGPDI0:1;
1395	uint32_t PGPDI1:1;
1396	uint32_t PGPDI2:1;
1397	uint32_t PGPDI3:1;
1398	uint32_t PGPDI4:1;
1399	uint32_t PGPDI5:1;
1400	uint32_t PGPDI6:1;
1401	uint32_t PGPDI7:1;
1402	uint32_t PGPDI8:1;
1403	uint32_t PGPDI9:1;
1404	uint32_t PGPDI10:1;
1405	uint32_t PGPDI11:1;
1406	uint32_t PGPDI12:1;
1407	uint32_t PGPDI13:1;
1408	uint32_t PGPDI14:1;
1409	uint32_t PGPDI15:1;
1410	uint32_t PGPDI16:1;
1411	uint32_t PGPDI17:1;
1412	uint32_t PGPDI18:1;
1413	uint32_t PGPDI19:1;
1414	uint32_t PGPDI20:1;
1415	uint32_t PGPDI21:1;
1416	uint32_t PGPDI22:1;
1417	uint32_t PGPDI23:1;
1418	uint32_t PGPDI24:1;
1419	uint32_t PGPDI25:1;
1420	uint32_t PGPDI26:1;
1421	uint32_t PGPDI27:1;
1422	uint32_t PGPDI28:1;
1423	uint32_t PGPDI29:1;
1424	uint32_t PGPDI30:1;
1425	uint32_t PGPDI31:1;
1426	} B;
1427	} PGPDI[16];
1428
1429	union { /* Masked Parallel GPIO Pin Data Input Register */
1430	uint32_t R;
1431	struct {
1432	uint32_t MASK0:1;
1433	uint32_t MASK1:1;
1434	uint32_t MASK2:1;
1435	uint32_t MASK3:1;
1436	uint32_t MASK4:1;
1437	uint32_t MASK5:1;
1438	uint32_t MASK6:1;
1439	uint32_t MASK7:1;
1440	uint32_t MASK8:1;
1441	uint32_t MASK9:1;
1442	uint32_t MASK10:1;
1443	uint32_t MASK11:1;
1444	uint32_t MASK12:1;
1445	uint32_t MASK13:1;
1446	uint32_t MASK14:1;
1447	uint32_t MASK15:1;
1448	uint32_t DATA0:1;
1449	uint32_t DATA1:1;
1450	uint32_t DATA2:1;
1451	uint32_t DATA3:1;
1452	uint32_t DATA4:1;
1453	uint32_t DATA5:1;
1454	uint32_t DATA6:1;
1455	uint32_t DATA7:1;
1456	uint32_t DATA8:1;
1457	uint32_t DATA9:1;
1458	uint32_t DATA10:1;
1459	uint32_t DATA11:1;
1460	uint32_t DATA12:1;
1461	uint32_t DATA13:1;
1462	uint32_t DATA14:1;
1463	uint32_t DATA15:1;
1464	} B;
1465	} MPGPDO[32];
1466
1467	union { /* DSPI_A Mask Output High Register */
1468	uint32_t R;
1469	struct {
1470	uint32_t MASK0:1;
1471	uint32_t MASK1:1;
1472	uint32_t MASK2:1;
1473	uint32_t MASK3:1;
1474	uint32_t MASK4:1;
1475	uint32_t MASK5:1;
1476	uint32_t MASK6:1;
1477	uint32_t MASK7:1;
1478	uint32_t MASK8:1;
1479	uint32_t MASK9:1;
1480	uint32_t MASK10:1;
1481	uint32_t MASK11:1;
1482	uint32_t MASK12:1;
1483	uint32_t MASK13:1;
1484	uint32_t MASK14:1;
1485	uint32_t MASK15:1;
1486	uint32_t DATA0:1;
1487	uint32_t DATA1:1;
1488	uint32_t DATA2:1;
1489	uint32_t DATA3:1;
1490	uint32_t DATA4:1;
1491	uint32_t DATA5:1;
1492	uint32_t DATA6:1;
1493	uint32_t DATA7:1;
1494	uint32_t DATA8:1;
1495	uint32_t DATA9:1;
1496	uint32_t DATA10:1;
1497	uint32_t DATA11:1;
1498	uint32_t DATA12:1;
1499	uint32_t DATA13:1;
1500	uint32_t DATA14:1;
1501	uint32_t DATA15:1;
1502	} B;
1503	} DSPIAH;
1504
1505	union { /* DSPI_A Mask Output Low Register */
1506	uint32_t R;
1507	struct {
1508	uint32_t MASK16:1;
1509	uint32_t MASK17:1;
1510	uint32_t MASK18:1;
1511	uint32_t MASK19:1;
1512	uint32_t MASK20:1;
1513	uint32_t MASK21:1;
1514	uint32_t MASK22:1;
1515	uint32_t MASK23:1;
1516	uint32_t MASK24:1;
1517	uint32_t MASK25:1;
1518	uint32_t MASK26:1;
1519	uint32_t MASK27:1;
1520	uint32_t MASK28:1;
1521	uint32_t MASK29:1;
1522	uint32_t MASK30:1;
1523	uint32_t MASK31:1;
1524	uint32_t DATA16:1;
1525	uint32_t DATA17:1;
1526	uint32_t DATA18:1;
1527	uint32_t DATA19:1;
1528	uint32_t DATA20:1;
1529	uint32_t DATA21:1;
1530	uint32_t DATA22:1;
1531	uint32_t DATA23:1;
1532	uint32_t DATA24:1;
1533	uint32_t DATA25:1;
1534	uint32_t DATA26:1;
1535	uint32_t DATA27:1;
1536	uint32_t DATA28:1;
1537	uint32_t DATA29:1;
1538	uint32_t DATA30:1;
1539	uint32_t DATA31:1;
1540	} B;
1541	} DSPIAL;
1542
1543	union { /* DSPI_B Mask Output High Register */
1544	uint32_t R;
1545	struct {
1546	uint32_t MASK0:1;
1547	uint32_t MASK1:1;
1548	uint32_t MASK2:1;
1549	uint32_t MASK3:1;
1550	uint32_t MASK4:1;
1551	uint32_t MASK5:1;
1552	uint32_t MASK6:1;
1553	uint32_t MASK7:1;
1554	uint32_t MASK8:1;
1555	uint32_t MASK9:1;
1556	uint32_t MASK10:1;
1557	uint32_t MASK11:1;
1558	uint32_t MASK12:1;
1559	uint32_t MASK13:1;
1560	uint32_t MASK14:1;
1561	uint32_t MASK15:1;
1562	uint32_t DATA0:1;
1563	uint32_t DATA1:1;
1564	uint32_t DATA2:1;
1565	uint32_t DATA3:1;
1566	uint32_t DATA4:1;
1567	uint32_t DATA5:1;
1568	uint32_t DATA6:1;
1569	uint32_t DATA7:1;
1570	uint32_t DATA8:1;
1571	uint32_t DATA9:1;
1572	uint32_t DATA10:1;
1573	uint32_t DATA11:1;
1574	uint32_t DATA12:1;
1575	uint32_t DATA13:1;
1576	uint32_t DATA14:1;
1577	uint32_t DATA15:1;
1578	} B;
1579	} DSPIBH;
1580
1581	union { /* DSPI_B Mask Output Low Register */
1582	uint32_t R;
1583	struct {
1584	uint32_t MASK16:1;
1585	uint32_t MASK17:1;
1586	uint32_t MASK18:1;
1587	uint32_t MASK19:1;
1588	uint32_t MASK20:1;
1589	uint32_t MASK21:1;
1590	uint32_t MASK22:1;
1591	uint32_t MASK23:1;
1592	uint32_t MASK24:1;
1593	uint32_t MASK25:1;
1594	uint32_t MASK26:1;
1595	uint32_t MASK27:1;
1596	uint32_t MASK28:1;
1597	uint32_t MASK29:1;
1598	uint32_t MASK30:1;
1599	uint32_t MASK31:1;
1600	uint32_t DATA16:1;
1601	uint32_t DATA17:1;
1602	uint32_t DATA18:1;
1603	uint32_t DATA19:1;
1604	uint32_t DATA20:1;
1605	uint32_t DATA21:1;
1606	uint32_t DATA22:1;
1607	uint32_t DATA23:1;
1608	uint32_t DATA24:1;
1609	uint32_t DATA25:1;
1610	uint32_t DATA26:1;
1611	uint32_t DATA27:1;
1612	uint32_t DATA28:1;
1613	uint32_t DATA29:1;
1614	uint32_t DATA30:1;
1615	uint32_t DATA31:1;
1616	} B;
1617	} DSPIBL;
1618
1619	union { /* DSPI_C Mask Output High Register */
1620	uint32_t R;
1621	struct {
1622	uint32_t MASK0:1;
1623	uint32_t MASK1:1;
1624	uint32_t MASK2:1;
1625	uint32_t MASK3:1;
1626	uint32_t MASK4:1;
1627	uint32_t MASK5:1;
1628	uint32_t MASK6:1;
1629	uint32_t MASK7:1;
1630	uint32_t MASK8:1;
1631	uint32_t MASK9:1;
1632	uint32_t MASK10:1;
1633	uint32_t MASK11:1;
1634	uint32_t MASK12:1;
1635	uint32_t MASK13:1;
1636	uint32_t MASK14:1;
1637	uint32_t MASK15:1;
1638	uint32_t DATA0:1;
1639	uint32_t DATA1:1;
1640	uint32_t DATA2:1;
1641	uint32_t DATA3:1;
1642	uint32_t DATA4:1;
1643	uint32_t DATA5:1;
1644	uint32_t DATA6:1;
1645	uint32_t DATA7:1;
1646	uint32_t DATA8:1;
1647	uint32_t DATA9:1;
1648	uint32_t DATA10:1;
1649	uint32_t DATA11:1;
1650	uint32_t DATA12:1;
1651	uint32_t DATA13:1;
1652	uint32_t DATA14:1;
1653	uint32_t DATA15:1;
1654	} B;
1655	} DSPICH;
1656
1657	union { /* DSPI_C Mask Output Low Register */
1658	uint32_t R;
1659	struct {
1660	uint32_t MASK16:1;
1661	uint32_t MASK17:1;
1662	uint32_t MASK18:1;
1663	uint32_t MASK19:1;
1664	uint32_t MASK20:1;
1665	uint32_t MASK21:1;
1666	uint32_t MASK22:1;
1667	uint32_t MASK23:1;
1668	uint32_t MASK24:1;
1669	uint32_t MASK25:1;
1670	uint32_t MASK26:1;
1671	uint32_t MASK27:1;
1672	uint32_t MASK28:1;
1673	uint32_t MASK29:1;
1674	uint32_t MASK30:1;
1675	uint32_t MASK31:1;
1676	uint32_t DATA16:1;
1677	uint32_t DATA17:1;
1678	uint32_t DATA18:1;
1679	uint32_t DATA19:1;
1680	uint32_t DATA20:1;
1681	uint32_t DATA21:1;
1682	uint32_t DATA22:1;
1683	uint32_t DATA23:1;
1684	uint32_t DATA24:1;
1685	uint32_t DATA25:1;
1686	uint32_t DATA26:1;
1687	uint32_t DATA27:1;
1688	uint32_t DATA28:1;
1689	uint32_t DATA29:1;
1690	uint32_t DATA30:1;
1691	uint32_t DATA31:1;
1692	} B;
1693	} DSPICL;
1694
1695	union { /* DSPI_D Mask Output High Register */
1696	uint32_t R;
1697	struct {
1698	uint32_t MASK0:1;
1699	uint32_t MASK1:1;
1700	uint32_t MASK2:1;
1701	uint32_t MASK3:1;
1702	uint32_t MASK4:1;
1703	uint32_t MASK5:1;
1704	uint32_t MASK6:1;
1705	uint32_t MASK7:1;
1706	uint32_t MASK8:1;
1707	uint32_t MASK9:1;
1708	uint32_t MASK10:1;
1709	uint32_t MASK11:1;
1710	uint32_t MASK12:1;
1711	uint32_t MASK13:1;
1712	uint32_t MASK14:1;
1713	uint32_t MASK15:1;
1714	uint32_t DATA0:1;
1715	uint32_t DATA1:1;
1716	uint32_t DATA2:1;
1717	uint32_t DATA3:1;
1718	uint32_t DATA4:1;
1719	uint32_t DATA5:1;
1720	uint32_t DATA6:1;
1721	uint32_t DATA7:1;
1722	uint32_t DATA8:1;
1723	uint32_t DATA9:1;
1724	uint32_t DATA10:1;
1725	uint32_t DATA11:1;
1726	uint32_t DATA12:1;
1727	uint32_t DATA13:1;
1728	uint32_t DATA14:1;
1729	uint32_t DATA15:1;
1730	} B;
1731	} DSPIDH;
1732
1733	union { /* DSPI_D Mask Output Low Register */
1734	uint32_t R;
1735	struct {
1736	uint32_t MASK16:1;
1737	uint32_t MASK17:1;
1738	uint32_t MASK18:1;
1739	uint32_t MASK19:1;
1740	uint32_t MASK20:1;
1741	uint32_t MASK21:1;
1742	uint32_t MASK22:1;
1743	uint32_t MASK23:1;
1744	uint32_t MASK24:1;
1745	uint32_t MASK25:1;
1746	uint32_t MASK26:1;
1747	uint32_t MASK27:1;
1748	uint32_t MASK28:1;
1749	uint32_t MASK29:1;
1750	uint32_t MASK30:1;
1751	uint32_t MASK31:1;
1752	uint32_t DATA16:1;
1753	uint32_t DATA17:1;
1754	uint32_t DATA18:1;
1755	uint32_t DATA19:1;
1756	uint32_t DATA20:1;
1757	uint32_t DATA21:1;
1758	uint32_t DATA22:1;
1759	uint32_t DATA23:1;
1760	uint32_t DATA24:1;
1761	uint32_t DATA25:1;
1762	uint32_t DATA26:1;
1763	uint32_t DATA27:1;
1764	uint32_t DATA28:1;
1765	uint32_t DATA29:1;
1766	uint32_t DATA30:1;
1767	uint32_t DATA31:1;
1768	} B;
1769	} DSPIDL;
1770
1771	int32_t SIU_reserved0D20[8]; /* 0x0D20-0x0D3F */
1772
1773	union { /* ETPU B Select Register */
1774	uint32_t R;
1775	struct {
1776	uint32_t ETPUB15:1;
1777	uint32_t ETPUB14:1;
1778	uint32_t ETPUB13:1;
1779	uint32_t ETPUB12:1;
1780	uint32_t ETPUB11:1;
1781	uint32_t ETPUB10:1;
1782	uint32_t ETPUB9:1;
1783	uint32_t ETPUB8:1;
1784	uint32_t ETPUB7:1;
1785	uint32_t ETPUB6:1;
1786	uint32_t ETPUB5:1;
1787	uint32_t ETPUB4:1;
1788	uint32_t ETPUB3:1;
1789	uint32_t ETPUB2:1;
1790	uint32_t ETPUB1:1;
1791	uint32_t ETPUB0:1;
1792	uint32_t ETPUB31:1;
1793	uint32_t ETPUB30:1;
1794	uint32_t ETPUB29:1;
1795	uint32_t ETPUB28:1;
1796	uint32_t ETPUB27:1;
1797	uint32_t ETPUB26:1;
1798	uint32_t ETPUB25:1;
1799	uint32_t ETPUB24:1;
1800	uint32_t ETPUB23:1;
1801	uint32_t ETPUB22:1;
1802	uint32_t ETPUB21:1;
1803	uint32_t ETPUB20:1;
1804	uint32_t ETPUB19:1;
1805	uint32_t ETPUB18:1;
1806	uint32_t ETPUB17:1;
1807	uint32_t ETPUB16:1;
1808	} B ;
1809	} ETPUBA;
1810
1811	union { /* EMIOS A Select Register */
1812	uint32_t R;
1813	struct {
1814	uint32_t EMIOS7:1;
1815	uint32_t EMIOS6:1;
1816	uint32_t EMIOS5:1;
1817	uint32_t EMIOS4:1;
1818	uint32_t EMIOS3:1;
1819	uint32_t EMIOS2:1;
1820	uint32_t EMIOS1:1;
1821	uint32_t EMIOS0:1;
1822	uint32_t EMIOS8:1;
1823	uint32_t EMIOS9:1;
1824	uint32_t EMIOS10:1;
1825	uint32_t EMIOS11:1;
1826	uint32_t EMIOS12:1;
1827	uint32_t EMIOS13:1;
1828	uint32_t EMIOS14:1;
1829	uint32_t EMIOS15:1;
1830	uint32_t EMIOS16:1;
1831	uint32_t EMIOS17:1;
1832	uint32_t EMIOS18:1;
1833	uint32_t EMIOS19:1;
1834	uint32_t EMIOS20:1;
1835	uint32_t EMIOS21:1;
1836	uint32_t EMIOS22:1;
1837	uint32_t EMIOS23:1;
1838	uint32_t EMIOS0_0:1;
1839	uint32_t EMIOS1_1:1;
1840	uint32_t EMIOS2_2:1;
1841	uint32_t EMIOS3_3:1;
1842	uint32_t EMIOS4_4:1;
1843	uint32_t EMIOS5_5:1;
1844	uint32_t EMIOS6_6:1;
1845	uint32_t EMIOS7_7:1;
1846	} B;
1847	} EMIOSA;
1848
1849	union { /* DSPIAH/L Select Register for DSPI A */
1850	uint32_t R;
1851	struct {
1852	uint32_t DSPIAH0:1;
1853	uint32_t DSPIAH1:1;
1854	uint32_t DSPIAH2:1;
1855	uint32_t DSPIAH3:1;
1856	uint32_t DSPIAH4:1;
1857	uint32_t DSPIAH5:1;
1858	uint32_t DSPIAH6:1;
1859	uint32_t DSPIAH7:1;
1860	uint32_t DSPIAH8:1;
1861	uint32_t DSPIAH9:1;
1862	uint32_t DSPIAH10:1;
1863	uint32_t DSPIAH11:1;
1864	uint32_t DSPIAH12:1;
1865	uint32_t DSPIAH13:1;
1866	uint32_t DSPIAH14:1;
1867	uint32_t DSPIAH15:1;
1868	uint32_t DSPIAL16:1;
1869	uint32_t DSPIAL17:1;
1870	uint32_t DSPIAL18:1;
1871	uint32_t DSPIAL19:1;
1872	uint32_t DSPIAL20:1;
1873	uint32_t DSPIAL21:1;
1874	uint32_t DSPIAL22:1;
1875	uint32_t DSPIAL23:1;
1876	uint32_t DSPIAL24:1;
1877	uint32_t DSPIAL25:1;
1878	uint32_t DSPIAL26:1;
1879	uint32_t DSPIAL27:1;
1880	uint32_t DSPIAL28:1;
1881	uint32_t DSPIAL29:1;
1882	uint32_t DSPIAL30:1;
1883	uint32_t DSPIAL31:1;
1884	} B;
1885	} DSPIAHLA;
1886
1887	int32_t SIU_reserved0D4C; /* 0x0D4C-0x0D4F */
1888
1889	union { /* ETPU A Select Register */
1890	uint32_t R;
1891	struct {
1892	uint32_t ETPUA23:1;
1893	uint32_t ETPUA22:1;
1894	uint32_t ETPUA21:1;
1895	uint32_t ETPUA20:1;
1896	uint32_t ETPUA19:1;
1897	uint32_t ETPUA18:1;
1898	uint32_t ETPUA17:1;
1899	uint32_t ETPUA16:1;
1900	uint32_t ETPUA29:1;
1901	uint32_t ETPUA28:1;
1902	uint32_t ETPUA27:1;
1903	uint32_t ETPUA26:1;
1904	uint32_t ETPUA25:1;
1905	uint32_t ETPUA24:1;
1906	uint32_t ETPUA31:1;
1907	uint32_t ETPUA30:1;
1908	uint32_t ETPUA12:1;
1909	uint32_t ETPUA13:1;
1910	uint32_t ETPUA14:1;
1911	uint32_t ETPUA15:1;
1912	uint32_t ETPUA0:1;
1913	uint32_t ETPUA1:1;
1914	uint32_t ETPUA2:1;
1915	uint32_t ETPUA3:1;
1916	uint32_t ETPUA4:1;
1917	uint32_t ETPUA5:1;
1918	uint32_t ETPUA6:1;
1919	uint32_t ETPUA7:1;
1920	uint32_t ETPUA8:1;
1921	uint32_t ETPUA9:1;
1922	uint32_t ETPUA10:1;
1923	uint32_t ETPUA11:1;
1924	} B ;
1925	} ETPUAB;
1926
1927	union { /* EMIOS B Select Register */
1928	uint32_t R;
1929	struct {
1930	uint32_t EMIOS11:1;
1931	uint32_t EMIOS10:1;
1932	uint32_t EMIOS9:1;
1933	uint32_t EMIOS8:1;
1934	uint32_t EMIOS6:1;
1935	uint32_t EMIOS5:1;
1936	uint32_t EMIOS4:1;
1937	uint32_t EMIOS3:1;
1938	uint32_t EMIOS2:1;
1939	uint32_t EMIOS1:1;
1940	uint32_t EMIOS0:1;
1941	uint32_t EMIOS23:1;
1942	uint32_t EMIOS15:1;
1943	uint32_t EMIOS14:1;
1944	uint32_t EMIOS13:1;
1945	uint32_t EMIOS12:1;
1946	uint32_t EMIOS23_23:1;
1947	uint32_t EMIOS15_15:1;
1948	uint32_t EMIOS14_14:1;
1949	uint32_t EMIOS13_13:1;
1950	uint32_t EMIOS12_12:1;
1951	uint32_t EMIOS11_11:1;
1952	uint32_t EMIOS10_10:1;
1953	uint32_t EMIOS9_9:1;
1954	uint32_t EMIOS8_8:1;
1955	uint32_t EMIOS6_6:1;
1956	uint32_t EMIOS5_5:1;
1957	uint32_t EMIOS4_4:1;
1958	uint32_t EMIOS3_3:1;
1959	uint32_t EMIOS2_2:1;
1960	uint32_t EMIOS1_1:1;
1961	uint32_t EMIOS0_0:1;
1962	} B;
1963	} EMIOSB;
1964
1965	union { /* DSPIBH/L Select Register for DSPI B */
1966	uint32_t R;
1967	struct {
1968	uint32_t DSPIBH0:1;
1969	uint32_t DSPIBH1:1;
1970	uint32_t DSPIBH2:1;
1971	uint32_t DSPIBH3:1;
1972	uint32_t DSPIBH4:1;
1973	uint32_t DSPIBH5:1;
1974	uint32_t DSPIBH6:1;
1975	uint32_t DSPIBH7:1;
1976	uint32_t DSPIBH8:1;
1977	uint32_t DSPIBH9:1;
1978	uint32_t DSPIBH10:1;
1979	uint32_t DSPIBH11:1;
1980	uint32_t DSPIBH12:1;
1981	uint32_t DSPIBH13:1;
1982	uint32_t DSPIBH14:1;
1983	uint32_t DSPIBH15:1;
1984	uint32_t DSPIBL16:1;
1985	uint32_t DSPIBL17:1;
1986	uint32_t DSPIBL18:1;
1987	uint32_t DSPIBL19:1;
1988	uint32_t DSPIBL20:1;
1989	uint32_t DSPIBL21:1;
1990	uint32_t DSPIBL22:1;
1991	uint32_t DSPIBL23:1;
1992	uint32_t DSPIBL24:1;
1993	uint32_t DSPIBL25:1;
1994	uint32_t DSPIBL26:1;
1995	uint32_t DSPIBL27:1;
1996	uint32_t DSPIBL28:1;
1997	uint32_t DSPIBL29:1;
1998	uint32_t DSPIBL30:1;
1999	uint32_t DSPIBL31:1;
2000	} B;
2001	} DSPIBHLB;
2002
2003	int32_t SIU_reserved0D5C; /* 0x0D5C-0x0D5F */
2004
2005	union { /* ETPU A Select Register */
2006	uint32_t R;
2007	struct {
2008	uint32_t ETPUA12:1;
2009	uint32_t ETPUA13:1;
2010	uint32_t ETPUA14:1;
2011	uint32_t ETPUA15:1;
2012	uint32_t ETPUA0:1;
2013	uint32_t ETPUA1:1;
2014	uint32_t ETPUA2:1;
2015	uint32_t ETPUA3:1;
2016	uint32_t ETPUA4:1;
2017	uint32_t ETPUA5:1;
2018	uint32_t ETPUA6:1;
2019	uint32_t ETPUA7:1;
2020	uint32_t ETPUA8:1;
2021	uint32_t ETPUA9:1;
2022	uint32_t ETPUA10:1;
2023	uint32_t ETPUA11:1;
2024	uint32_t ETPUA23:1;
2025	uint32_t ETPUA22:1;
2026	uint32_t ETPUA21:1;
2027	uint32_t ETPUA20:1;
2028	uint32_t ETPUA19:1;
2029	uint32_t ETPUA18:1;
2030	uint32_t ETPUA17:1;
2031	uint32_t ETPUA16:1;
2032	uint32_t ETPUA29:1;
2033	uint32_t ETPUA28:1;
2034	uint32_t ETPUA27:1;
2035	uint32_t ETPUA26:1;
2036	uint32_t ETPUA25:1;
2037	uint32_t ETPUA24:1;
2038	uint32_t ETPUA31:1;
2039	uint32_t ETPUA30:1;
2040	} B ;
2041	} ETPUAC;
2042
2043	union { /* EMIOS C Select Register */
2044	uint32_t R;
2045	struct {
2046	uint32_t EMIOS12:1;
2047	uint32_t EMIOS13:1;
2048	uint32_t EMIOS14:1;
2049	uint32_t EMIOS15:1;
2050	uint32_t EMIOS23:1;
2051	uint32_t EMIOS0:1;
2052	uint32_t EMIOS1:1;
2053	uint32_t EMIOS2:1;
2054	uint32_t EMIOS3:1;
2055	uint32_t EMIOS4:1;
2056	uint32_t EMIOS5:1;
2057	uint32_t EMIOS6:1;
2058	uint32_t EMIOS8:1;
2059	uint32_t EMIOS9:1;
2060	uint32_t EMIOS10:1;
2061	uint32_t EMIOS11:1;
2062	uint32_t EMIOS23_23:1;
2063	uint32_t EMIOS22:1;
2064	uint32_t EMIOS21:1;
2065	uint32_t EMIOS20:1;
2066	uint32_t EMIOS19:1;
2067	uint32_t EMIOS18:1;
2068	uint32_t EMIOS17:1;
2069	uint32_t EMIOS16:1;
2070	uint32_t EMIOS29:1;
2071	uint32_t EMIOS28:1;
2072	uint32_t EMIOS27:1;
2073	uint32_t EMIOS26:1;
2074	uint32_t EMIOS25:1;
2075	uint32_t EMIOS24:1;
2076	uint32_t EMIOS31:1;
2077	uint32_t EMIOS30:1;
2078	} B;
2079	} EMIOSC;
2080
2081	union { /* DSPICH/L Select Register for DSPI C */
2082	uint32_t R;
2083	struct {
2084	uint32_t DSPICH0:1;
2085	uint32_t DSPICH1:1;
2086	uint32_t DSPICH2:1;
2087	uint32_t DSPICH3:1;
2088	uint32_t DSPICH4:1;
2089	uint32_t DSPICH5:1;
2090	uint32_t DSPICH6:1;
2091	uint32_t DSPICH7:1;
2092	uint32_t DSPICH8:1;
2093	uint32_t DSPICH9:1;
2094	uint32_t DSPICH10:1;
2095	uint32_t DSPICH11:1;
2096	uint32_t DSPICH12:1;
2097	uint32_t DSPICH13:1;
2098	uint32_t DSPICH14:1;
2099	uint32_t DSPICH15:1;
2100	uint32_t DSPICL16:1;
2101	uint32_t DSPICL17:1;
2102	uint32_t DSPICL18:1;
2103	uint32_t DSPICL19:1;
2104	uint32_t DSPICL20:1;
2105	uint32_t DSPICL21:1;
2106	uint32_t DSPICL22:1;
2107	uint32_t DSPICL23:1;
2108	uint32_t DSPICL24:1;
2109	uint32_t DSPICL25:1;
2110	uint32_t DSPICL26:1;
2111	uint32_t DSPICL27:1;
2112	uint32_t DSPICL28:1;
2113	uint32_t DSPICL29:1;
2114	uint32_t DSPICL30:1;
2115	uint32_t DSPICL31:1;
2116	} B;
2117	} DSPICHLC;
2118
2119	int32_t SIU_reserved0D6C; /* 0x0D6C-0x0D6F */
2120
2121	union { /* ETPU B Select Register */
2122	uint32_t R;
2123	struct {
2124	uint32_t ETPUB21:1;
2125	uint32_t ETPUB20:1;
2126	uint32_t ETPUB19:1;
2127	uint32_t ETPUB18:1;
2128	uint32_t ETPUB17:1;
2129	uint32_t ETPUB16:1;
2130	uint32_t:4;
2131	uint32_t ETPUB29:1;
2132	uint32_t ETPUB28:1;
2133	uint32_t ETPUB27:1;
2134	uint32_t ETPUB26:1;
2135	uint32_t ETPUB25:1;
2136	uint32_t ETPUB24:1;
2137	uint32_t:16;
2138	} B ;
2139	} ETPUBD;
2140
2141	union { /* EMIOS D Select Register */
2142	uint32_t R;
2143	struct {
2144	uint32_t:6;
2145	uint32_t EMIOS11:1;
2146	uint32_t EMIOS10:1;
2147	uint32_t EMIOS13:1;
2148	uint32_t EMIOS12:1;
2149	uint32_t:22;
2150	} B;
2151	} EMIOSD;
2152
2153	union { /* DSPIDH/L Select Register for DSPI D */
2154	uint32_t R;
2155	struct {
2156	uint32_t:32;
2157	} B;
2158	} DSPIDHLD;
2159
2160	int32_t SIU_reserved0D7C; /* 0x0D7C-0x0D7F */
2161
2162	int32_t SIU_reserved0D80[32]; /* 0x0D80-0x0DFF */
2163
2164	union { /* GPIO Pin Data Input Registers */
2165	uint8_t R;
2166	struct {
2167	uint8_t:7;
2168	uint8_t PDI:1;
2169	} B;
2170	} GPDI0_511[512];
2171
2172	uint32_t SIU_reserved1000[3072]; /* 0x1000-0x3FFF */
2173	};
2174
2175	/****************************************************************************/
2176	/* MODULE : EMIOS */
2177	/****************************************************************************/
2178
2179	struct EMIOS_tag {
2180
2181	union EMIOS_MCR_tag { /* Module Configuration Register */
2182	uint32_t R;
2183	struct {
2184	uint32_t:1;
2185	uint32_t MDIS:1;
2186	uint32_t FRZ:1;
2187	uint32_t GTBE:1;
2188	uint32_t ETB:1;
2189	uint32_t GPREN:1;
2190	uint32_t:6;
2191	uint32_t SRV:4;
2192	uint32_t GPRE:8;
2193	uint32_t:8;
2194	} B;
2195	} MCR;
2196
2197	union { /* Global FLAG Register */
2198	uint32_t R;
2199	struct {
2200	uint32_t F31:1;
2201	uint32_t F30:1;
2202	uint32_t F29:1;
2203	uint32_t F28:1;
2204	uint32_t F27:1;
2205	uint32_t F26:1;
2206	uint32_t F25:1;
2207	uint32_t F24:1;
2208	uint32_t F23:1;
2209	uint32_t F22:1;
2210	uint32_t F21:1;
2211	uint32_t F20:1;
2212	uint32_t F19:1;
2213	uint32_t F18:1;
2214	uint32_t F17:1;
2215	uint32_t F16:1;
2216	uint32_t F15:1;
2217	uint32_t F14:1;
2218	uint32_t F13:1;
2219	uint32_t F12:1;
2220	uint32_t F11:1;
2221	uint32_t F10:1;
2222	uint32_t F9:1;
2223	uint32_t F8:1;
2224	uint32_t F7:1;
2225	uint32_t F6:1;
2226	uint32_t F5:1;
2227	uint32_t F4:1;
2228	uint32_t F3:1;
2229	uint32_t F2:1;
2230	uint32_t F1:1;
2231	uint32_t F0:1;
2232	} B;
2233	} GFR;
2234
2235	union { /* Output Update Disable Register */
2236	uint32_t R;
2237	struct {
2238	uint32_t OU31:1;
2239	uint32_t OU30:1;
2240	uint32_t OU29:1;
2241	uint32_t OU28:1;
2242	uint32_t OU27:1;
2243	uint32_t OU26:1;
2244	uint32_t OU25:1;
2245	uint32_t OU24:1;
2246	uint32_t OU23:1;
2247	uint32_t OU22:1;
2248	uint32_t OU21:1;
2249	uint32_t OU20:1;
2250	uint32_t OU19:1;
2251	uint32_t OU18:1;
2252	uint32_t OU17:1;
2253	uint32_t OU16:1;
2254	uint32_t OU15:1;
2255	uint32_t OU14:1;
2256	uint32_t OU13:1;
2257	uint32_t OU12:1;
2258	uint32_t OU11:1;
2259	uint32_t OU10:1;
2260	uint32_t OU9:1;
2261	uint32_t OU8:1;
2262	uint32_t OU7:1;
2263	uint32_t OU6:1;
2264	uint32_t OU5:1;
2265	uint32_t OU4:1;
2266	uint32_t OU3:1;
2267	uint32_t OU2:1;
2268	uint32_t OU1:1;
2269	uint32_t OU0:1;
2270	} B;
2271	} OUDR;
2272
2273	uint32_t eMIOS_reserved000C[5]; /* 0x000C-0x001F */
2274
2275	struct EMIOS_CH_tag {
2276	union { /* Channel A Data Register */
2277	uint32_t R;
2278	} CADR;
2279
2280	union { /* Channel B Data Register */
2281	uint32_t R;
2282	} CBDR;
2283
2284	union { /* Channel Counter Register */
2285	uint32_t R;
2286	} CCNTR;
2287
2288	union EMIOS_CCR_tag {/* Channel Control Register */
2289	uint32_t R;
2290	struct {
2291	uint32_t FREN:1;
2292	uint32_t ODIS:1;
2293	uint32_t ODISSL:2;
2294	uint32_t UCPRE:2;
2295	uint32_t UCPREN:1;
2296	uint32_t DMA:1;
2297	uint32_t:1;
2298	uint32_t IF:4;
2299	uint32_t FCK:1;
2300	uint32_t FEN:1;
2301	uint32_t:3;
2302	uint32_t FORCMA:1;
2303	uint32_t FORCMB:1;
2304	uint32_t:1;
2305	uint32_t BSL:2;
2306	uint32_t EDSEL:1;
2307	uint32_t EDPOL:1;
2308	uint32_t MODE:7;
2309	} B;
2310	} CCR;
2311
2312	union EMIOS_CSR_tag {/* Channel Status Register */
2313	uint32_t R;
2314	struct {
2315	uint32_t OVR:1;
2316	uint32_t:15;
2317	uint32_t OVFL:1;
2318	uint32_t:12;
2319	uint32_t UCIN:1;
2320	uint32_t UCOUT:1;
2321	uint32_t FLAG:1;
2322	} B;
2323	} CSR;
2324
2325	union { /* Alternate Channel A Data Register */
2326	uint32_t R;
2327	} ALTA;
2328
2329	uint32_t eMIOS_channel_reserved0018[2]; /* 0x0018-0x001F */
2330
2331	} CH[32];
2332
2333	uint32_t eMIOS_reserved0420[3832]; /* 0x0420-0x3FFF */
2334
2335	};
2336
2337	/****************************************************************************/
2338	/* MODULE : PMC */
2339	/****************************************************************************/
2340
2341	struct PMC_tag {
2342
2343	union {
2344	uint32_t R;
2345	struct {
2346	uint32_t LVRER:1;
2347	uint32_t LVREH:1;
2348	uint32_t LVRE50:1;
2349	uint32_t LVRE33:1;
2350	uint32_t LVREC:1;
2351	uint32_t LVREA:1;
2352	uint32_t:1;
2353	uint32_t:1;
2354	uint32_t LVIER:1;
2355	uint32_t LVIEH:1;
2356	uint32_t LVIE50:1;
2357	uint32_t LVIE33:1;
2358	uint32_t LVIEC:1;
2359	uint32_t LVIEA:1;
2360	uint32_t:1;
2361	uint32_t TLK:1;
2362	uint32_t:16;
2363	} B;
2364	} MCR; /* Module Configuration Register */
2365
2366	union {
2367	uint32_t R;
2368	struct {
2369	uint32_t :8;
2370	uint32_t LVDATRIM:4;
2371	uint32_t LVDREGTRIM:4;
2372	uint32_t VDD33TRIM:4;
2373	uint32_t LVD33TRIM:4;
2374	uint32_t VDDCTRIM:4;
2375	uint32_t LVDCTRIM:4;
2376	} B;
2377	} TRIMR; /* Trimming register */
2378
2379	union {
2380	uint32_t R;
2381	struct {
2382	uint32_t :5;
2383	uint32_t LVFSTBY:1;
2384	uint32_t BGRDY:1;
2385	uint32_t BGTS:1;
2386	uint32_t :5;
2387	uint32_t LVFCSTBY:1;
2388	uint32_t :2;
2389	uint32_t LVFCR:1;
2390	uint32_t LVFCH:1;
2391	uint32_t LVFC50:1;
2392	uint32_t LVFC33:1;
2393	uint32_t LVFCC:1;
2394	uint32_t LVFCA:1;
2395	uint32_t :2;
2396	uint32_t LVFR:1;
2397	uint32_t LVFH:1;
2398	uint32_t LVF50:1;
2399	uint32_t LVF33:1;
2400	uint32_t LVFC:1;
2401	uint32_t LVFA:1;
2402	uint32_t :2;
2403	} B;
2404	} SR; /* status register */
2405
2406	uint32_t PMC_reserved000C[4093]; /* 0x000C-0x3FFF */
2407	};
2408
2409	/****************************************************************************/
2410	/* MODULE :ETPU */
2411	/****************************************************************************/
2412
2413	/*************************Configuration Registers************************/
2414
2415	struct ETPU_tag {
2416	union { /* MODULE CONFIGURATION REGISTER */
2417	uint32_t R;
2418	struct {
2419	uint32_t GEC:1; /* Global Exception Clear */
2420	uint32_t SDMERR:1; /* SDM Read Error */
2421	uint32_t WDTOA:1; /* Watchdog Timeout-eTPU_A */
2422	uint32_t WDTOB:1; /* Watchdog Timeout-eTPU_B */
2423	uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
2424	uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */
2425	uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
2426	uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */
2427	uint32_t:3;
2428	uint32_t SCMSIZE:5; /* Shared Code Memory size */
2429	uint32_t:4;
2430	uint32_t SCMMISC:1; /* SCM MISC Complete/Clear */
2431	uint32_t SCMMISF:1; /* SCM MISC Flag */
2432	uint32_t SCMMISEN:1; /* SCM MISC Enable */
2433	uint32_t:2;
2434	uint32_t VIS:1; /* SCM Visability */
2435	uint32_t:5;
2436	uint32_t GTBE:1; /* Global Time Base Enable */
2437	} B;
2438	} MCR;
2439
2440	union { /* COHERENT DUAL-PARAMETER CONTROL */
2441	uint32_t R;
2442	struct {
2443	uint32_t STS:1; /* Start Status bit */
2444	uint32_t CTBASE:5; /* Channel Transfer Base */
2445	uint32_t PBASE:10; /* Parameter Buffer Base Address */
2446	uint32_t PWIDTH:1; /* Parameter Width */
2447	uint32_t PARAM0:7; /* Channel Parameter 0 */
2448	uint32_t WR:1; /* Read/Write selection */
2449	uint32_t PARAM1:7; /* Channel Parameter 1 */
2450	} B;
2451	} CDCR;
2452
2453	uint32_t eTPU_reserved0008; /* 0x0008-0x000B */
2454
2455	union { /* MISC Compare Register */
2456	uint32_t R;
2457	struct {
2458	uint32_t ETPUMISCCMP:32;
2459	} B;
2460	} MISCCMPR;
2461
2462	union { /* SCM off-range Date Register */
2463	uint32_t R;
2464	struct {
2465	uint32_t ETPUSCMOFFDATA:32;
2466	} B;
2467	} SCMOFFDATAR;
2468
2469	union { /* ETPU_A Configuration Register */
2470	uint32_t R;
2471	struct {
2472	uint32_t FEND:1; /* Force END */
2473	uint32_t MDIS:1; /* Low power Stop */
2474	uint32_t:1;
2475	uint32_t STF:1; /* Stop Flag */
2476	uint32_t:4;
2477	uint32_t HLTF:1; /* Halt Mode Flag */
2478	uint32_t:3;
2479	uint32_t FCSS:1; /* Filter Clock Source Select */
2480	uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
2481	uint32_t CDFC:2;
2482	uint32_t:1;
2483	uint32_t ERBA:5; /* Engine Relative Base Address */
2484	uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */
2485	uint32_t:2;
2486	uint32_t ETB:5; /* Entry Table Base */
2487	} B;
2488	} ECR_A;
2489
2490	union { /* ETPU_B Configuration Register */
2491	uint32_t R;
2492	struct {
2493	uint32_t FEND:1; /* Force END */
2494	uint32_t MDIS:1; /* Low power Stop */
2495	uint32_t:1;
2496	uint32_t STF:1; /* Stop Flag */
2497	uint32_t:4;
2498	uint32_t HLTF:1; /* Halt Mode Flag */
2499	uint32_t:3;
2500	uint32_t FCSS:1; /* Filter Clock Source Select */
2501	uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
2502	uint32_t CDFC:2;
2503	uint32_t:1;
2504	uint32_t ERBA:5; /* Engine Relative Base Address */
2505	uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */
2506	uint32_t:2;
2507	uint32_t ETB:5; /* Entry Table Base */
2508	} B;
2509	} ECR_B;
2510
2511	uint32_t eTPU_reserved001C; /* 0x001C-0x001F */
2512
2513	union { /* ETPU_A Timebase Configuration Register */
2514	uint32_t R;
2515	struct {
2516	uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
2517	uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
2518	uint32_t AM:2; /* Angle Mode */
2519	uint32_t:3;
2520	uint32_t TCR2P:6; /* TCR2 Prescaler Control */
2521	uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
2522	uint32_t TCR1CS:1; /* TCR1 Clock Source */
2523	uint32_t:5;
2524	uint32_t TCR1P:8; /* TCR1 Prescaler Control */
2525	} B;
2526	} TBCR_A;
2527
2528	union { /* ETPU_A TCR1 Visibility Register */
2529	uint32_t R;
2530	struct {
2531	uint32_t:8;
2532	uint32_t TCR1:24;
2533	} B;
2534	} TB1R_A;
2535
2536	union { /* ETPU_A TCR2 Visibility Register */
2537	uint32_t R;
2538	struct {
2539	uint32_t:8;
2540	uint32_t TCR2:24;
2541	} B;
2542	} TB2R_A;
2543
2544	union { /* ETPU_A STAC Configuration Register */
2545	uint32_t R;
2546	struct {
2547	uint32_t REN1:1; /* Resource Enable TCR1 */
2548	uint32_t RSC1:1; /* Resource Control TCR1 */
2549	uint32_t:2;
2550	uint32_t SERVER_ID1:4; /* TCR1 Server ID */
2551	uint32_t:4;
2552	uint32_t SRV1:4; /* Resource Server Slot */
2553	uint32_t REN2:1; /* Resource Enable TCR2 */
2554	uint32_t RSC2:1; /* Resource Control TCR2 */
2555	uint32_t:2;
2556	uint32_t SERVER_ID2:4; /* TCR2 Server ID */
2557	uint32_t:4;
2558	uint32_t SRV2:4; /* Resource Server Slot */
2559	} B;
2560	} REDCR_A;
2561
2562	uint32_t eTPU_reserved0030[4]; /* 0x0030-0x003F */
2563
2564	union { /* ETPU_B Timebase Configuration Register */
2565	uint32_t R;
2566	struct {
2567	uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
2568	uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
2569	uint32_t AM:2; /* Angle Mode */
2570	uint32_t:3;
2571	uint32_t TCR2P:6; /* TCR2 Prescaler Control */
2572	uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
2573	uint32_t TCR1CS:1; /* TCR1 Clock Source */
2574	uint32_t:5;
2575	uint32_t TCR1P:8; /* TCR1 Prescaler Control */
2576	} B;
2577	} TBCR_B;
2578
2579	union { /* ETPU_B TCR1 Visibility Register */
2580	uint32_t R;
2581	struct {
2582	uint32_t:8;
2583	uint32_t TCR1:24;
2584	} B;
2585	} TB1R_B;
2586
2587	union { /* ETPU_B TCR2 Visibility Register */
2588	uint32_t R;
2589	struct {
2590	uint32_t:8;
2591	uint32_t TCR2:24;
2592	} B;
2593	} TB2R_B;
2594
2595	union { /* ETPU_B STAC Configuration Register */
2596	uint32_t R;
2597	struct {
2598	uint32_t REN1:1; /* Resource Enable TCR1 */
2599	uint32_t RSC1:1; /* Resource Control TCR1 */
2600	uint32_t:2;
2601	uint32_t SERVER_ID1:4; /* TCR1 Server ID */
2602	uint32_t:4;
2603	uint32_t SRV1:4; /* Resource Server Slot */
2604	uint32_t REN2:1; /* Resource Enable TCR2 */
2605	uint32_t RSC2:1; /* Resource Control TCR2 */
2606	uint32_t:2;
2607	uint32_t SERVER_ID2:4; /* TCR2 Server ID */
2608	uint32_t:4;
2609	uint32_t SRV2:4; /* Resource Server Slot */
2610	} B;
2611	} REDCR_B;
2612
2613	uint32_t eTPU_reserved0050[4]; /* 0x0050-0x005F */
2614
2615	union { /* Watchdog Timer Register A */
2616	uint32_t R;
2617	struct {
2618	uint32_t WDM:2; /* Watchdog Mode */
2619	uint32_t:14;
2620	uint32_t WDCNT:16; /* Watchdog Count */
2621	} B;
2622	} WDTR_A;
2623
2624	uint32_t eTPU_reserved0064; /* 0x0064-0x0067 */
2625
2626	union { /* Idle Counter Register A*/
2627	uint32_t R;
2628	struct {
2629	uint32_t IDLE_CNT:31;
2630	uint32_t ICLR:1; /* Idle Clear */
2631	} B;
2632
2633	} IDLE_A;
2634
2635	uint32_t eTPU_reserved006C; /* 0x006C-0x006F */
2636
2637	union { /* Watchdog Timer Register B */
2638	uint32_t R;
2639	struct {
2640	uint32_t WDM:2; /* Watchdog Mode */
2641	uint32_t:14;
2642	uint32_t WDCNT:16; /* Watchdog Count */
2643	} B;
2644	} WDTR_B;
2645
2646	uint32_t eTPU_reserved0074; /* 0x0074-0x0077 */
2647
2648	union { /* Idle Counter Register B*/
2649	uint32_t R;
2650	struct {
2651	uint32_t IDLE_CNT:31;
2652	uint32_t ICLR:1; /* Idle Clear */
2653	} B;
2654	} IDLE_B;
2655
2656	uint32_t eTPU_reserved007C; /* 0x007C-0x007F */
2657
2658	uint32_t eTPU_reserved0080[96]; /* 0x0080-0x01FF */
2659
2660	/***************************Status and Control Registers************************/
2661
2662	union { /* ETPU_A Channel Interrut Status */
2663	uint32_t R;
2664	struct {
2665	uint32_t CIS31:1; /* Channel 31 Interrut Status */
2666	uint32_t CIS30:1; /* Channel 30 Interrut Status */
2667	uint32_t CIS29:1; /* Channel 29 Interrut Status */
2668	uint32_t CIS28:1; /* Channel 28 Interrut Status */
2669	uint32_t CIS27:1; /* Channel 27 Interrut Status */
2670	uint32_t CIS26:1; /* Channel 26 Interrut Status */
2671	uint32_t CIS25:1; /* Channel 25 Interrut Status */
2672	uint32_t CIS24:1; /* Channel 24 Interrut Status */
2673	uint32_t CIS23:1; /* Channel 23 Interrut Status */
2674	uint32_t CIS22:1; /* Channel 22 Interrut Status */
2675	uint32_t CIS21:1; /* Channel 21 Interrut Status */
2676	uint32_t CIS20:1; /* Channel 20 Interrut Status */
2677	uint32_t CIS19:1; /* Channel 19 Interrut Status */
2678	uint32_t CIS18:1; /* Channel 18 Interrut Status */
2679	uint32_t CIS17:1; /* Channel 17 Interrut Status */
2680	uint32_t CIS16:1; /* Channel 16 Interrut Status */
2681	uint32_t CIS15:1; /* Channel 15 Interrut Status */
2682	uint32_t CIS14:1; /* Channel 14 Interrut Status */
2683	uint32_t CIS13:1; /* Channel 13 Interrut Status */
2684	uint32_t CIS12:1; /* Channel 12 Interrut Status */
2685	uint32_t CIS11:1; /* Channel 11 Interrut Status */
2686	uint32_t CIS10:1; /* Channel 10 Interrut Status */
2687	uint32_t CIS9:1; /* Channel 9 Interrut Status */
2688	uint32_t CIS8:1; /* Channel 8 Interrut Status */
2689	uint32_t CIS7:1; /* Channel 7 Interrut Status */
2690	uint32_t CIS6:1; /* Channel 6 Interrut Status */
2691	uint32_t CIS5:1; /* Channel 5 Interrut Status */
2692	uint32_t CIS4:1; /* Channel 4 Interrut Status */
2693	uint32_t CIS3:1; /* Channel 3 Interrut Status */
2694	uint32_t CIS2:1; /* Channel 2 Interrut Status */
2695	uint32_t CIS1:1; /* Channel 1 Interrut Status */
2696	uint32_t CIS0:1; /* Channel 0 Interrut Status */
2697	} B;
2698	} CISR_A;
2699
2700	union { /* ETPU_B Channel Interruput Status */
2701	uint32_t R;
2702	struct {
2703	uint32_t CIS31:1; /* Channel 31 Interrut Status */
2704	uint32_t CIS30:1; /* Channel 30 Interrut Status */
2705	uint32_t CIS29:1; /* Channel 29 Interrut Status */
2706	uint32_t CIS28:1; /* Channel 28 Interrut Status */
2707	uint32_t CIS27:1; /* Channel 27 Interrut Status */
2708	uint32_t CIS26:1; /* Channel 26 Interrut Status */
2709	uint32_t CIS25:1; /* Channel 25 Interrut Status */
2710	uint32_t CIS24:1; /* Channel 24 Interrut Status */
2711	uint32_t CIS23:1; /* Channel 23 Interrut Status */
2712	uint32_t CIS22:1; /* Channel 22 Interrut Status */
2713	uint32_t CIS21:1; /* Channel 21 Interrut Status */
2714	uint32_t CIS20:1; /* Channel 20 Interrut Status */
2715	uint32_t CIS19:1; /* Channel 19 Interrut Status */
2716	uint32_t CIS18:1; /* Channel 18 Interrut Status */
2717	uint32_t CIS17:1; /* Channel 17 Interrut Status */
2718	uint32_t CIS16:1; /* Channel 16 Interrut Status */
2719	uint32_t CIS15:1; /* Channel 15 Interrut Status */
2720	uint32_t CIS14:1; /* Channel 14 Interrut Status */
2721	uint32_t CIS13:1; /* Channel 13 Interrut Status */
2722	uint32_t CIS12:1; /* Channel 12 Interrut Status */
2723	uint32_t CIS11:1; /* Channel 11 Interrut Status */
2724	uint32_t CIS10:1; /* Channel 10 Interrut Status */
2725	uint32_t CIS9:1; /* Channel 9 Interrut Status */
2726	uint32_t CIS8:1; /* Channel 8 Interrut Status */
2727	uint32_t CIS7:1; /* Channel 7 Interrut Status */
2728	uint32_t CIS6:1; /* Channel 6 Interrut Status */
2729	uint32_t CIS5:1; /* Channel 5 Interrut Status */
2730	uint32_t CIS4:1; /* Channel 4 Interrut Status */
2731	uint32_t CIS3:1; /* Channel 3 Interrut Status */
2732	uint32_t CIS2:1; /* Channel 2 Interrut Status */
2733	uint32_t CIS1:1; /* Channel 1 Interrupt Status */
2734	uint32_t CIS0:1; /* Channel 0 Interrupt Status */
2735	} B;
2736	} CISR_B;
2737
2738	uint32_t eTPU_reserved0208[2]; /* 0x0208-0x020F */
2739
2740	union { /* ETPU_A Data Transfer Request Status */
2741	uint32_t R;
2742	struct {
2743	uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
2744	uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
2745	uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
2746	uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
2747	uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
2748	uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
2749	uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
2750	uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
2751	uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
2752	uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
2753	uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
2754	uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
2755	uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
2756	uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
2757	uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
2758	uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
2759	uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
2760	uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
2761	uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
2762	uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
2763	uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
2764	uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
2765	uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
2766	uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
2767	uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
2768	uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
2769	uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
2770	uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
2771	uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
2772	uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
2773	uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
2774	uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
2775	} B;
2776	} CDTRSR_A;
2777
2778	union { /* ETPU_B Data Transfer Request Status */
2779	uint32_t R;
2780	struct {
2781	uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
2782	uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
2783	uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
2784	uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
2785	uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
2786	uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
2787	uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
2788	uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
2789	uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
2790	uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
2791	uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
2792	uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
2793	uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
2794	uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
2795	uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
2796	uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
2797	uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
2798	uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
2799	uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
2800	uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
2801	uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
2802	uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
2803	uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
2804	uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
2805	uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
2806	uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
2807	uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
2808	uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
2809	uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
2810	uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
2811	uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
2812	uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
2813	} B;
2814	} CDTRSR_B;
2815
2816	uint32_t eTPU_reserved0218[2]; /* 0x0218-0x021F */
2817
2818	union { /* ETPU_A Interruput Overflow Status */
2819	uint32_t R;
2820	struct {
2821	uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
2822	uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
2823	uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
2824	uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
2825	uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
2826	uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
2827	uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
2828	uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
2829	uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
2830	uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
2831	uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
2832	uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
2833	uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
2834	uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
2835	uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
2836	uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
2837	uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
2838	uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
2839	uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
2840	uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
2841	uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
2842	uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
2843	uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
2844	uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
2845	uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
2846	uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
2847	uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
2848	uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
2849	uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
2850	uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
2851	uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
2852	uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
2853	} B;
2854	} CIOSR_A;
2855
2856	union { /* ETPU_B Interruput Overflow Status */
2857	uint32_t R;
2858	struct {
2859	uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
2860	uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
2861	uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
2862	uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
2863	uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
2864	uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
2865	uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
2866	uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
2867	uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
2868	uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
2869	uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
2870	uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
2871	uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
2872	uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
2873	uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
2874	uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
2875	uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
2876	uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
2877	uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
2878	uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
2879	uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
2880	uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
2881	uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
2882	uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
2883	uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
2884	uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
2885	uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
2886	uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
2887	uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
2888	uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
2889	uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
2890	uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
2891	} B;
2892	} CIOSR_B;
2893
2894	uint32_t eTPU_reserved0228[2]; /* 0x0228-0x022F */
2895
2896	union { /* ETPU_A Data Transfer Overflow Status */
2897	uint32_t R;
2898	struct {
2899	uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
2900	uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
2901	uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
2902	uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
2903	uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
2904	uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
2905	uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
2906	uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
2907	uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
2908	uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
2909	uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
2910	uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
2911	uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
2912	uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
2913	uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
2914	uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
2915	uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
2916	uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
2917	uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
2918	uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
2919	uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
2920	uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
2921	uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
2922	uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
2923	uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
2924	uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
2925	uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
2926	uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
2927	uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
2928	uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
2929	uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
2930	uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
2931	} B;
2932	} CDTROSR_A;
2933
2934	union { /* ETPU_B Data Transfer Overflow Status */
2935	uint32_t R;
2936	struct {
2937	uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
2938	uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
2939	uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
2940	uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
2941	uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
2942	uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
2943	uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
2944	uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
2945	uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
2946	uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
2947	uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
2948	uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
2949	uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
2950	uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
2951	uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
2952	uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
2953	uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
2954	uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
2955	uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
2956	uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
2957	uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
2958	uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
2959	uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
2960	uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
2961	uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
2962	uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
2963	uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
2964	uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
2965	uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
2966	uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
2967	uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
2968	uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
2969	} B;
2970	} CDTROSR_B;
2971
2972	uint32_t eTPU_reserved0238[2]; /* 0x0238-0x023F */
2973
2974	union { /* ETPU_A Channel Interruput Enable */
2975	uint32_t R;
2976	struct {
2977	uint32_t CIE31:1; /* Channel 31 Interruput Enable */
2978	uint32_t CIE30:1; /* Channel 30 Interruput Enable */
2979	uint32_t CIE29:1; /* Channel 29 Interruput Enable */
2980	uint32_t CIE28:1; /* Channel 28 Interruput Enable */
2981	uint32_t CIE27:1; /* Channel 27 Interruput Enable */
2982	uint32_t CIE26:1; /* Channel 26 Interruput Enable */
2983	uint32_t CIE25:1; /* Channel 25 Interruput Enable */
2984	uint32_t CIE24:1; /* Channel 24 Interruput Enable */
2985	uint32_t CIE23:1; /* Channel 23 Interruput Enable */
2986	uint32_t CIE22:1; /* Channel 22 Interruput Enable */
2987	uint32_t CIE21:1; /* Channel 21 Interruput Enable */
2988	uint32_t CIE20:1; /* Channel 20 Interruput Enable */
2989	uint32_t CIE19:1; /* Channel 19 Interruput Enable */
2990	uint32_t CIE18:1; /* Channel 18 Interruput Enable */
2991	uint32_t CIE17:1; /* Channel 17 Interruput Enable */
2992	uint32_t CIE16:1; /* Channel 16 Interruput Enable */
2993	uint32_t CIE15:1; /* Channel 15 Interruput Enable */
2994	uint32_t CIE14:1; /* Channel 14 Interruput Enable */
2995	uint32_t CIE13:1; /* Channel 13 Interruput Enable */
2996	uint32_t CIE12:1; /* Channel 12 Interruput Enable */
2997	uint32_t CIE11:1; /* Channel 11 Interruput Enable */
2998	uint32_t CIE10:1; /* Channel 10 Interruput Enable */
2999	uint32_t CIE9:1; /* Channel 9 Interruput Enable */
3000	uint32_t CIE8:1; /* Channel 8 Interruput Enable */
3001	uint32_t CIE7:1; /* Channel 7 Interruput Enable */
3002	uint32_t CIE6:1; /* Channel 6 Interruput Enable */
3003	uint32_t CIE5:1; /* Channel 5 Interruput Enable */
3004	uint32_t CIE4:1; /* Channel 4 Interruput Enable */
3005	uint32_t CIE3:1; /* Channel 3 Interruput Enable */
3006	uint32_t CIE2:1; /* Channel 2 Interruput Enable */
3007	uint32_t CIE1:1; /* Channel 1 Interruput Enable */
3008	uint32_t CIE0:1; /* Channel 0 Interruput Enable */
3009	} B;
3010	} CIER_A;
3011
3012	union { /* ETPU_B Channel Interruput Enable */
3013	uint32_t R;
3014	struct {
3015	uint32_t CIE31:1; /* Channel 31 Interruput Enable */
3016	uint32_t CIE30:1; /* Channel 30 Interruput Enable */
3017	uint32_t CIE29:1; /* Channel 29 Interruput Enable */
3018	uint32_t CIE28:1; /* Channel 28 Interruput Enable */
3019	uint32_t CIE27:1; /* Channel 27 Interruput Enable */
3020	uint32_t CIE26:1; /* Channel 26 Interruput Enable */
3021	uint32_t CIE25:1; /* Channel 25 Interruput Enable */
3022	uint32_t CIE24:1; /* Channel 24 Interruput Enable */
3023	uint32_t CIE23:1; /* Channel 23 Interruput Enable */
3024	uint32_t CIE22:1; /* Channel 22 Interruput Enable */
3025	uint32_t CIE21:1; /* Channel 21 Interruput Enable */
3026	uint32_t CIE20:1; /* Channel 20 Interruput Enable */
3027	uint32_t CIE19:1; /* Channel 19 Interruput Enable */
3028	uint32_t CIE18:1; /* Channel 18 Interruput Enable */
3029	uint32_t CIE17:1; /* Channel 17 Interruput Enable */
3030	uint32_t CIE16:1; /* Channel 16 Interruput Enable */
3031	uint32_t CIE15:1; /* Channel 15 Interruput Enable */
3032	uint32_t CIE14:1; /* Channel 14 Interruput Enable */
3033	uint32_t CIE13:1; /* Channel 13 Interruput Enable */
3034	uint32_t CIE12:1; /* Channel 12 Interruput Enable */
3035	uint32_t CIE11:1; /* Channel 11 Interruput Enable */
3036	uint32_t CIE10:1; /* Channel 10 Interruput Enable */
3037	uint32_t CIE9:1; /* Channel 9 Interruput Enable */
3038	uint32_t CIE8:1; /* Channel 8 Interruput Enable */
3039	uint32_t CIE7:1; /* Channel 7 Interruput Enable */
3040	uint32_t CIE6:1; /* Channel 6 Interruput Enable */
3041	uint32_t CIE5:1; /* Channel 5 Interruput Enable */
3042	uint32_t CIE4:1; /* Channel 4 Interruput Enable */
3043	uint32_t CIE3:1; /* Channel 3 Interruput Enable */
3044	uint32_t CIE2:1; /* Channel 2 Interruput Enable */
3045	uint32_t CIE1:1; /* Channel 1 Interruput Enable */
3046	uint32_t CIE0:1; /* Channel 0 Interruput Enable */
3047	} B;
3048	} CIER_B;
3049
3050	uint32_t eTPU_reserved0248[2]; /* 0x0248-0x024F */
3051
3052	union { /* ETPU_A Channel Data Transfer Request Enable */
3053	uint32_t R;
3054	struct {
3055	uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
3056	uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
3057	uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
3058	uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
3059	uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
3060	uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
3061	uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
3062	uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
3063	uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
3064	uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
3065	uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
3066	uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
3067	uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
3068	uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
3069	uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
3070	uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
3071	uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
3072	uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
3073	uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
3074	uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
3075	uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
3076	uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
3077	uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
3078	uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
3079	uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
3080	uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
3081	uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
3082	uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
3083	uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
3084	uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
3085	uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
3086	uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
3087	} B;
3088	} CDTRER_A;
3089
3090	union { /* ETPU_B Channel Data Transfer Request Enable */
3091	uint32_t R;
3092	struct {
3093	uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
3094	uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
3095	uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
3096	uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
3097	uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
3098	uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
3099	uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
3100	uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
3101	uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
3102	uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
3103	uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
3104	uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
3105	uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
3106	uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
3107	uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
3108	uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
3109	uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
3110	uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
3111	uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
3112	uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
3113	uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
3114	uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
3115	uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
3116	uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
3117	uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
3118	uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
3119	uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
3120	uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
3121	uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
3122	uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
3123	uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
3124	uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
3125	} B;
3126	} CDTRER_B;
3127
3128	uint32_t eTPU_reserved0258[2]; /* 0x0258-0x025F */
3129
3130	union { /* Watchdog Status Register A */
3131	uint32_t R;
3132	struct {
3133	uint32_t WDS31:1;
3134	uint32_t WDS30:1;
3135	uint32_t WDS29:1;
3136	uint32_t WDS28:1;
3137	uint32_t WDS27:1;
3138	uint32_t WDS26:1;
3139	uint32_t WDS25:1;
3140	uint32_t WDS24:1;
3141	uint32_t WDS23:1;
3142	uint32_t WDS22:1;
3143	uint32_t WDS21:1;
3144	uint32_t WDS20:1;
3145	uint32_t WDS19:1;
3146	uint32_t WDS18:1;
3147	uint32_t WDS17:1;
3148	uint32_t WDS16:1;
3149	uint32_t WDS15:1;
3150	uint32_t WDS14:1;
3151	uint32_t WDS13:1;
3152	uint32_t WDS12:1;
3153	uint32_t WDS11:1;
3154	uint32_t WDS10:1;
3155	uint32_t WDS9:1;
3156	uint32_t WDS8:1;
3157	uint32_t WDS7:1;
3158	uint32_t WDS6:1;
3159	uint32_t WDS5:1;
3160	uint32_t WDS4:1;
3161	uint32_t WDS3:1;
3162	uint32_t WDS2:1;
3163	uint32_t WDS1:1;
3164	uint32_t WDS0:1;
3165	} B;
3166	} WDSR_A;
3167
3168	union { /* Watchdog Status Register B */
3169	uint32_t R;
3170	struct {
3171	uint32_t WDS31:1;
3172	uint32_t WDS30:1;
3173	uint32_t WDS29:1;
3174	uint32_t WDS28:1;
3175	uint32_t WDS27:1;
3176	uint32_t WDS26:1;
3177	uint32_t WDS25:1;
3178	uint32_t WDS24:1;
3179	uint32_t WDS23:1;
3180	uint32_t WDS22:1;
3181	uint32_t WDS21:1;
3182	uint32_t WDS20:1;
3183	uint32_t WDS19:1;
3184	uint32_t WDS18:1;
3185	uint32_t WDS17:1;
3186	uint32_t WDS16:1;
3187	uint32_t WDS15:1;
3188	uint32_t WDS14:1;
3189	uint32_t WDS13:1;
3190	uint32_t WDS12:1;
3191	uint32_t WDS11:1;
3192	uint32_t WDS10:1;
3193	uint32_t WDS9:1;
3194	uint32_t WDS8:1;
3195	uint32_t WDS7:1;
3196	uint32_t WDS6:1;
3197	uint32_t WDS5:1;
3198	uint32_t WDS4:1;
3199	uint32_t WDS3:1;
3200	uint32_t WDS2:1;
3201	uint32_t WDS1:1;
3202	uint32_t WDS0:1;
3203	} B;
3204	} WDSR_B;
3205
3206	uint32_t eTPU_reserved0268[6]; /* 0x0268-0x027F */
3207
3208	union { /* ETPU_A Channel Pending Service Status */
3209	uint32_t R;
3210	struct {
3211	uint32_t SR31:1; /* Channel 31 Pending Service Status */
3212	uint32_t SR30:1; /* Channel 30 Pending Service Status */
3213	uint32_t SR29:1; /* Channel 29 Pending Service Status */
3214	uint32_t SR28:1; /* Channel 28 Pending Service Status */
3215	uint32_t SR27:1; /* Channel 27 Pending Service Status */
3216	uint32_t SR26:1; /* Channel 26 Pending Service Status */
3217	uint32_t SR25:1; /* Channel 25 Pending Service Status */
3218	uint32_t SR24:1; /* Channel 24 Pending Service Status */
3219	uint32_t SR23:1; /* Channel 23 Pending Service Status */
3220	uint32_t SR22:1; /* Channel 22 Pending Service Status */
3221	uint32_t SR21:1; /* Channel 21 Pending Service Status */
3222	uint32_t SR20:1; /* Channel 20 Pending Service Status */
3223	uint32_t SR19:1; /* Channel 19 Pending Service Status */
3224	uint32_t SR18:1; /* Channel 18 Pending Service Status */
3225	uint32_t SR17:1; /* Channel 17 Pending Service Status */
3226	uint32_t SR16:1; /* Channel 16 Pending Service Status */
3227	uint32_t SR15:1; /* Channel 15 Pending Service Status */
3228	uint32_t SR14:1; /* Channel 14 Pending Service Status */
3229	uint32_t SR13:1; /* Channel 13 Pending Service Status */
3230	uint32_t SR12:1; /* Channel 12 Pending Service Status */
3231	uint32_t SR11:1; /* Channel 11 Pending Service Status */
3232	uint32_t SR10:1; /* Channel 10 Pending Service Status */
3233	uint32_t SR9:1; /* Channel 9 Pending Service Status */
3234	uint32_t SR8:1; /* Channel 8 Pending Service Status */
3235	uint32_t SR7:1; /* Channel 7 Pending Service Status */
3236	uint32_t SR6:1; /* Channel 6 Pending Service Status */
3237	uint32_t SR5:1; /* Channel 5 Pending Service Status */
3238	uint32_t SR4:1; /* Channel 4 Pending Service Status */
3239	uint32_t SR3:1; /* Channel 3 Pending Service Status */
3240	uint32_t SR2:1; /* Channel 2 Pending Service Status */
3241	uint32_t SR1:1; /* Channel 1 Pending Service Status */
3242	uint32_t SR0:1; /* Channel 0 Pending Service Status */
3243	} B;
3244	} CPSSR_A;
3245
3246	union { /* ETPU_B Channel Pending Service Status */
3247	uint32_t R;
3248	struct {
3249	uint32_t SR31:1; /* Channel 31 Pending Service Status */
3250	uint32_t SR30:1; /* Channel 30 Pending Service Status */
3251	uint32_t SR29:1; /* Channel 29 Pending Service Status */
3252	uint32_t SR28:1; /* Channel 28 Pending Service Status */
3253	uint32_t SR27:1; /* Channel 27 Pending Service Status */
3254	uint32_t SR26:1; /* Channel 26 Pending Service Status */
3255	uint32_t SR25:1; /* Channel 25 Pending Service Status */
3256	uint32_t SR24:1; /* Channel 24 Pending Service Status */
3257	uint32_t SR23:1; /* Channel 23 Pending Service Status */
3258	uint32_t SR22:1; /* Channel 22 Pending Service Status */
3259	uint32_t SR21:1; /* Channel 21 Pending Service Status */
3260	uint32_t SR20:1; /* Channel 20 Pending Service Status */
3261	uint32_t SR19:1; /* Channel 19 Pending Service Status */
3262	uint32_t SR18:1; /* Channel 18 Pending Service Status */
3263	uint32_t SR17:1; /* Channel 17 Pending Service Status */
3264	uint32_t SR16:1; /* Channel 16 Pending Service Status */
3265	uint32_t SR15:1; /* Channel 15 Pending Service Status */
3266	uint32_t SR14:1; /* Channel 14 Pending Service Status */
3267	uint32_t SR13:1; /* Channel 13 Pending Service Status */
3268	uint32_t SR12:1; /* Channel 12 Pending Service Status */
3269	uint32_t SR11:1; /* Channel 11 Pending Service Status */
3270	uint32_t SR10:1; /* Channel 10 Pending Service Status */
3271	uint32_t SR9:1; /* Channel 9 Pending Service Status */
3272	uint32_t SR8:1; /* Channel 8 Pending Service Status */
3273	uint32_t SR7:1; /* Channel 7 Pending Service Status */
3274	uint32_t SR6:1; /* Channel 6 Pending Service Status */
3275	uint32_t SR5:1; /* Channel 5 Pending Service Status */
3276	uint32_t SR4:1; /* Channel 4 Pending Service Status */
3277	uint32_t SR3:1; /* Channel 3 Pending Service Status */
3278	uint32_t SR2:1; /* Channel 2 Pending Service Status */
3279	uint32_t SR1:1; /* Channel 1 Pending Service Status */
3280	uint32_t SR0:1; /* Channel 0 Pending Service Status */
3281	} B;
3282	} CPSSR_B;
3283
3284	uint32_t eTPU_reserved0288[2]; /* 0x0288-0x028F */
3285
3286	union { /* ETPU_A Channel Service Status */
3287	uint32_t R;
3288	struct {
3289	uint32_t SS31:1; /* Channel 31 Service Status */
3290	uint32_t SS30:1; /* Channel 30 Service Status */
3291	uint32_t SS29:1; /* Channel 29 Service Status */
3292	uint32_t SS28:1; /* Channel 28 Service Status */
3293	uint32_t SS27:1; /* Channel 27 Service Status */
3294	uint32_t SS26:1; /* Channel 26 Service Status */
3295	uint32_t SS25:1; /* Channel 25 Service Status */
3296	uint32_t SS24:1; /* Channel 24 Service Status */
3297	uint32_t SS23:1; /* Channel 23 Service Status */
3298	uint32_t SS22:1; /* Channel 22 Service Status */
3299	uint32_t SS21:1; /* Channel 21 Service Status */
3300	uint32_t SS20:1; /* Channel 20 Service Status */
3301	uint32_t SS19:1; /* Channel 19 Service Status */
3302	uint32_t SS18:1; /* Channel 18 Service Status */
3303	uint32_t SS17:1; /* Channel 17 Service Status */
3304	uint32_t SS16:1; /* Channel 16 Service Status */
3305	uint32_t SS15:1; /* Channel 15 Service Status */
3306	uint32_t SS14:1; /* Channel 14 Service Status */
3307	uint32_t SS13:1; /* Channel 13 Service Status */
3308	uint32_t SS12:1; /* Channel 12 Service Status */
3309	uint32_t SS11:1; /* Channel 11 Service Status */
3310	uint32_t SS10:1; /* Channel 10 Service Status */
3311	uint32_t SS9:1; /* Channel 9 Service Status */
3312	uint32_t SS8:1; /* Channel 8 Service Status */
3313	uint32_t SS7:1; /* Channel 7 Service Status */
3314	uint32_t SS6:1; /* Channel 6 Service Status */
3315	uint32_t SS5:1; /* Channel 5 Service Status */
3316	uint32_t SS4:1; /* Channel 4 Service Status */
3317	uint32_t SS3:1; /* Channel 3 Service Status */
3318	uint32_t SS2:1; /* Channel 2 Service Status */
3319	uint32_t SS1:1; /* Channel 1 Service Status */
3320	uint32_t SS0:1; /* Channel 0 Service Status */
3321	} B;
3322	} CSSR_A;
3323
3324	union { /* ETPU_B Channel Service Status */
3325	uint32_t R;
3326	struct {
3327	uint32_t SS31:1; /* Channel 31 Service Status */
3328	uint32_t SS30:1; /* Channel 30 Service Status */
3329	uint32_t SS29:1; /* Channel 29 Service Status */
3330	uint32_t SS28:1; /* Channel 28 Service Status */
3331	uint32_t SS27:1; /* Channel 27 Service Status */
3332	uint32_t SS26:1; /* Channel 26 Service Status */
3333	uint32_t SS25:1; /* Channel 25 Service Status */
3334	uint32_t SS24:1; /* Channel 24 Service Status */
3335	uint32_t SS23:1; /* Channel 23 Service Status */
3336	uint32_t SS22:1; /* Channel 22 Service Status */
3337	uint32_t SS21:1; /* Channel 21 Service Status */
3338	uint32_t SS20:1; /* Channel 20 Service Status */
3339	uint32_t SS19:1; /* Channel 19 Service Status */
3340	uint32_t SS18:1; /* Channel 18 Service Status */
3341	uint32_t SS17:1; /* Channel 17 Service Status */
3342	uint32_t SS16:1; /* Channel 16 Service Status */
3343	uint32_t SS15:1; /* Channel 15 Service Status */
3344	uint32_t SS14:1; /* Channel 14 Service Status */
3345	uint32_t SS13:1; /* Channel 13 Service Status */
3346	uint32_t SS12:1; /* Channel 12 Service Status */
3347	uint32_t SS11:1; /* Channel 11 Service Status */
3348	uint32_t SS10:1; /* Channel 10 Service Status */
3349	uint32_t SS9:1; /* Channel 9 Service Status */
3350	uint32_t SS8:1; /* Channel 8 Service Status */
3351	uint32_t SS7:1; /* Channel 7 Service Status */
3352	uint32_t SS6:1; /* Channel 6 Service Status */
3353	uint32_t SS5:1; /* Channel 5 Service Status */
3354	uint32_t SS4:1; /* Channel 4 Service Status */
3355	uint32_t SS3:1; /* Channel 3 Service Status */
3356	uint32_t SS2:1; /* Channel 2 Service Status */
3357	uint32_t SS1:1; /* Channel 1 Service Status */
3358	uint32_t SS0:1; /* Channel 0 Service Status */
3359	} B;
3360	} CSSR_B;
3361
3362	uint32_t eTPU_reserved0298[2]; /* 0x0298-0x029F */
3363
3364	uint32_t eTPU_reserved02A0[88]; /* 0x02A0-0x03FF */
3365
3366	/***************************Channels******************************/
3367
3368	struct {
3369	union { /* Channel Configuration Register */
3370	uint32_t R;
3371	struct {
3372	uint32_t CIE:1; /* Channel Interruput Enable */
3373	uint32_t DTRE:1; /* Data Transfer Request Enable */
3374	uint32_t CPR:2; /* Channel Priority */
3375	uint32_t:2;
3376	uint32_t ETPD:1;
3377	uint32_t ETCS:1; /* Entry Table Condition Select */
3378	uint32_t:3;
3379	uint32_t CFS:5; /* Channel Function Select */
3380	uint32_t ODIS:1; /* Output disable */
3381	uint32_t OPOL:1; /* output polarity */
3382	uint32_t:3;
3383	uint32_t CPBA:11; /* Channel Parameter Base Address */
3384	} B;
3385	} CR;
3386
3387	union { /* Channel Status Control Register */
3388	uint32_t R;
3389	struct {
3390	uint32_t CIS:1; /* Channel Interruput Status */
3391	uint32_t CIOS:1; /* Channel Interruput Overflow Status */
3392	uint32_t:6;
3393	uint32_t DTRS:1; /* Data Transfer Status */
3394	uint32_t DTROS:1; /* Data Transfer Overflow Status */
3395	uint32_t:6;
3396	uint32_t IPS:1; /* Input Pin State */
3397	uint32_t OPS:1; /* Output Pin State */
3398	uint32_t OBE:1; /* Output Buffer Enable */
3399	uint32_t:11;
3400	uint32_t FM1:1; /* Function mode */
3401	uint32_t FM0:1; /* Function mode */
3402	} B;
3403	} SCR;
3404
3405	union { /* Channel Host Service Request Register */
3406	uint32_t R;
3407	struct {
3408	uint32_t:29; /* Host Service Request */
3409	uint32_t HSR:3;
3410	} B;
3411	} HSRR;
3412
3413	uint32_t eTPU_ch_reserved00C; /* channel offset 0x00C-0x00F */
3414
3415	} CHAN[127];
3416
3417	uint32_t eTPU_reserved1000[7168]; /* 0x1000-0x7FFF */
3418
3419	};
3420
3421	/****************************************************************************/
3422	/* MODULE : PIT / RTI */
3423	/****************************************************************************/
3424
3425	struct PIT_tag {
3426	union { /* Module Configuration Register */
3427	uint32_t R;
3428	struct {
3429	uint32_t:29;
3430	uint32_t MDIS_RTI:1;
3431	uint32_t MDIS:1;
3432	uint32_t FRZ:1;
3433	} B;
3434	} MCR;
3435
3436	uint32_t PIT_reserved0004[59]; /* 0x0004-0x00EF */
3437
3438	struct {
3439	union {
3440	uint32_t R; /* <URM>TSVn</URM> */
3441	} LDVAL; /* Timer Load Value Register */
3442
3443	union {
3444	uint32_t R; /* <URM>TVLn</URM> */
3445	} CVAL; /* Current Timer Value Register */
3446
3447	union {
3448	uint32_t R;
3449	struct {
3450	uint32_t:30;
3451	uint32_t TIE:1;
3452	uint32_t TEN:1;
3453	} B;
3454	} TCTRL; /* Timer Control Register */
3455
3456	union {
3457	uint32_t R;
3458	struct {
3459	uint32_t:31;
3460	uint32_t TIF:1;
3461	} B;
3462	} TFLG; /* Timer Flag Register */
3463	} RTI; /* RTI Channel */
3464
3465	struct {
3466	union {
3467	uint32_t R;
3468	struct {
3469	uint32_t TSV:32;
3470	} B;
3471	} LDVAL;
3472
3473	union {
3474	uint32_t R;
3475	struct {
3476	uint32_t TVL:32;
3477	} B;
3478	} CVAL;
3479
3480	union {
3481	uint32_t R;
3482	struct {
3483	uint32_t:30;
3484	uint32_t TIE:1;
3485	uint32_t TEN:1;
3486	} B;
3487	} TCTRL;
3488
3489	union {
3490	uint32_t R;
3491	struct {
3492	uint32_t:31;
3493	uint32_t TIF:1;
3494	} B;
3495	} TFLG;
3496	} CH[4];
3497
3498	uint32_t PIT_reserved00140[4016]; /* 0x0140-0x3FFF */
3499	};
3500
3501	/****************************************************************************/
3502	/* MODULE : XBAR CrossBar */
3503	/****************************************************************************/
3504
3505	struct XBAR_tag {
3506
3507	union { /* Master Priority Register for Slave Port 0 */
3508	uint32_t R;
3509	struct {
3510	uint32_t:1;
3511	uint32_t MSTR7:3; /* EBI (development bus) */
3512	uint32_t:1;
3513	uint32_t MSTR6:3; /* FlexRay */
3514	uint32_t:1;
3515	uint32_t MSTR5:3; /* eDMA_B */
3516	uint32_t:1;
3517	uint32_t MSTR4:3; /* eDMA_A */
3518	uint32_t:1;
3519	uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3520	uint32_t:1;
3521	uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3522	uint32_t:1;
3523	uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3524	uint32_t:1;
3525	uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3526	} B;
3527	} MPR0;
3528
3529	uint32_t XBAR_reserved0004[3]; /* 0x0004-0x000F */
3530
3531	union { /* General Purpose Control Register for Slave Port 0 */
3532	uint32_t R;
3533	struct {
3534	uint32_t RO:1;
3535	uint32_t:21;
3536	uint32_t ARB:2;
3537	uint32_t:2;
3538	uint32_t PCTL:2;
3539	uint32_t:1;
3540	uint32_t PARK:3;
3541	} B;
3542	} SGPCR0;
3543
3544	uint32_t XBAR_reserved0014[59]; /* 0x0014-0x00FF */
3545
3546	union { /* Master Priority Register for Slave Port 1 */
3547	uint32_t R;
3548	struct {
3549	uint32_t:1;
3550	uint32_t MSTR7:3; /* EBI (development bus) */
3551	uint32_t:1;
3552	uint32_t MSTR6:3; /* FlexRay */
3553	uint32_t:1;
3554	uint32_t MSTR5:3; /* eDMA_B */
3555	uint32_t:1;
3556	uint32_t MSTR4:3; /* eDMA_A */
3557	uint32_t:1;
3558	uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3559	uint32_t:1;
3560	uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3561	uint32_t:1;
3562	uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3563	uint32_t:1;
3564	uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3565	} B;
3566	} MPR1;
3567
3568	uint32_t XBAR_reserved0104[3]; /* 0x0104-0x010F */
3569
3570	union { /* General Purpose Control Register for Slave Port 1 */
3571	uint32_t R;
3572	struct {
3573	uint32_t RO:1;
3574	uint32_t:21;
3575	uint32_t ARB:2;
3576	uint32_t:2;
3577	uint32_t PCTL:2;
3578	uint32_t:1;
3579	uint32_t PARK:3;
3580	} B;
3581	} SGPCR1;
3582
3583	uint32_t XBAR_reserved0114[59]; /* 0x0114-0x01FF */
3584
3585	union { /* Master Priority Register for Slave Port 2 */
3586	uint32_t R;
3587	struct {
3588	uint32_t:1;
3589	uint32_t MSTR7:3; /* EBI (development bus) */
3590	uint32_t:1;
3591	uint32_t MSTR6:3; /* FlexRay */
3592	uint32_t:1;
3593	uint32_t MSTR5:3; /* eDMA_B */
3594	uint32_t:1;
3595	uint32_t MSTR4:3; /* eDMA_A */
3596	uint32_t:1;
3597	uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3598	uint32_t:1;
3599	uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3600	uint32_t:1;
3601	uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3602	uint32_t:1;
3603	uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3604	} B;
3605	} MPR2;
3606
3607	uint32_t XBAR_reserved0204[3]; /* 0x0204-0x020F */
3608
3609	union { /* General Purpose Control Register for Slave Port 2 */
3610	uint32_t R;
3611	struct {
3612	uint32_t RO:1;
3613	uint32_t:21;
3614	uint32_t ARB:2;
3615	uint32_t:2;
3616	uint32_t PCTL:2;
3617	uint32_t:1;
3618	uint32_t PARK:3;
3619	} B;
3620	} SGPCR2;
3621
3622	uint32_t XBAR_reserved0214[59]; /* 0x0214-0x02FF */
3623
3624	uint32_t XBAR_reserved0300[64]; /* 0x0300-0x03FF */
3625
3626	uint32_t XBAR_reserved0400[64]; /* 0x0400-0x04FF */
3627
3628	uint32_t XBAR_reserved0500[64]; /* 0x0500-0x05FF */
3629
3630	union { /* Master Priority Register for Slave Port 6 */
3631	uint32_t R;
3632	struct {
3633	uint32_t:1;
3634	uint32_t MSTR7:3; /* EBI (development bus) */
3635	uint32_t:1;
3636	uint32_t MSTR6:3; /* FlexRay */
3637	uint32_t:1;
3638	uint32_t MSTR5:3; /* eDMA_B */
3639	uint32_t:1;
3640	uint32_t MSTR4:3; /* eDMA_A */
3641	uint32_t:1;
3642	uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3643	uint32_t:1;
3644	uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3645	uint32_t:1;
3646	uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3647	uint32_t:1;
3648	uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3649	} B;
3650	} MPR6;
3651
3652	uint32_t XBAR_reserved604[3]; /* 0x0604-0x060F */
3653
3654	union { /* General Purpose Control Register for Slave Port 6 */
3655	uint32_t R;
3656	struct {
3657	uint32_t RO:1;
3658	uint32_t:21;
3659	uint32_t ARB:2;
3660	uint32_t:2;
3661	uint32_t PCTL:2;
3662	uint32_t:1;
3663	uint32_t PARK:3;
3664	} B;
3665	} SGPCR6;
3666
3667	uint32_t XBAR_reserved0614[59]; /* 0x0614-0x06FF */
3668
3669	union { /* Master Priority Register for Slave Port 7 */
3670	uint32_t R;
3671	struct {
3672	uint32_t:1;
3673	uint32_t MSTR7:3; /* EBI (development bus) */
3674	uint32_t:1;
3675	uint32_t MSTR6:3; /* FlexRay */
3676	uint32_t:1;
3677	uint32_t MSTR5:3; /* eDMA_B */
3678	uint32_t:1;
3679	uint32_t MSTR4:3; /* eDMA_A */
3680	uint32_t:1;
3681	uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3682	uint32_t:1;
3683	uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3684	uint32_t:1;
3685	uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3686	uint32_t:1;
3687	uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3688	} B;
3689	} MPR7;
3690
3691	uint32_t XBAR_reserved704[3]; /* 0x0704-0x070F */
3692
3693	union {
3694	uint32_t R;
3695	struct {
3696	uint32_t RO:1;
3697	uint32_t:21;
3698	uint32_t ARB:2;
3699	uint32_t:2;
3700	uint32_t PCTL:2;
3701	uint32_t:1;
3702	uint32_t PARK:3;
3703	} B;
3704	} SGPCR7; /* General Purpose Control Register for Slave Port 7 */
3705
3706	uint32_t XBAR_reserved0714[59]; /* 0x0714-0x07FF */
3707
3708	uint32_t XBAR_reserved0800[3584]; /* 0x0800-0x3FFF */
3709	};
3710
3711	/****************************************************************************/
3712	/* MODULE : MPU */
3713	/****************************************************************************/
3714
3715	struct MPU_tag {
3716
3717	union { /* Module Control/Error Status Register */
3718	uint32_t R;
3719	struct {
3720	uint32_t SPERR:8;
3721	uint32_t:4;
3722	uint32_t HRL:4;
3723	uint32_t NSP:4;
3724	uint32_t NRGD:4;
3725	uint32_t:7;
3726	uint32_t VLD:1;
3727	} B;
3728	} CESR;
3729
3730	uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */
3731
3732	struct {
3733	union { /* MPU Error Address Registers */
3734	uint32_t R;
3735	struct {
3736	uint32_t EADDR:32;
3737	} B;
3738	} EAR;
3739
3740	union { /* MPU Error Detail Registers */
3741	uint32_t R;
3742	struct {
3743	uint32_t EACD:16;
3744	uint32_t EPID:8;
3745	uint32_t EMN:4;
3746	uint32_t EATTR:3;
3747	uint32_t ERW:1;
3748	} B;
3749	} EDR;
3750	} PORT[3];
3751
3752	uint32_t MPU_reserved0028[246]; /* 0x0028-0x03FF */
3753
3754	struct {
3755	union { /* Region Descriptor n Word 0 */
3756	uint32_t R;
3757	struct {
3758	uint32_t SRTADDR:27;
3759	uint32_t:5;
3760	} B;
3761	} WORD0;
3762
3763	union { /* Region Descriptor n Word 1 */
3764	uint32_t R;
3765	struct {
3766	uint32_t ENDADDR:27;
3767	uint32_t:5;
3768	} B;
3769	} WORD1;
3770
3771	union { /* Region Descriptor n Word 2 */
3772	uint32_t R;
3773	struct {
3774	uint32_t M7RE:1;
3775	uint32_t M7WE:1;
3776	uint32_t M6RE:1;
3777	uint32_t M6WE:1;
3778	uint32_t M5RE:1;
3779	uint32_t M5WE:1;
3780	uint32_t M4RE:1;
3781	uint32_t M4WE:1;
3782	uint32_t: 18;
3783	uint32_t M0PE:1;
3784	uint32_t M0SM:2;
3785	uint32_t M0UM:3;
3786	} B;
3787	} WORD2;
3788
3789	union { /* Region Descriptor n Word 3 */
3790	uint32_t R;
3791	struct {
3792	uint32_t PID:8;
3793	uint32_t PIDMASK:8;
3794	uint32_t:15;
3795	uint32_t VLD:1;
3796	} B;
3797	} WORD3;
3798	} RGD[16];
3799
3800	uint32_t MPU_reserved0500[192]; /* 0x0500-0x07FF */
3801
3802	union { /* Region Descriptor Alternate Access Control n */
3803	uint32_t R;
3804	struct {
3805	uint32_t:6;
3806	uint32_t M4RE:1;
3807	uint32_t M4WE:1;
3808	uint32_t M3PE:1;
3809	uint32_t M3SM:2;
3810	uint32_t M3UM:3;
3811	uint32_t M2PE:1;
3812	uint32_t M2SM:2;
3813	uint32_t M2UM:3;
3814	uint32_t M1PE:1;
3815	uint32_t M1SM:2;
3816	uint32_t M1UM:3;
3817	uint32_t M0PE:1;
3818	uint32_t M0SM:2;
3819	uint32_t M0UM:3;
3820	} B;
3821	} RGDAAC[16];
3822
3823	uint32_t MPU_reserved0840[3568]; /* 0x0840-0x3FFF */
3824
3825	};
3826
3827	/****************************************************************************/
3828	/* MODULE : SWT */
3829	/****************************************************************************/
3830
3831	struct SWT_tag {
3832
3833	union { /* Module Configuration Register */
3834	uint32_t R;
3835	struct {
3836	uint32_t MAP0:1;
3837	uint32_t MAP1:1;
3838	uint32_t:1;
3839	uint32_t:1;
3840	uint32_t MAP4:1;
3841	uint32_t MAP5:1;
3842	uint32_t MAP6:1;
3843	uint32_t MAP7:1;
3844	uint32_t:14;
3845	uint32_t KEY:1;
3846	uint32_t RIA:1;
3847	uint32_t WND:1;
3848	uint32_t ITR:1;
3849	uint32_t HLK:1;
3850	uint32_t SLK:1;
3851	uint32_t CSL:1;
3852	uint32_t STP:1;
3853	uint32_t FRZ:1;
3854	uint32_t WEN:1;
3855	} B;
3856	} MCR;
3857
3858	union { /* Interrupt register */
3859	uint32_t R;
3860	struct {
3861	uint32_t :31;
3862	uint32_t TIF:1;
3863	} B;
3864	} IR;
3865
3866	union { /* Timeout register */
3867	uint32_t R;
3868	struct {
3869	uint32_t WTO:32;
3870	} B;
3871	} TO;
3872
3873	union { /* Window register */
3874	uint32_t R;
3875	struct {
3876	uint32_t WST:32;
3877	} B;
3878	} WN;
3879
3880	union { /* Service register */
3881	uint32_t R;
3882	struct {
3883	uint32_t :16;
3884	uint32_t WSC:16;
3885	} B;
3886	} SR;
3887
3888	union { /* Counter output register */
3889	uint32_t R;
3890	struct {
3891	uint32_t CNT:32;
3892	} B;
3893	} CO;
3894
3895	union { /* Service key register */
3896	uint32_t R;
3897	struct {
3898	uint32_t :16;
3899	uint32_t SK:16;
3900	} B;
3901	} SK;
3902
3903	uint32_t SWT_reserved001C[4089]; /* 0x001C-0x3FFF */
3904
3905	};
3906
3907	/****************************************************************************/
3908	/* MODULE : STM */
3909	/****************************************************************************/
3910
3911	struct STM_tag {
3912
3913	union { /* Control Register */
3914	uint32_t R;
3915	struct {
3916	uint32_t :16;
3917	uint32_t CPS:8;
3918	uint32_t :6;
3919	uint32_t FRZ:1;
3920	uint32_t TEN:1;
3921	} B;
3922	} CR;
3923
3924	union { /* STM Counter */
3925	uint32_t R;
3926	} CNT;
3927
3928	uint32_t STM_reserved0008[2]; /* 0x0008-0x000F */
3929
3930	/* channel 0 registers */
3931	union {
3932	uint32_t R;
3933	struct {
3934	uint32_t :31;
3935	uint32_t CEN:1;
3936	} B;
3937	} CCR0; /* Chan 0 Control Register */
3938
3939	union {
3940	uint32_t R;
3941	struct {
3942	uint32_t :31;
3943	uint32_t CIF:1;
3944	} B;
3945	} CIR0; /* Chan 0 Interrupt Register */
3946
3947	union {
3948	uint32_t R;
3949	} CMP0; /* Chan 0 Compare Register */
3950
3951	uint32_t STM_reserved2[1];
3952
3953	/* channel 1 registers */
3954	union {
3955	uint32_t R;
3956	struct {
3957	uint32_t :31;
3958	uint32_t CEN:1;
3959	} B;
3960	} CCR1; /* Chan 1 Control Register */
3961
3962	union {
3963	uint32_t R;
3964	struct {
3965	uint32_t :31;
3966	uint32_t CIF:1;
3967	} B;
3968	} CIR1; /* Chan 1 Interrupt Register */
3969
3970	union {
3971	uint32_t R;
3972	} CMP1; /* Chan 1 Compare Register */
3973
3974	uint32_t STM_reserved3[1];
3975
3976	/* channel 2 registers */
3977	union {
3978	uint32_t R;
3979	struct {
3980	uint32_t :31;
3981	uint32_t CEN:1;
3982	} B;
3983	} CCR2; /* Chan 2 Control Register */
3984
3985	union {
3986	uint32_t R;
3987	struct {
3988	uint32_t :31;
3989	uint32_t CIF:1;
3990	} B;
3991	} CIR2; /* Chan 2 Interrupt Register */
3992
3993	union {
3994	uint32_t R;
3995	} CMP2; /* Chan 2 Compare Register */
3996
3997	uint32_t STM_reserved4[1];
3998
3999	/* channel 3 registers */
4000	union {
4001	uint32_t R;
4002	struct {
4003	uint32_t :31;
4004	uint32_t CEN:1;
4005	} B;
4006	} CCR3; /* Chan 3 Control Register */
4007
4008	union {
4009	uint32_t R;
4010	struct {
4011	uint32_t :31;
4012	uint32_t CIF:1;
4013	} B;
4014	} CIR3; /* Chan 3 Interrupt Register */
4015
4016	union {
4017	uint32_t R;
4018	} CMP3; /* Chan 3 Compare Register */
4019
4020	uint32_t STM_reserved0050[4076]; /* 0x0050-0x3FFF */
4021
4022	};
4023
4024	/****************************************************************************/
4025	/* MODULE : ECSM */
4026	/****************************************************************************/
4027
4028	struct ECSM_tag {
4029
4030	union { /* Processor core type */
4031	uint16_t R;
4032	} PCT;
4033
4034	union { /* Platform revision */
4035	uint16_t R;
4036	} REV;
4037
4038	uint32_t ECSM_reserved0004; /* 0x0004-0x0007 */
4039
4040	union { /* IPS Module Configuration */
4041	uint32_t R;
4042	} IMC;
4043
4044	uint8_t ECSM_reserved000C[3]; /* 0x000C-0x000E */
4045
4046	union { /* Miscellaneous Reset Status Register */
4047	uint8_t R;
4048	struct {
4049	uint8_t POR:1;
4050	uint8_t DIR:1;
4051	uint8_t SWTR:1;
4052	uint8_t:5;
4053	} B;
4054	} MRSR;
4055
4056	uint8_t ECSM_reserved0010[51]; /* 0x0010-0x0042 */
4057
4058	union { /* ECC Configuration Register */
4059	uint8_t R;
4060	struct {
4061	uint8_t:2;
4062	uint8_t ER1BR:1;
4063	uint8_t EF1BR:1;
4064	uint8_t:2;
4065	uint8_t ERNCR:1;
4066	uint8_t EFNCR:1;
4067	} B;
4068	} ECR;
4069
4070	uint8_t ECSM_reserved0044[3]; /* 0x0044-0x0046 */
4071
4072	union { /* ECC Status Register */
4073	uint8_t R;
4074	struct {
4075	uint8_t:2;
4076	uint8_t R1BC:1;
4077	uint8_t F1BC:1;
4078	uint8_t:2;
4079	uint8_t RNCE:1;
4080	uint8_t FNCE:1;
4081	} B;
4082	} ESR;
4083
4084	uint16_t ECSM_reserved0048; /* 0x0048-0x0049 */
4085
4086	union { /* ECC Error Generation Register */
4087	uint16_t R;
4088	struct {
4089	uint16_t:2;
4090	uint16_t FRC1BI:1;
4091	uint16_t FR11BI:1;
4092	uint16_t:2;
4093	uint16_t FRCNCI:1;
4094	uint16_t FR1NCI:1;
4095	uint16_t:1;
4096	uint16_t ERRBIT:7;
4097	} B;
4098	} EEGR;
4099
4100	uint32_t ECSM_reserved004C; /* 0x004C-0x004F */
4101
4102	union { /* Flash ECC Address Register */
4103	uint32_t R;
4104	struct {
4105	uint32_t FEAR:32;
4106	} B;
4107	} FEAR;
4108
4109	uint16_t ECSM_reserved0054; /* 0x0054-0x0055 */
4110
4111	union { /* Flash ECC Master Number Register */
4112	uint8_t R;
4113	struct {
4114	uint8_t:4;
4115	uint8_t FEMR:4;
4116	} B;
4117	} FEMR;
4118
4119	union { /* Flash ECC Attributes Register */
4120	uint8_t R;
4121	struct {
4122	uint8_t WRITE:1;
4123	uint8_t SIZE:3;
4124	uint8_t PROT0:1;
4125	uint8_t PROT1:1;
4126	uint8_t PROT2:1;
4127	uint8_t PROT3:1;
4128	} B;
4129	} FEAT;
4130
4131	union { /* Flash ECC Data Register High */
4132	uint32_t R;
4133	struct {
4134	uint32_t FEDH:32;
4135	} B;
4136	} FEDRH;
4137
4138	union { /* Flash ECC Data Register Low */
4139	uint32_t R;
4140	struct {
4141	uint32_t FEDL:32;
4142	} B;
4143	} FEDRL;
4144
4145	union { /* RAM ECC Address Register */
4146	uint32_t R;
4147	struct {
4148	uint32_t REAR:32;
4149	} B;
4150	} REAR;
4151
4152	uint16_t ECSM_reserved0064; /* 0x0064-0x0065 */
4153
4154	union { /* RAM ECC Master Number Register */
4155	uint8_t R;
4156	struct {
4157	uint8_t:4;
4158	uint8_t REMR:4;
4159	} B;
4160	} REMR;
4161
4162	union { /* RAM ECC Attributes Register */
4163	uint8_t R;
4164	struct {
4165	uint8_t WRITE:1;
4166	uint8_t SIZE:3;
4167	uint8_t PROT0:1;
4168	uint8_t PROT1:1;
4169	uint8_t PROT2:1;
4170	uint8_t PROT3:1;
4171	} B;
4172	} REAT;
4173
4174	union { /* RAM ECC Data Register */
4175	uint32_t R;
4176	struct {
4177	uint32_t REDH:32;
4178	} B;
4179	} REDRH;
4180
4181	union { /* RAM ECC Data Register */
4182	uint32_t R;
4183	struct {
4184	uint32_t REDL:32;
4185	} B;
4186	} REDRL;
4187
4188	uint32_t ECSM_reserved0070[4068]; /* 0x0070-0x3FFF */
4189
4190	};
4191
4192	/****************************************************************************/
4193	/* MODULE : INTC */
4194	/****************************************************************************/
4195
4196	struct INTC_tag {
4197
4198	union { /* Module Configuration Register */
4199	uint32_t R;
4200	struct {
4201	uint32_t:26;
4202	uint32_t VTES:1;
4203	uint32_t:4;
4204	uint32_t HVEN:1;
4205	} B;
4206	} MCR;
4207
4208	uint32_t INTC_reserved0004; /* 0x0004-0x0007 */
4209
4210	union { /* Current Priority Register */
4211	uint32_t R;
4212	struct {
4213	uint32_t:28;
4214	uint32_t PRI:4;
4215	} B;
4216	} CPR;
4217
4218	uint32_t INTC_reserved000C; /* 0x000C-0x000F */
4219
4220	union { /* Interrupt Acknowledge Register */
4221	uint32_t R;
4222	struct {
4223	uint32_t VTBA:21;
4224	uint32_t INTVEC:9;
4225	uint32_t:2;
4226	} B;
4227	} IACKR;
4228
4229	uint32_t INTC_reserved0014; /* 0x0014-0x0017 */
4230
4231	union { /* End of Interrupt Register */
4232	uint32_t R;
4233	struct {
4234	uint32_t EOIR:32;
4235	} B;
4236	} EOIR;
4237
4238	uint32_t INTC_reserved001C; /* 0x001C-0x001F */
4239
4240	union { /* Software Set/Clear Interruput Register */
4241	uint8_t R;
4242	struct {
4243	uint8_t:6;
4244	uint8_t SET:1;
4245	uint8_t CLR:1;
4246	} B;
4247	} SSCIR[8];
4248
4249	uint32_t INTC_reserved0028[6]; /* 0x0028-0x003F */
4250
4251	union { /* Software Set/Clear Interrupt Register */
4252	uint8_t R;
4253	struct {
4254	uint8_t:4;
4255	uint8_t PRI:4;
4256	} B;
4257	} PSR[474];
4258
4259	uint16_t INTC_reserved021A[7923]; /* 0x021A-0x3FFF */
4260
4261	};
4262
4263	/****************************************************************************/
4264	/* MODULE : EQADC */
4265	/****************************************************************************/
4266
4267	struct EQADC_tag {
4268
4269	union { /* Module Configuration Register */
4270	uint32_t R;
4271	struct {
4272	uint32_t:24;
4273	uint32_t ICEA0:1;
4274	uint32_t ICEA1:1;
4275	uint32_t:1;
4276	uint32_t ESSIE:2;
4277	uint32_t:1;
4278	uint32_t DBG:2;
4279	} B;
4280	} MCR;
4281
4282	uint32_t eQADC_reserved0004; /* 0x0004-0x0007 */
4283
4284	union { /* Null Message Send Format Register */
4285	uint32_t R;
4286	struct {
4287	uint32_t:6;
4288	uint32_t NMF:26;
4289	} B;
4290	} NMSFR;
4291
4292	union { /* External Trigger Digital Filter Register */
4293	uint32_t R;
4294	struct {
4295	uint32_t:28;
4296	uint32_t DFL:4;
4297	} B;
4298	} ETDFR;
4299
4300	union { /* CFIFO Push Registers */
4301	uint32_t R;
4302	struct {
4303	uint32_t CFPUSH:32;
4304	} B;
4305	} CFPR[6];
4306
4307	uint32_t eQADC_reserved0028[2]; /* 0x0028-0x002F */
4308
4309	union { /* Result FIFO Pop Registers */
4310	uint32_t R;
4311	struct {
4312	uint32_t:16;
4313	uint32_t RFPOP:16;
4314	} B;
4315	} RFPR[6];
4316
4317	uint32_t eQADC_reserved0048[2]; /* 0x0048-0x004F */
4318
4319	union { /* CFIFO Control Registers */
4320	uint16_t R;
4321	struct {
4322	uint16_t:5;
4323	uint16_t SSE:1;
4324	uint16_t CFINV:1;
4325	uint16_t:1;
4326	uint16_t MODE:4;
4327	uint16_t:4;
4328	} B;
4329	} CFCR[6];
4330
4331	uint32_t eQADC_reserved005C; /* 0x005C-0x005F */
4332
4333	union { /* Interrupt and DMA Control Registers */
4334	uint16_t R;
4335	struct {
4336	uint16_t NCIE:1;
4337	uint16_t TORIE:1;
4338	uint16_t PIE:1;
4339	uint16_t EOQIE:1;
4340	uint16_t CFUIE:1;
4341	uint16_t:1;
4342	uint16_t CFFE:1;
4343	uint16_t CFFS:1;
4344	uint16_t:4;
4345	uint16_t RFOIE:1;
4346	uint16_t:1;
4347	uint16_t RFDE:1;
4348	uint16_t RFDS:1;
4349	} B;
4350	} IDCR[6];
4351
4352	uint32_t eQADC_reserved006C; /* 0x006C-0x006F */
4353
4354	union { /* FIFO and Interrupt Status Registers */
4355	uint32_t R;
4356	struct {
4357	uint32_t NCF:1;
4358	uint32_t TORF:1;
4359	uint32_t PF:1;
4360	uint32_t EOQF:1;
4361	uint32_t CFUF:1;
4362	uint32_t SSS:1;
4363	uint32_t CFFF:1;
4364	uint32_t:5;
4365	uint32_t RFOF:1;
4366	uint32_t:1;
4367	uint32_t RFDF:1;
4368	uint32_t:1;
4369	uint32_t CFCTR:4;
4370	uint32_t TNXTPTR:4;
4371	uint32_t RFCTR:4;
4372	uint32_t POPNXTPTR:4;
4373	} B;
4374	} FISR[6];
4375
4376	uint32_t eQADC_reserved0088[2]; /* 0x0088-0x008F */
4377
4378	union { /* CFIFO Transfer Counter Registers */
4379	uint16_t R;
4380	struct {
4381	uint16_t:5;
4382	uint16_t TCCF:11; /* Legacy naming - refer to TC_CF in Reference Manual */
4383	} B;
4384	} CFTCR[6];
4385
4386	uint32_t eQADC_reserved009C[1]; /* 0x009F */
4387
4388	union { /* CFIFO Status Register 0 */
4389	uint32_t R;
4390	struct {
4391	uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB0 in Reference Manual */
4392	uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB0 in Reference Manual */
4393	uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB0 in Reference Manual */
4394	uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB0 in Reference Manual */
4395	uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB0 in Reference Manual */
4396	uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB0 in Reference Manual */
4397	uint32_t:5;
4398	uint32_t LCFTCB0:4;
4399	uint32_t TC_LCFTCB0:11;
4400	} B;
4401	} CFSSR0;
4402
4403	union { /* CFIFO Status Register 1 */
4404	uint32_t R;
4405	struct {
4406	uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB1 in Reference Manual */
4407	uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB1 in Reference Manual */
4408	uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB1 in Reference Manual */
4409	uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB1 in Reference Manual */
4410	uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB1 in Reference Manual */
4411	uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB1 in Reference Manual */
4412	uint32_t:5;
4413	uint32_t LCFTCB1:4;
4414	uint32_t TC_LCFTCB1:11;
4415	} B;
4416	} CFSSR1;
4417
4418	union { /* CFIFO Status Register 2 */
4419	uint32_t R;
4420	struct {
4421	uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TSSI in Reference Manual */
4422	uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TSSI in Reference Manual */
4423	uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TSSI in Reference Manual */
4424	uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TSSI in Reference Manual */
4425	uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TSSI in Reference Manual */
4426	uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TSSI in Reference Manual */
4427	uint32_t:4;
4428	uint32_t ECBNI:1;
4429	uint32_t LCFTSSI:4;
4430	uint32_t TC_LCFTSSI:11;
4431	} B;
4432	} CFSSR2;
4433
4434	union { /* CFIFO Status Register */
4435	uint32_t R;
4436	struct {
4437	uint32_t CFS0:2;
4438	uint32_t CFS1:2;
4439	uint32_t CFS2:2;
4440	uint32_t CFS3:2;
4441	uint32_t CFS4:2;
4442	uint32_t CFS5:2;
4443	uint32_t:20;
4444	} B;
4445	} CFSR;
4446
4447	uint32_t eQADC_reserved00B0; /* 0x00B0-0x00B3 */
4448
4449	union { /* SSI Control Register */
4450	uint32_t R;
4451	struct {
4452	uint32_t:21;
4453	uint32_t MDT:3;
4454	uint32_t:4;
4455	uint32_t BR:4;
4456	} B;
4457	} SSICR;
4458
4459	union { /* SSI Recieve Data Register */
4460	uint32_t R;
4461	struct {
4462	uint32_t RDV:1;
4463	uint32_t:5;
4464	uint32_t RDATA:26;
4465	} B;
4466	} SSIRDR;
4467
4468	uint32_t eQADC_reserved00BC[17]; /* 0x00BC-0x00FF */
4469
4470	struct {
4471	union {
4472	uint32_t R;
4473	struct {
4474	uint32_t CFIFO_DATA:32;
4475	} B;
4476	} R[4];
4477
4478	uint32_t eQADC_cf_reserved010[12]; /* CFIFO offset 0x010-0x03F */
4479
4480	} CF[6];
4481
4482	uint32_t eQADC_reserved0280[32]; /* 0x0280-0x02FF */
4483
4484	struct {
4485	union {
4486	uint32_t R;
4487	struct {
4488	uint32_t RFIFO_DATA:32;
4489	} B;
4490	} R[4];
4491
4492	uint32_t eQADC_rf_reserved010[12]; /* RFIFO offset 0x010-0x03F */
4493
4494	} RF[6];
4495
4496	uint32_t eQADC_reserved0480[3808]; /* 0x0480-0x3FFF */
4497	};
4498
4499	/****************************************************************************/
4500	/* MODULE : Decimation Filter */
4501	/****************************************************************************/
4502
4503	struct DECFIL_tag {
4504
4505	union { /* Module Configuration Register */
4506	uint32_t R;
4507	struct {
4508	uint32_t MDIS:1;
4509	uint32_t FREN:1;
4510	uint32_t :1;
4511	uint32_t FRZ:1;
4512	uint32_t SRES:1;
4513	uint32_t CASCD:2;
4514	uint32_t IDEN:1;
4515	uint32_t ODEN:1;
4516	uint32_t ERREN:1;
4517	uint32_t :1;
4518	uint32_t FTYPE:2;
4519	uint32_t :1;
4520	uint32_t SCAL:2;
4521	uint32_t :1;
4522	uint32_t SAT:1;
4523	uint32_t ISEL:1;
4524	uint32_t :1;
4525	uint32_t DEC_RATE:4;
4526	uint32_t :1;
4527	uint32_t DSEL:1;
4528	uint32_t IBIE:1;
4529	uint32_t OBIE:1;
4530	uint32_t EDME:1;
4531	uint32_t TORE:1;
4532	uint32_t TRFE:1;
4533	uint32_t :1;
4534	} B;
4535	} MCR;
4536
4537	union { /* Module Status Register */
4538	uint32_t R;
4539	struct {
4540	uint32_t BSY:1;
4541	uint32_t:1;
4542	uint32_t DEC_COUNTER:4;
4543	uint32_t IDFC:1;
4544	uint32_t ODFC:1;
4545	uint32_t:1;
4546	uint32_t IBIC:1;
4547	uint32_t OBIC:1;
4548	uint32_t:1;
4549	uint32_t DIVRC:1;
4550	uint32_t OVFC:1;
4551	uint32_t OVRC:1;
4552	uint32_t IVRC:1;
4553	uint32_t:6;
4554	uint32_t IDF:1;
4555	uint32_t ODF:1;
4556	uint32_t:1;
4557	uint32_t IBIF:1;
4558	uint32_t OBIF:1;
4559	uint32_t:1;
4560	uint32_t DIVR:1;
4561	uint32_t OVF:1;
4562	uint32_t OVR:1;
4563	uint32_t IVR:1;
4564	} B;
4565	} SR;
4566
4567	union { /* Module Extended Config Register */
4568	uint32_t R;
4569	struct {
4570	uint32_t SDMAE:1;
4571	uint32_t SSIG:1;
4572	uint32_t SSAT:1;
4573	uint32_t SCSAT:1;
4574	uint32_t:10;
4575	uint32_t SRQ:1;
4576	uint32_t SZR0:1;
4577	uint32_t:1;
4578	uint32_t SISEL:1;
4579	uint32_t SZROSEL:2;
4580	uint32_t:2;
4581	uint32_t SHLTSEL:2;
4582	uint32_t:1;
4583	uint32_t SRQSEL:3;
4584	uint32_t:2;
4585	uint32_t SENSEL:2;
4586	} B;
4587	} MXCR;
4588
4589	union { /* Module Extended Status Register */
4590	uint32_t R;
4591	struct {
4592	uint32_t:7;
4593	uint32_t SDFC:1;
4594	uint32_t:2;
4595	uint32_t SSEC:1;
4596	uint32_t SCEC:1;
4597	uint32_t:1;
4598	uint32_t SSOVFC:1;
4599	uint32_t SCOVFC:1;
4600	uint32_t SVRC:1;
4601	uint32_t:7;
4602	uint32_t SDF:1;
4603	uint32_t:2;
4604	uint32_t SSE:1;
4605	uint32_t SCE:1;
4606	uint32_t:1;
4607	uint32_t SSOVF:1;
4608	uint32_t SCOVF:1;
4609	uint32_t SVR:1;
4610	} B;
4611	} MXSR;
4612
4613	union { /* Interface Input Buffer Register */
4614	uint32_t R;
4615	struct {
4616	uint32_t:14;
4617	uint32_t PREFILL:1;
4618	uint32_t FLUSH:1;
4619	uint32_t INPBUF:16;
4620	} B;
4621	} IB;
4622
4623	union { /* Interface Output Buffer Register */
4624	uint32_t R;
4625	struct {
4626	uint32_t:9;
4627	uint32_t TSI:1;
4628	uint32_t:2;
4629	uint32_t OUTTAG:4;
4630	uint32_t OUTBUF:16;
4631	} B;
4632	} OB;
4633
4634	uint32_t DFILT_reserved0018[2]; /* 0x0018-0x001F */
4635
4636	union { /* Coefficient n Register */
4637	int32_t R;
4638	struct {
4639	int32_t:8;
4640	int32_t COEF:24;
4641	} B;
4642	} COEF[9];
4643
4644	uint32_t DFILT_reserved0044[13]; /* 0x0044-0x0077 */
4645
4646	union { /* TAP n Register */
4647	int32_t R;
4648	struct {
4649	int32_t:8;
4650	int32_t TAP:24;
4651	} B;
4652	} TAP[8];
4653
4654	uint32_t DFILT_reserved0098[14]; /* 0x0098-0x00CF */
4655
4656	union { /* EDID Register */
4657	uint32_t R;
4658	struct {
4659	uint32_t:16;
4660	uint32_t SAMP_DATA:16;
4661	} B;
4662	} EDID;
4663
4664	uint32_t DFILT_reserved00D4[459]; /* 0x00D4-0x07FF */
4665
4666	};
4667
4668	/****************************************************************************/
4669	/* MODULE : DSPI */
4670	/****************************************************************************/
4671
4672	struct DSPI_tag {
4673
4674	union DSPI_MCR_tag { /* Module Configuration Register */
4675	uint32_t R;
4676	struct {
4677	uint32_t MSTR:1;
4678	uint32_t CONT_SCKE:1;
4679	uint32_t DCONF:2;
4680	uint32_t FRZ:1;
4681	uint32_t MTFE:1;
4682	uint32_t PCSSE:1;
4683	uint32_t ROOE:1;
4684	uint32_t PCSIS7:1;
4685	uint32_t PCSIS6:1;
4686	uint32_t PCSIS5:1;
4687	uint32_t PCSIS4:1;
4688	uint32_t PCSIS3:1;
4689	uint32_t PCSIS2:1;
4690	uint32_t PCSIS1:1;
4691	uint32_t PCSIS0:1;
4692	uint32_t DOZE:1;
4693	uint32_t MDIS:1;
4694	uint32_t DIS_TXF:1;
4695	uint32_t DIS_RXF:1;
4696	uint32_t CLR_TXF:1;
4697	uint32_t CLR_RXF:1;
4698	uint32_t SMPL_PT:2;
4699	uint32_t:7;
4700	uint32_t HALT:1;
4701	} B;
4702	} MCR;
4703
4704	uint32_t DSPI_reserved0004; /* 0x0004-0x0007 */
4705
4706	union { /* Transfer Count Register */
4707	uint32_t R;
4708	struct {
4709	uint32_t TCNT:16;
4710	uint32_t:16;
4711	} B;
4712	} TCR;
4713
4714	union DSPI_CTAR_tag {/* Clock and Transfer Attributes Registers */
4715	uint32_t R;
4716	struct {
4717	uint32_t DBR:1;
4718	uint32_t FMSZ:4;
4719	uint32_t CPOL:1;
4720	uint32_t CPHA:1;
4721	uint32_t LSBFE:1;
4722	uint32_t PCSSCK:2;
4723	uint32_t PASC:2;
4724	uint32_t PDT:2;
4725	uint32_t PBR:2;
4726	uint32_t CSSCK:4;
4727	uint32_t ASC:4;
4728	uint32_t DT:4;
4729	uint32_t BR:4;
4730	} B;
4731	} CTAR[8];
4732
4733	union DSPI_SR_tag { /* Status Register */
4734	uint32_t R;
4735	struct {
4736	uint32_t TCF:1;
4737	uint32_t TXRXS:1;
4738	uint32_t:1;
4739	uint32_t EOQF:1;
4740	uint32_t TFUF:1;
4741	uint32_t:1;
4742	uint32_t TFFF:1;
4743	uint32_t:5;
4744	uint32_t RFOF:1;
4745	uint32_t:1;
4746	uint32_t RFDF:1;
4747	uint32_t:1;
4748	uint32_t TXCTR:4;
4749	uint32_t TXNXTPTR:4;
4750	uint32_t RXCTR:4;
4751	uint32_t POPNXTPTR:4;
4752	} B;
4753	} SR;
4754
4755	union DSPI_RSER_tag { /* DMA/Interrupt Request Select and Enable Register */
4756	uint32_t R;
4757	struct {
4758	uint32_t TCFRE:1;
4759	uint32_t:2;
4760	uint32_t EOQFRE:1;
4761	uint32_t TFUFRE:1;
4762	uint32_t:1;
4763	uint32_t TFFFRE:1;
4764	uint32_t TFFFDIRS:1;
4765	uint32_t:4;
4766	uint32_t RFOFRE:1;
4767	uint32_t:1;
4768	uint32_t RFDFRE:1;
4769	uint32_t RFDFDIRS:1;
4770	uint32_t:16;
4771	} B;
4772	} RSER;
4773
4774	union DSPI_PUSHR_tag { /* PUSH TX FIFO Register */
4775	uint32_t R;
4776	struct {
4777	uint32_t CONT:1;
4778	uint32_t CTAS:3;
4779	uint32_t EOQ:1;
4780	uint32_t CTCNT:1;
4781	uint32_t:2;
4782	uint32_t PCS7:1;
4783	uint32_t PCS6:1;
4784	uint32_t PCS5:1;
4785	uint32_t PCS4:1;
4786	uint32_t PCS3:1;
4787	uint32_t PCS2:1;
4788	uint32_t PCS1:1;
4789	uint32_t PCS0:1;
4790	uint32_t TXDATA:16;
4791	} B;
4792	} PUSHR;
4793
4794	union DSPI_POPR_tag { /* POP RX FIFO Register */
4795	uint32_t R;
4796	struct {
4797	uint32_t:16;
4798	uint32_t RXDATA:16;
4799	} B;
4800	} POPR;
4801
4802	union { /* Transmit FIFO Registers */
4803	uint32_t R;
4804	struct {
4805	uint32_t TXCMD:16;
4806	uint32_t TXDATA:16;
4807	} B;
4808	} TXFR[4];
4809
4810	uint32_t DSPI_reserved004C[12]; /* 0x004C-0x007B */
4811
4812	union { /* Transmit FIFO Registers */
4813	uint32_t R;
4814	struct {
4815	uint32_t:16;
4816	uint32_t RXDATA:16;
4817	} B;
4818	} RXFR[4];
4819
4820	uint32_t DSPI_reserved008C[12]; /* 0x008C-0x00BB */
4821
4822	union { /* DSI Configuration Register */
4823	uint32_t R;
4824	struct {
4825	uint32_t MTOE:1;
4826	uint32_t:1;
4827	uint32_t MTOCNT:6;
4828	uint32_t:3;
4829	uint32_t TSBC:1;
4830	uint32_t TXSS:1;
4831	uint32_t TPOL:1;
4832	uint32_t TRRE:1;
4833	uint32_t CID:1;
4834	uint32_t DCONT:1;
4835	uint32_t DSICTAS:3;
4836	uint32_t:4;
4837	uint32_t DPCS7:1;
4838	uint32_t DPCS6:1;
4839	uint32_t DPCS5:1;
4840	uint32_t DPCS4:1;
4841	uint32_t DPCS3:1;
4842	uint32_t DPCS2:1;
4843	uint32_t DPCS1:1;
4844	uint32_t DPCS0:1;
4845	} B;
4846	} DSICR;
4847
4848	union { /* DSI Serialization Data Register */
4849	uint32_t R;
4850	struct {
4851	uint32_t SER_DATA:32;
4852	} B;
4853	} SDR;
4854
4855	union { /* DSI Alternate Serialization Data Register */
4856	uint32_t R;
4857	struct {
4858	uint32_t ASER_DATA:32;
4859	} B;
4860	} ASDR;
4861
4862	union { /* DSI Transmit Comparison Register */
4863	uint32_t R;
4864	struct {
4865	uint32_t COMP_DATA:32;
4866	} B;
4867	} COMPR;
4868
4869	union { /* DSI deserialization Data Register */
4870	uint32_t R;
4871	struct {
4872	uint32_t DESER_DATA:32;
4873	} B;
4874	} DDR;
4875
4876	union {
4877	uint32_t R;
4878	struct {
4879	uint32_t:3;
4880	uint32_t TSBCNT:5;
4881	uint32_t:16;
4882	uint32_t DPCS1_7:1;
4883	uint32_t DPCS1_6:1;
4884	uint32_t DPCS1_5:1;
4885	uint32_t DPCS1_4:1;
4886	uint32_t DPCS1_3:1;
4887	uint32_t DPCS1_2:1;
4888	uint32_t DPCS1_1:1;
4889	uint32_t DPCS1_0:1;
4890	} B;
4891	} DSICR1;
4892	uint32_t DSPI_reserved00D4[4043]; /* 0x00D4-0x3FFF */
4893
4894	};
4895
4896	/****************************************************************************/
4897	/* MODULE : eSCI */
4898	/****************************************************************************/
4899
4900	struct ESCI_tag {
4901	union ESCI_CR1_tag { /* Control Register 1 */
4902	uint32_t R;
4903	struct {
4904	uint32_t:3;
4905	uint32_t SBR:13;
4906	uint32_t LOOPS:1;
4907	uint32_t:1;
4908	uint32_t RSRC:1;
4909	uint32_t M:1;
4910	uint32_t WAKE:1;
4911	uint32_t ILT:1;
4912	uint32_t PE:1;
4913	uint32_t PT:1;
4914	uint32_t TIE:1;
4915	uint32_t TCIE:1;
4916	uint32_t RIE:1;
4917	uint32_t ILIE:1;
4918	uint32_t TE:1;
4919	uint32_t RE:1;
4920	uint32_t RWU:1;
4921	uint32_t SBK:1;
4922	} B;
4923	} CR1;
4924
4925	union ESCI_CR2_tag { /* Control Register 2 */
4926	uint16_t R;
4927	struct {
4928	uint16_t MDIS:1;
4929	uint16_t FBR:1;
4930	uint16_t BSTP:1;
4931	uint16_t IEBERR:1;
4932	uint16_t RXDMA:1;
4933	uint16_t TXDMA:1;
4934	uint16_t BRK13:1;
4935	uint16_t TXDIR:1;
4936	uint16_t BESM13:1;
4937	uint16_t SBSTP:1;
4938	uint16_t RXPOL:1;
4939	uint16_t PMSK:1;
4940	uint16_t ORIE:1;
4941	uint16_t NFIE:1;
4942	uint16_t FEIE:1;
4943	uint16_t PFIE:1;
4944	} B;
4945	} CR2;
4946
4947	union ESCI_DR_tag { /* Data Register */
4948	uint16_t R;
4949
4950	struct {
4951	uint16_t RN:1;
4952	uint16_t TN:1;
4953	uint16_t ERR:1;
4954	uint16_t:1;
4955	uint16_t RD_11:4;
4956	uint16_t D:8;
4957	} B;
4958	} DR; /* Legacy naming - refer to SDR in Reference Manual */
4959
4960	union ESCI_SR_tag { /* Status Register */
4961	uint32_t R;
4962	struct {
4963	uint32_t TDRE:1;
4964	uint32_t TC:1;
4965	uint32_t RDRF:1;
4966	uint32_t IDLE:1;
4967	uint32_t OR:1;
4968	uint32_t NF:1;
4969	uint32_t FE:1;
4970	uint32_t PF:1;
4971	uint32_t:3;
4972	uint32_t BERR:1;
4973	uint32_t:2;
4974	uint32_t TACT:1;
4975	uint32_t RAF:1;
4976	uint32_t RXRDY:1;
4977	uint32_t TXRDY:1;
4978	uint32_t LWAKE:1;
4979	uint32_t STO:1;
4980	uint32_t PBERR:1;
4981	uint32_t CERR:1;
4982	uint32_t CKERR:1;
4983	uint32_t FRC:1;
4984	uint32_t:6;
4985	uint32_t UREQ:1;
4986	uint32_t OVFL:1;
4987	} B;
4988	} SR;
4989
4990	union { /* LIN Control Register */
4991	uint32_t R;
4992	struct {
4993	uint32_t LRES:1;
4994	uint32_t WU:1;
4995	uint32_t WUD0:1;
4996	uint32_t WUD1:1;
4997	uint32_t :2;
4998	uint32_t PRTY:1;
4999	uint32_t LIN:1;
5000	uint32_t RXIE:1;
5001	uint32_t TXIE:1;
5002	uint32_t WUIE:1;
5003	uint32_t STIE:1;
5004	uint32_t PBIE:1;
5005	uint32_t CIE:1;
5006	uint32_t CKIE:1;
5007	uint32_t FCIE:1;
5008	uint32_t:6;
5009	uint32_t UQIE:1;
5010	uint32_t OFIE:1;
5011	uint32_t:8;
5012	} B;
5013	} LCR;
5014
5015	union { /* LIN Transmit Register */
5016	uint8_t R;
5017	} LTR;
5018
5019	uint8_t eSCI_reserved0011[3]; /* 0x0011-0x0013 */
5020
5021	union { /* LIN Recieve Register */
5022	uint8_t R;
5023	struct {
5024	uint8_t D:8;
5025	} B;
5026	} LRR;
5027
5028	uint8_t eSCI_reserved0015[3]; /* 0x0015-0x0017 */
5029
5030	union { /* LIN CRC Polynom Register */
5031	uint16_t R;
5032	struct {
5033	uint16_t P:16;
5034	} B;
5035	} LPR;
5036
5037	union { /* Control Register 3 */
5038	uint16_t R;
5039	struct {
5040	uint16_t:3;
5041	uint16_t SYNM:1;
5042	uint16_t EROE:1;
5043	uint16_t ERFE:1;
5044	uint16_t ERPE:1;
5045	uint16_t M2:1;
5046	uint16_t:8;
5047	} B;
5048	} CR3;
5049
5050	uint32_t eSCI_reserved001C; /* 0x001C-0x001F */
5051
5052	uint32_t eSCI_reserved0020[4088]; /* 0x0020-0x3FFF */
5053
5054	};
5055
5056	/****************************************************************************/
5057	/* MODULE : FlexCAN */
5058	/****************************************************************************/
5059
5060	struct FLEXCAN2_tag {
5061	union { /* Module Configuration Register */
5062	uint32_t R;
5063	struct {
5064	uint32_t MDIS:1;
5065	uint32_t FRZ:1;
5066	uint32_t FEN:1;
5067	uint32_t HALT:1;
5068	uint32_t NOTRDY:1;
5069	uint32_t WAK_MSK:1;
5070	uint32_t SOFTRST:1;
5071	uint32_t FRZACK:1;
5072	uint32_t SUPV:1;
5073	uint32_t SLF_WAK:1;
5074	uint32_t WRNEN:1;
5075	uint32_t MDISACK:1;
5076	uint32_t WAK_SRC:1;
5077	uint32_t DOZE:1;
5078	uint32_t SRXDIS:1;
5079	uint32_t BCC:1;
5080	uint32_t:2;
5081	uint32_t LPRIO_EN:1;
5082	uint32_t AEN:1;
5083	uint32_t:2;
5084	uint32_t IDAM:2;
5085	uint32_t:2;
5086	uint32_t MAXMB:6;
5087	} B;
5088	} MCR;
5089
5090	union { /* Control Register */
5091	uint32_t R;
5092	struct {
5093	uint32_t PRESDIV:8;
5094	uint32_t RJW:2;
5095	uint32_t PSEG1:3;
5096	uint32_t PSEG2:3;
5097	uint32_t BOFFMSK:1;
5098	uint32_t ERRMSK:1;
5099	uint32_t CLKSRC:1;
5100	uint32_t LPB:1;
5101	uint32_t TWRNMSK:1;
5102	uint32_t RWRNMSK:1;
5103	uint32_t:2;
5104	uint32_t SMP:1;
5105	uint32_t BOFFREC:1;
5106	uint32_t TSYN:1;
5107	uint32_t LBUF:1;
5108	uint32_t LOM:1;
5109	uint32_t PROPSEG:3;
5110	} B;
5111	} CR; /* Legacy naming - refer to CTRL in Reference Manual */
5112
5113	union { /* Free Running Timer */
5114	uint32_t R;
5115	} TIMER;
5116
5117	int32_t FLEXCAN_reserved000C; /* 0x000C-0x000F */
5118
5119	union { /* RX Global Mask */
5120	uint32_t R;
5121	struct {
5122	uint32_t MI31:1;
5123	uint32_t MI30:1;
5124	uint32_t MI29:1;
5125	uint32_t MI28:1;
5126	uint32_t MI27:1;
5127	uint32_t MI26:1;
5128	uint32_t MI25:1;
5129	uint32_t MI24:1;
5130	uint32_t MI23:1;
5131	uint32_t MI22:1;
5132	uint32_t MI21:1;
5133	uint32_t MI20:1;
5134	uint32_t MI19:1;
5135	uint32_t MI18:1;
5136	uint32_t MI17:1;
5137	uint32_t MI16:1;
5138	uint32_t MI15:1;
5139	uint32_t MI14:1;
5140	uint32_t MI13:1;
5141	uint32_t MI12:1;
5142	uint32_t MI11:1;
5143	uint32_t MI10:1;
5144	uint32_t MI9:1;
5145	uint32_t MI8:1;
5146	uint32_t MI7:1;
5147	uint32_t MI6:1;
5148	uint32_t MI5:1;
5149	uint32_t MI4:1;
5150	uint32_t MI3:1;
5151	uint32_t MI2:1;
5152	uint32_t MI1:1;
5153	uint32_t MI0:1;
5154	} B;
5155	} RXGMASK;
5156
5157	union { /* RX 14 Mask */
5158	uint32_t R;
5159	struct {
5160	uint32_t MI31:1;
5161	uint32_t MI30:1;
5162	uint32_t MI29:1;
5163	uint32_t MI28:1;
5164	uint32_t MI27:1;
5165	uint32_t MI26:1;
5166	uint32_t MI25:1;
5167	uint32_t MI24:1;
5168	uint32_t MI23:1;
5169	uint32_t MI22:1;
5170	uint32_t MI21:1;
5171	uint32_t MI20:1;
5172	uint32_t MI19:1;
5173	uint32_t MI18:1;
5174	uint32_t MI17:1;
5175	uint32_t MI16:1;
5176	uint32_t MI15:1;
5177	uint32_t MI14:1;
5178	uint32_t MI13:1;
5179	uint32_t MI12:1;
5180	uint32_t MI11:1;
5181	uint32_t MI10:1;
5182	uint32_t MI9:1;
5183	uint32_t MI8:1;
5184	uint32_t MI7:1;
5185	uint32_t MI6:1;
5186	uint32_t MI5:1;
5187	uint32_t MI4:1;
5188	uint32_t MI3:1;
5189	uint32_t MI2:1;
5190	uint32_t MI1:1;
5191	uint32_t MI0:1;
5192	} B;
5193	} RX14MASK;
5194
5195	union { /* RX 15 Mask */
5196	uint32_t R;
5197	struct {
5198	uint32_t MI31:1;
5199	uint32_t MI30:1;
5200	uint32_t MI29:1;
5201	uint32_t MI28:1;
5202	uint32_t MI27:1;
5203	uint32_t MI26:1;
5204	uint32_t MI25:1;
5205	uint32_t MI24:1;
5206	uint32_t MI23:1;
5207	uint32_t MI22:1;
5208	uint32_t MI21:1;
5209	uint32_t MI20:1;
5210	uint32_t MI19:1;
5211	uint32_t MI18:1;
5212	uint32_t MI17:1;
5213	uint32_t MI16:1;
5214	uint32_t MI15:1;
5215	uint32_t MI14:1;
5216	uint32_t MI13:1;
5217	uint32_t MI12:1;
5218	uint32_t MI11:1;
5219	uint32_t MI10:1;
5220	uint32_t MI9:1;
5221	uint32_t MI8:1;
5222	uint32_t MI7:1;
5223	uint32_t MI6:1;
5224	uint32_t MI5:1;
5225	uint32_t MI4:1;
5226	uint32_t MI3:1;
5227	uint32_t MI2:1;
5228	uint32_t MI1:1;
5229	uint32_t MI0:1;
5230	} B;
5231	} RX15MASK;
5232
5233	union { /* Error Counter Register */
5234	uint32_t R;
5235	struct {
5236	uint32_t:16;
5237	uint32_t RXECNT:8;
5238	uint32_t TXECNT:8;
5239	} B;
5240	} ECR;
5241
5242	union { /* Error and Status Register */
5243	uint32_t R;
5244	struct {
5245	uint32_t:14;
5246
5247	uint32_t TWRNINT:1;
5248	uint32_t RWRNINT:1;
5249	uint32_t BIT1ERR:1;
5250	uint32_t BIT0ERR:1;
5251	uint32_t ACKERR:1;
5252	uint32_t CRCERR:1;
5253	uint32_t FRMERR:1;
5254	uint32_t STFERR:1;
5255	uint32_t TXWRN:1;
5256	uint32_t RXWRN:1;
5257	uint32_t IDLE:1;
5258	uint32_t TXRX:1;
5259	uint32_t FLTCONF:2;
5260	uint32_t:1;
5261	uint32_t BOFFINT:1;
5262	uint32_t ERRINT:1;
5263	uint32_t WAKINT:1;
5264	} B;
5265	} ESR;
5266
5267	union { /* Interruput Masks Register */
5268	uint32_t R;
5269	struct {
5270	uint32_t BUF63M:1;
5271	uint32_t BUF62M:1;
5272	uint32_t BUF61M:1;
5273	uint32_t BUF60M:1;
5274	uint32_t BUF59M:1;
5275	uint32_t BUF58M:1;
5276	uint32_t BUF57M:1;
5277	uint32_t BUF56M:1;
5278	uint32_t BUF55M:1;
5279	uint32_t BUF54M:1;
5280	uint32_t BUF53M:1;
5281	uint32_t BUF52M:1;
5282	uint32_t BUF51M:1;
5283	uint32_t BUF50M:1;
5284	uint32_t BUF49M:1;
5285	uint32_t BUF48M:1;
5286	uint32_t BUF47M:1;
5287	uint32_t BUF46M:1;
5288	uint32_t BUF45M:1;
5289	uint32_t BUF44M:1;
5290	uint32_t BUF43M:1;
5291	uint32_t BUF42M:1;
5292	uint32_t BUF41M:1;
5293	uint32_t BUF40M:1;
5294	uint32_t BUF39M:1;
5295	uint32_t BUF38M:1;
5296	uint32_t BUF37M:1;
5297	uint32_t BUF36M:1;
5298	uint32_t BUF35M:1;
5299	uint32_t BUF34M:1;
5300	uint32_t BUF33M:1;
5301	uint32_t BUF32M:1;
5302	} B;
5303	} IMRH; /* Legacy naming - refer to IMASK2 in Reference Manual */
5304
5305	union { /* Interruput Masks Register */
5306	uint32_t R;
5307	struct {
5308	uint32_t BUF31M:1;
5309	uint32_t BUF30M:1;
5310	uint32_t BUF29M:1;
5311	uint32_t BUF28M:1;
5312	uint32_t BUF27M:1;
5313	uint32_t BUF26M:1;
5314	uint32_t BUF25M:1;
5315	uint32_t BUF24M:1;
5316	uint32_t BUF23M:1;
5317	uint32_t BUF22M:1;
5318	uint32_t BUF21M:1;
5319	uint32_t BUF20M:1;
5320	uint32_t BUF19M:1;
5321	uint32_t BUF18M:1;
5322	uint32_t BUF17M:1;
5323	uint32_t BUF16M:1;
5324	uint32_t BUF15M:1;
5325	uint32_t BUF14M:1;
5326	uint32_t BUF13M:1;
5327	uint32_t BUF12M:1;
5328	uint32_t BUF11M:1;
5329	uint32_t BUF10M:1;
5330	uint32_t BUF09M:1;
5331	uint32_t BUF08M:1;
5332	uint32_t BUF07M:1;
5333	uint32_t BUF06M:1;
5334	uint32_t BUF05M:1;
5335	uint32_t BUF04M:1;
5336	uint32_t BUF03M:1;
5337	uint32_t BUF02M:1;
5338	uint32_t BUF01M:1;
5339	uint32_t BUF00M:1;
5340	} B;
5341	} IMRL; /* Legacy naming - refer to IMASK1 in Reference Manual */
5342
5343	union { /* Interruput Flag Register */
5344	uint32_t R;
5345	struct {
5346	uint32_t BUF63I:1;
5347	uint32_t BUF62I:1;
5348	uint32_t BUF61I:1;
5349	uint32_t BUF60I:1;
5350	uint32_t BUF59I:1;
5351	uint32_t BUF58I:1;
5352	uint32_t BUF57I:1;
5353	uint32_t BUF56I:1;
5354	uint32_t BUF55I:1;
5355	uint32_t BUF54I:1;
5356	uint32_t BUF53I:1;
5357	uint32_t BUF52I:1;
5358	uint32_t BUF51I:1;
5359	uint32_t BUF50I:1;
5360	uint32_t BUF49I:1;
5361	uint32_t BUF48I:1;
5362	uint32_t BUF47I:1;
5363	uint32_t BUF46I:1;
5364	uint32_t BUF45I:1;
5365	uint32_t BUF44I:1;
5366	uint32_t BUF43I:1;
5367	uint32_t BUF42I:1;
5368	uint32_t BUF41I:1;
5369	uint32_t BUF40I:1;
5370	uint32_t BUF39I:1;
5371	uint32_t BUF38I:1;
5372	uint32_t BUF37I:1;
5373	uint32_t BUF36I:1;
5374	uint32_t BUF35I:1;
5375	uint32_t BUF34I:1;
5376	uint32_t BUF33I:1;
5377	uint32_t BUF32I:1;
5378	} B;
5379	} IFRH; /* Legacy naming - refer to IFLAG2 in Reference Manual */
5380
5381	union { /* Interruput Flag Register */
5382	uint32_t R;
5383	struct {
5384	uint32_t BUF31I:1;
5385	uint32_t BUF30I:1;
5386	uint32_t BUF29I:1;
5387	uint32_t BUF28I:1;
5388	uint32_t BUF27I:1;
5389	uint32_t BUF26I:1;
5390	uint32_t BUF25I:1;
5391	uint32_t BUF24I:1;
5392	uint32_t BUF23I:1;
5393	uint32_t BUF22I:1;
5394	uint32_t BUF21I:1;
5395	uint32_t BUF20I:1;
5396	uint32_t BUF19I:1;
5397	uint32_t BUF18I:1;
5398	uint32_t BUF17I:1;
5399	uint32_t BUF16I:1;
5400	uint32_t BUF15I:1;
5401	uint32_t BUF14I:1;
5402	uint32_t BUF13I:1;
5403	uint32_t BUF12I:1;
5404	uint32_t BUF11I:1;
5405	uint32_t BUF10I:1;
5406	uint32_t BUF09I:1;
5407	uint32_t BUF08I:1;
5408	uint32_t BUF07I:1;
5409	uint32_t BUF06I:1;
5410	uint32_t BUF05I:1;
5411	uint32_t BUF04I:1;
5412	uint32_t BUF03I:1;
5413	uint32_t BUF02I:1;
5414	uint32_t BUF01I:1;
5415	uint32_t BUF00I:1;
5416	} B;
5417	} IFRL; /* Legacy naming - refer to IFLAG1 in Reference Manual */
5418
5419	uint32_t FLEXCAN_reserved0034[19]; /* 0x0034-0x007F */
5420
5421	struct canbuf_t {
5422	union {
5423	uint32_t R;
5424	struct {
5425	uint32_t:4;
5426	uint32_t CODE:4;
5427	uint32_t:1;
5428	uint32_t SRR:1;
5429	uint32_t IDE:1;
5430	uint32_t RTR:1;
5431	uint32_t LENGTH:4;
5432	uint32_t TIMESTAMP:16;
5433	} B;
5434	} CS;
5435
5436	union {
5437	uint32_t R;
5438	struct {
5439	uint32_t PRIO:3;
5440	uint32_t STD_ID:11;
5441	uint32_t EXT_ID:18;
5442	} B;
5443	} ID;
5444
5445	union {
5446	uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
5447	uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
5448	uint32_t W[2]; /* Data buffer in words (32 bits) */
5449	uint32_t R[2]; /* Data buffer in words (32 bits) */
5450	} DATA;
5451
5452	} BUF[64];
5453
5454	int32_t FLEXCAN_reserved0480[256]; /* 0x0480-0x087F */
5455
5456	union { /* RX Individual Mask Registers */
5457	uint32_t R;
5458	struct {
5459	uint32_t MI31:1;
5460	uint32_t MI30:1;
5461	uint32_t MI29:1;
5462	uint32_t MI28:1;
5463	uint32_t MI27:1;
5464	uint32_t MI26:1;
5465	uint32_t MI25:1;
5466	uint32_t MI24:1;
5467	uint32_t MI23:1;
5468	uint32_t MI22:1;
5469	uint32_t MI21:1;
5470	uint32_t MI20:1;
5471	uint32_t MI19:1;
5472	uint32_t MI18:1;
5473	uint32_t MI17:1;
5474	uint32_t MI16:1;
5475	uint32_t MI15:1;
5476	uint32_t MI14:1;
5477	uint32_t MI13:1;
5478	uint32_t MI12:1;
5479	uint32_t MI11:1;
5480	uint32_t MI10:1;
5481	uint32_t MI9:1;
5482	uint32_t MI8:1;
5483	uint32_t MI7:1;
5484	uint32_t MI6:1;
5485	uint32_t MI5:1;
5486	uint32_t MI4:1;
5487	uint32_t MI3:1;
5488	uint32_t MI2:1;
5489	uint32_t MI1:1;
5490	uint32_t MI0:1;
5491	} B;
5492	} RXIMR[64];
5493
5494	int32_t FLEXCAN_reserved0980[3488]; /* 0x0980-0x3FFF */
5495
5496	};
5497
5498	/****************************************************************************/
5499	/* MODULE : FlexRay */
5500	/****************************************************************************/
5501
5502	typedef union uMVR {
5503	uint16_t R;
5504	struct {
5505	uint16_t CHIVER:8; /* CHI Version Number */
5506	uint16_t PEVER:8; /* PE Version Number */
5507	} B;
5508	} MVR_t;
5509
5510	typedef union uMCR {
5511	uint16_t R;
5512	struct {
5513	uint16_t MEN:1; /* module enable */
5514	uint16_t:1;
5515	uint16_t SCMD:1; /* single channel mode */
5516	uint16_t CHB:1; /* channel B enable */
5517	uint16_t CHA:1; /* channel A enable */
5518	uint16_t SFFE:1; /* synchronization frame filter enable */
5519	uint16_t:5;
5520	uint16_t CLKSEL:1; /* protocol engine clock source select */
5521	uint16_t PRESCALE:3; /* protocol engine clock prescaler */
5522	uint16_t:1;
5523	} B;
5524	} MCR_t;
5525
5526	typedef union uSTBSCR {
5527	uint16_t R;
5528	struct {
5529	uint16_t WMD:1; /* write mode */
5530	uint16_t STBSSEL:7; /* strobe signal select */
5531	uint16_t:3;
5532	uint16_t ENB:1; /* strobe signal enable */
5533	uint16_t:2;
5534	uint16_t STBPSEL:2; /* strobe port select */
5535	} B;
5536	} STBSCR_t;
5537	typedef union uSTBPCR {
5538	uint16_t R;
5539	struct {
5540	uint16_t:12;
5541	uint16_t STB3EN:1; /* strobe port enable */
5542	uint16_t STB2EN:1; /* strobe port enable */
5543	uint16_t STB1EN:1; /* strobe port enable */
5544	uint16_t STB0EN:1; /* strobe port enable */
5545	} B;
5546	} STBPCR_t;
5547
5548	typedef union uMBDSR {
5549	uint16_t R;
5550	struct {
5551	uint16_t:1;
5552	uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
5553	uint16_t:1;
5554	uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
5555	} B;
5556	} MBDSR_t;
5557	typedef union uMBSSUTR {
5558	uint16_t R;
5559	struct {
5560
5561	uint16_t:1;
5562	uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */
5563	uint16_t:1;
5564	uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */
5565	} B;
5566	} MBSSUTR_t;
5567
5568	typedef union uPOCR {
5569	uint16_t R;
5570	uint8_t byte[2];
5571	struct {
5572	uint16_t WME:1; /* write mode external correction command */
5573	uint16_t:3;
5574	uint16_t EOC_AP:2; /* external offset correction application */
5575	uint16_t ERC_AP:2; /* external rate correction application */
5576	uint16_t BSY:1; /* command write busy / write mode command */
5577	uint16_t:3;
5578	uint16_t POCCMD:4; /* protocol command */
5579	} B;
5580	} POCR_t;
5581	/* protocol commands */
5582	typedef union uGIFER {
5583	uint16_t R;
5584	struct {
5585	uint16_t MIF:1; /* module interrupt flag */
5586	uint16_t PRIF:1; /* protocol interrupt flag */
5587	uint16_t CHIF:1; /* CHI interrupt flag */
5588	uint16_t WKUPIF:1; /* wakeup interrupt flag */
5589	uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
5590	uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
5591	uint16_t RBIF:1; /* receive message buffer interrupt flag */
5592	uint16_t TBIF:1; /* transmit buffer interrupt flag */
5593	uint16_t MIE:1; /* module interrupt enable */
5594	uint16_t PRIE:1; /* protocol interrupt enable */
5595	uint16_t CHIE:1; /* CHI interrupt enable */
5596	uint16_t WKUPIE:1; /* wakeup interrupt enable */
5597	uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
5598	uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
5599	uint16_t RBIE:1; /* receive message buffer interrupt enable */
5600	uint16_t TBIE:1; /* transmit buffer interrupt enable */
5601	} B;
5602	} GIFER_t;
5603	typedef union uPIFR0 {
5604	uint16_t R;
5605	struct {
5606	uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
5607	uint16_t INTLIF:1; /* internal protocol error interrupt flag */
5608	uint16_t ILCFIF:1; /* illegal protocol configuration flag */
5609	uint16_t CSAIF:1; /* cold start abort interrupt flag */
5610	uint16_t MRCIF:1; /* missing rate correctio interrupt flag */
5611	uint16_t MOCIF:1; /* missing offset correctio interrupt flag */
5612	uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
5613	uint16_t MXSIF:1; /* max sync frames detected interrupt flag */
5614	uint16_t MTXIF:1; /* media access test symbol received flag */
5615	uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
5616	uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
5617	uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
5618	uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
5619	uint16_t TI2IF:1; /* timer 2 expired interrupt flag */
5620	uint16_t TI1IF:1; /* timer 1 expired interrupt flag */
5621	uint16_t CYSIF:1; /* cycle start interrupt flag */
5622	} B;
5623	} PIFR0_t;
5624	typedef union uPIFR1 {
5625	uint16_t R;
5626	struct {
5627	uint16_t EMCIF:1; /* error mode changed interrupt flag */
5628	uint16_t IPCIF:1; /* illegal protocol command interrupt flag */
5629	uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
5630	uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
5631	uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
5632	uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
5633	uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
5634	uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
5635	uint16_t:2;
5636	uint16_t EVTIF:1; /* even cycle table written interrupt flag */
5637	uint16_t ODTIF:1; /* odd cycle table written interrupt flag */
5638	uint16_t:4;
5639	} B;
5640	} PIFR1_t;
5641	typedef union uPIER0 {
5642	uint16_t R;
5643	struct {
5644	uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
5645	uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
5646	uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
5647	uint16_t CSAIE:1; /* cold start abort interrupt enable */
5648	uint16_t MRCIE:1; /* missing rate correctio interrupt enable */
5649	uint16_t MOCIE:1; /* missing offset correctio interrupt enable */
5650	uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
5651	uint16_t MXSIE:1; /* max sync frames detected interrupt enable */
5652	uint16_t MTXIE:1; /* media access test symbol received interrupt enable */
5653	uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
5654	uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
5655	uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
5656	uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
5657	uint16_t TI2IE:1; /* timer 2 expired interrupt enable */
5658	uint16_t TI1IE:1; /* timer 1 expired interrupt enable */
5659	uint16_t CYSIE:1; /* cycle start interrupt enable */
5660	} B;
5661	} PIER0_t;
5662	typedef union uPIER1 {
5663	uint16_t R;
5664	struct {
5665	uint16_t EMCIE:1; /* error mode changed interrupt enable */
5666	uint16_t IPCIE:1; /* illegal protocol command interrupt enable */
5667	uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
5668	uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
5669	uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
5670	uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
5671	uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
5672	uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
5673	uint16_t:2;
5674	uint16_t EVTIE:1; /* even cycle table written interrupt enable */
5675	uint16_t ODTIE:1; /* odd cycle table written interrupt enable */
5676	uint16_t:4;
5677	} B;
5678	} PIER1_t;
5679	typedef union uCHIERFR {
5680	uint16_t R;
5681	struct {
5682	uint16_t FRLBEF:1; /* flame lost channel B error flag */
5683	uint16_t FRLAEF:1; /* frame lost channel A error flag */
5684	uint16_t PCMIEF:1; /* command ignored error flag */
5685	uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
5686	uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
5687	uint16_t MSBEF:1; /* message buffer search error flag */
5688	uint16_t MBUEF:1; /* message buffer utilization error flag */
5689	uint16_t LCKEF:1; /* lock error flag */
5690	uint16_t DBLEF:1; /* double transmit message buffer lock error flag */
5691	uint16_t SBCFEF:1; /* system bus communication failure error flag */
5692	uint16_t FIDEF:1; /* frame ID error flag */
5693	uint16_t DPLEF:1; /* dynamic payload length error flag */
5694	uint16_t SPLEF:1; /* static payload length error flag */
5695	uint16_t NMLEF:1; /* network management length error flag */
5696	uint16_t NMFEF:1; /* network management frame error flag */
5697	uint16_t ILSAEF:1; /* illegal access error flag */
5698	} B;
5699	} CHIERFR_t;
5700	typedef union uMBIVEC {
5701	uint16_t R;
5702	struct {
5703
5704	uint16_t:1;
5705	uint16_t TBIVEC:7; /* transmit buffer interrupt vector */
5706	uint16_t:1;
5707	uint16_t RBIVEC:7; /* receive buffer interrupt vector */
5708	} B;
5709	} MBIVEC_t;
5710
5711	typedef union uPSR0 {
5712	uint16_t R;
5713	struct {
5714	uint16_t ERRMODE:2; /* error mode */
5715	uint16_t SLOTMODE:2; /* slot mode */
5716	uint16_t:1;
5717	uint16_t PROTSTATE:3; /* protocol state */
5718	uint16_t SUBSTATE:4; /* protocol sub state */
5719	uint16_t:1;
5720	uint16_t WAKEUPSTATUS:3; /* wakeup status */
5721	} B;
5722	} PSR0_t;
5723
5724	/* protocol states */
5725	/* protocol sub-states */
5726	/* wakeup status */
5727	typedef union uPSR1 {
5728	uint16_t R;
5729	struct {
5730	uint16_t CSAA:1; /* cold start attempt abort flag */
5731	uint16_t SCP:1; /* cold start path */
5732	uint16_t:1;
5733	uint16_t REMCSAT:5; /* remanining coldstart attempts */
5734	uint16_t CPN:1; /* cold start noise path */
5735	uint16_t HHR:1; /* host halt request pending */
5736	uint16_t FRZ:1; /* freeze occured */
5737	uint16_t APTAC:5; /* allow passive to active counter */
5738	} B;
5739	} PSR1_t;
5740	typedef union uPSR2 {
5741	uint16_t R;
5742	struct {
5743	uint16_t NBVB:1; /* NIT boundary violation on channel B */
5744	uint16_t NSEB:1; /* NIT syntax error on channel B */
5745	uint16_t STCB:1; /* symbol window transmit conflict on channel B */
5746	uint16_t SBVB:1; /* symbol window boundary violation on channel B */
5747	uint16_t SSEB:1; /* symbol window syntax error on channel B */
5748	uint16_t MTB:1; /* media access test symbol MTS received on channel B */
5749	uint16_t NBVA:1; /* NIT boundary violation on channel A */
5750	uint16_t NSEA:1; /* NIT syntax error on channel A */
5751	uint16_t STCA:1; /* symbol window transmit conflict on channel A */
5752	uint16_t SBVA:1; /* symbol window boundary violation on channel A */
5753	uint16_t SSEA:1; /* symbol window syntax error on channel A */
5754	uint16_t MTA:1; /* media access test symbol MTS received on channel A */
5755	uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
5756	} B;
5757	} PSR2_t;
5758	typedef union uPSR3 {
5759	uint16_t R;
5760	struct {
5761	uint16_t:2;
5762	uint16_t WUB:1; /* wakeup symbol received on channel B */
5763	uint16_t ABVB:1; /* aggregated boundary violation on channel B */
5764	uint16_t AACB:1; /* aggregated additional communication on channel B */
5765	uint16_t ACEB:1; /* aggregated content error on channel B */
5766	uint16_t ASEB:1; /* aggregated syntax error on channel B */
5767	uint16_t AVFB:1; /* aggregated valid frame on channel B */
5768	uint16_t:2;
5769	uint16_t WUA:1; /* wakeup symbol received on channel A */
5770	uint16_t ABVA:1; /* aggregated boundary violation on channel A */
5771	uint16_t AACA:1; /* aggregated additional communication on channel A */
5772	uint16_t ACEA:1; /* aggregated content error on channel A */
5773	uint16_t ASEA:1; /* aggregated syntax error on channel A */
5774	uint16_t AVFA:1; /* aggregated valid frame on channel A */
5775	} B;
5776	} PSR3_t;
5777	typedef union uCIFRR {
5778	uint16_t R;
5779	struct {
5780	uint16_t:8;
5781	uint16_t MIFR:1; /* module interrupt flag */
5782	uint16_t PRIFR:1; /* protocol interrupt flag */
5783	uint16_t CHIFR:1; /* CHI interrupt flag */
5784	uint16_t WUPIFR:1; /* wakeup interrupt flag */
5785	uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
5786	uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
5787	uint16_t RBIFR:1; /* receive message buffer interrupt flag */
5788	uint16_t TBIFR:1; /* transmit buffer interrupt flag */
5789	} B;
5790	} CIFRR_t;
5791	typedef union uSFCNTR {
5792	uint16_t R;
5793	struct {
5794	uint16_t SFEVB:4; /* sync frames channel B, even cycle */
5795	uint16_t SFEVA:4; /* sync frames channel A, even cycle */
5796	uint16_t SFODB:4; /* sync frames channel B, odd cycle */
5797	uint16_t SFODA:4; /* sync frames channel A, odd cycle */
5798	} B;
5799	} SFCNTR_t;
5800
5801	typedef union uSFTCCSR {
5802	uint16_t R;
5803	struct {
5804	uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
5805	uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
5806	uint16_t CYCNUM:6; /* cycle number */
5807	uint16_t ELKS:1; /* even cycle tables lock status */
5808	uint16_t OLKS:1; /* odd cycle tables lock status */
5809	uint16_t EVAL:1; /* even cycle tables valid */
5810	uint16_t OVAL:1; /* odd cycle tables valid */
5811	uint16_t:1;
5812	uint16_t OPT:1; /one pair trigger /
5813	uint16_t SDVEN:1; /* sync frame deviation table enable */
5814	uint16_t SIDEN:1; /* sync frame ID table enable */
5815	} B;
5816	} SFTCCSR_t;
5817	typedef union uSFIDRFR {
5818	uint16_t R;
5819	struct {
5820	uint16_t:6;
5821	uint16_t SYNFRID:10; /* sync frame rejection ID */
5822	} B;
5823	} SFIDRFR_t;
5824
5825	typedef union uTICCR {
5826	uint16_t R;
5827	struct {
5828	uint16_t:2;
5829	uint16_t T2CFG:1; /* timer 2 configuration */
5830	uint16_t T2REP:1; /* timer 2 repetitive mode */
5831	uint16_t:1;
5832	uint16_t T2SP:1; /* timer 2 stop */
5833	uint16_t T2TR:1; /* timer 2 trigger */
5834	uint16_t T2ST:1; /* timer 2 state */
5835	uint16_t:3;
5836	uint16_t T1REP:1; /* timer 1 repetitive mode */
5837	uint16_t:1;
5838	uint16_t T1SP:1; /* timer 1 stop */
5839	uint16_t T1TR:1; /* timer 1 trigger */
5840	uint16_t T1ST:1; /* timer 1 state */
5841
5842	} B;
5843	} TICCR_t;
5844	typedef union uTI1CYSR {
5845	uint16_t R;
5846	struct {
5847	uint16_t:2;
5848	uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
5849	uint16_t:2;
5850	uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
5851
5852	} B;
5853	} TI1CYSR_t;
5854
5855	typedef union uSSSR {
5856	uint16_t R;
5857	struct {
5858	uint16_t WMD:1; /* write mode */
5859	uint16_t:1;
5860	uint16_t SEL:2; /* static slot number */
5861	uint16_t:1;
5862	uint16_t SLOTNUMBER:11; /* selector */
5863	} B;
5864	} SSSR_t;
5865
5866	typedef union uSSCCR {
5867	uint16_t R;
5868	struct {
5869	uint16_t WMD:1; /* write mode */
5870	uint16_t:1;
5871	uint16_t SEL:2; /* selector */
5872	uint16_t:1;
5873	uint16_t CNTCFG:2; /* counter configuration */
5874	uint16_t MCY:1; /* multi cycle selection */
5875	uint16_t VFR:1; /* valid frame selection */
5876	uint16_t SYF:1; /* sync frame selection */
5877	uint16_t NUF:1; /* null frame selection */
5878	uint16_t SUF:1; /* startup frame selection */
5879	uint16_t STATUSMASK:4; /* slot status mask */
5880	} B;
5881	} SSCCR_t;
5882	typedef union uSSR {
5883	uint16_t R;
5884	struct {
5885	uint16_t VFB:1; /* valid frame on channel B */
5886	uint16_t SYB:1; /* valid sync frame on channel B */
5887	uint16_t NFB:1; /* valid null frame on channel B */
5888	uint16_t SUB:1; /* valid startup frame on channel B */
5889	uint16_t SEB:1; /* syntax error on channel B */
5890	uint16_t CEB:1; /* content error on channel B */
5891	uint16_t BVB:1; /* boundary violation on channel B */
5892	uint16_t TCB:1; /* tx conflict on channel B */
5893	uint16_t VFA:1; /* valid frame on channel A */
5894	uint16_t SYA:1; /* valid sync frame on channel A */
5895	uint16_t NFA:1; /* valid null frame on channel A */
5896	uint16_t SUA:1; /* valid startup frame on channel A */
5897	uint16_t SEA:1; /* syntax error on channel A */
5898	uint16_t CEA:1; /* content error on channel A */
5899	uint16_t BVA:1; /* boundary violation on channel A */
5900	uint16_t TCA:1; /* tx conflict on channel A */
5901	} B;
5902	} SSR_t;
5903	typedef union uMTSCFR {
5904	uint16_t R;
5905	struct {
5906	uint16_t MTE:1; /* media access test symbol transmission enable */
5907	uint16_t:1;
5908	uint16_t CYCCNTMSK:6; /* cycle counter mask */
5909	uint16_t:2;
5910	uint16_t CYCCNTVAL:6; /* cycle counter value */
5911	} B;
5912	} MTSCFR_t;
5913	typedef union uRSBIR {
5914	uint16_t R;
5915	struct {
5916	uint16_t WMD:1; /* write mode */
5917	uint16_t:1;
5918	uint16_t SEL:2; /* selector */
5919	uint16_t:4;
5920	uint16_t RSBIDX:8; /* receive shadow buffer index */
5921	} B;
5922	} RSBIR_t;
5923	typedef union uRFDSR {
5924	uint16_t R;
5925	struct {
5926	uint16_t FIFODEPTH:8; /* fifo depth */
5927	uint16_t:1;
5928	uint16_t ENTRYSIZE:7; /* entry size */
5929	} B;
5930	} RFDSR_t;
5931
5932	typedef union uRFRFCFR {
5933	uint16_t R;
5934	struct {
5935	uint16_t WMD:1; /* write mode */
5936	uint16_t IBD:1; /* interval boundary */
5937	uint16_t SEL:2; /* filter number */
5938	uint16_t:1;
5939	uint16_t SID:11; /* slot ID */
5940	} B;
5941	} RFRFCFR_t;
5942
5943	typedef union uRFRFCTR {
5944	uint16_t R;
5945	struct {
5946	uint16_t:4;
5947	uint16_t F3MD:1; /* filter mode */
5948	uint16_t F2MD:1; /* filter mode */
5949	uint16_t F1MD:1; /* filter mode */
5950	uint16_t F0MD:1; /* filter mode */
5951	uint16_t:4;
5952	uint16_t F3EN:1; /* filter enable */
5953	uint16_t F2EN:1; /* filter enable */
5954	uint16_t F1EN:1; /* filter enable */
5955	uint16_t F0EN:1; /* filter enable */
5956	} B;
5957	} RFRFCTR_t;
5958	typedef union uPCR0 {
5959	uint16_t R;
5960	struct {
5961	uint16_t ACTION_POINT_OFFSET:6;
5962	uint16_t STATIC_SLOT_LENGTH:10;
5963	} B;
5964	} PCR0_t;
5965
5966	typedef union uPCR1 {
5967	uint16_t R;
5968	struct {
5969	uint16_t:2;
5970	uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
5971	} B;
5972	} PCR1_t;
5973
5974	typedef union uPCR2 {
5975	uint16_t R;
5976	struct {
5977	uint16_t MINISLOT_AFTER_ACTION_POINT:6;
5978	uint16_t NUMBER_OF_STATIC_SLOTS:10;
5979	} B;
5980	} PCR2_t;
5981
5982	typedef union uPCR3 {
5983	uint16_t R;
5984	struct {
5985	uint16_t WAKEUP_SYMBOL_RX_LOW:6;
5986	uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
5987	uint16_t COLDSTART_ATTEMPTS:5;
5988	} B;
5989	} PCR3_t;
5990
5991	typedef union uPCR4 {
5992	uint16_t R;
5993	struct {
5994	uint16_t CAS_RX_LOW_MAX:7;
5995	uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
5996	} B;
5997	} PCR4_t;
5998
5999	typedef union uPCR5 {
6000	uint16_t R;
6001	struct {
6002	uint16_t TSS_TRANSMITTER:4;
6003	uint16_t WAKEUP_SYMBOL_TX_LOW:6;
6004	uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
6005	} B;
6006	} PCR5_t;
6007
6008	typedef union uPCR6 {
6009	uint16_t R;
6010	struct {
6011	uint16_t:1;
6012	uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
6013	uint16_t MACRO_INITIAL_OFFSET_A:7;
6014	} B;
6015	} PCR6_t;
6016
6017	typedef union uPCR7 {
6018	uint16_t R;
6019	struct {
6020	uint16_t DECODING_CORRECTION_B:9;
6021	uint16_t MICRO_PER_MACRO_NOM_HALF:7;
6022	} B;
6023	} PCR7_t;
6024
6025	typedef union uPCR8 {
6026	uint16_t R;
6027	struct {
6028	uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
6029	uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
6030	uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
6031	} B;
6032	} PCR8_t;
6033
6034	typedef union uPCR9 {
6035	uint16_t R;
6036	struct {
6037	uint16_t MINISLOT_EXISTS:1;
6038	uint16_t SYMBOL_WINDOW_EXISTS:1;
6039	uint16_t OFFSET_CORRECTION_OUT:14;
6040	} B;
6041	} PCR9_t;
6042
6043	typedef union uPCR10 {
6044	uint16_t R;
6045	struct {
6046	uint16_t SINGLE_SLOT_ENABLED:1;
6047	uint16_t WAKEUP_CHANNEL:1;
6048	uint16_t MACRO_PER_CYCLE:14;
6049	} B;
6050	} PCR10_t;
6051
6052	typedef union uPCR11 {
6053	uint16_t R;
6054	struct {
6055	uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
6056	uint16_t KEY_SLOT_USED_FOR_SYNC:1;
6057	uint16_t OFFSET_CORRECTION_START:14;
6058	} B;
6059	} PCR11_t;
6060
6061	typedef union uPCR12 {
6062	uint16_t R;
6063	struct {
6064	uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
6065	uint16_t KEY_SLOT_HEADER_CRC:11;
6066	} B;
6067	} PCR12_t;
6068
6069	typedef union uPCR13 {
6070	uint16_t R;
6071	struct {
6072	uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
6073	uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
6074	} B;
6075	} PCR13_t;
6076
6077	typedef union uPCR14 {
6078	uint16_t R;
6079	struct {
6080	uint16_t RATE_CORRECTION_OUT:11;
6081	uint16_t LISTEN_TIMEOUT_H:5;
6082	} B;
6083	} PCR14_t;
6084
6085	typedef union uPCR15 {
6086	uint16_t R;
6087	struct {
6088	uint16_t LISTEN_TIMEOUT_L:16;
6089	} B;
6090	} PCR15_t;
6091
6092	typedef union uPCR16 {
6093	uint16_t R;
6094	struct {
6095	uint16_t MACRO_INITIAL_OFFSET_B:7;
6096	uint16_t NOISE_LISTEN_TIMEOUT_H:9;
6097	} B;
6098	} PCR16_t;
6099
6100	typedef union uPCR17 {
6101	uint16_t R;
6102	struct {
6103	uint16_t NOISE_LISTEN_TIMEOUT_L:16;
6104	} B;
6105	} PCR17_t;
6106
6107	typedef union uPCR18 {
6108	uint16_t R;
6109	struct {
6110	uint16_t WAKEUP_PATTERN:6;
6111	uint16_t KEY_SLOT_ID:10;
6112	} B;
6113	} PCR18_t;
6114
6115	typedef union uPCR19 {
6116	uint16_t R;
6117	struct {
6118	uint16_t DECODING_CORRECTION_A:9;
6119	uint16_t PAYLOAD_LENGTH_STATIC:7;
6120	} B;
6121	} PCR19_t;
6122
6123	typedef union uPCR20 {
6124	uint16_t R;
6125	struct {
6126	uint16_t MICRO_INITIAL_OFFSET_B:8;
6127	uint16_t MICRO_INITIAL_OFFSET_A:8;
6128	} B;
6129	} PCR20_t;
6130
6131	typedef union uPCR21 {
6132	uint16_t R;
6133	struct {
6134	uint16_t EXTERN_RATE_CORRECTION:3;
6135	uint16_t LATEST_TX:13;
6136	} B;
6137	} PCR21_t;
6138
6139	typedef union uPCR22 {
6140	uint16_t R;
6141	struct {
6142	uint16_t:1;
6143	uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
6144	uint16_t MICRO_PER_CYCLE_H:4;
6145	} B;
6146	} PCR22_t;
6147
6148	typedef union uPCR23 {
6149	uint16_t R;
6150	struct {
6151	uint16_t micro_per_cycle_l:16;
6152	} B;
6153	} PCR23_t;
6154
6155	typedef union uPCR24 {
6156	uint16_t R;
6157	struct {
6158	uint16_t CLUSTER_DRIFT_DAMPING:5;
6159	uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
6160	uint16_t MICRO_PER_CYCLE_MIN_H:4;
6161	} B;
6162	} PCR24_t;
6163
6164	typedef union uPCR25 {
6165	uint16_t R;
6166	struct {
6167	uint16_t MICRO_PER_CYCLE_MIN_L:16;
6168	} B;
6169	} PCR25_t;
6170
6171	typedef union uPCR26 {
6172	uint16_t R;
6173	struct {
6174	uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
6175	uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
6176	uint16_t MICRO_PER_CYCLE_MAX_H:4;
6177	} B;
6178	} PCR26_t;
6179
6180	typedef union uPCR27 {
6181	uint16_t R;
6182	struct {
6183	uint16_t MICRO_PER_CYCLE_MAX_L:16;
6184	} B;
6185	} PCR27_t;
6186
6187	typedef union uPCR28 {
6188	uint16_t R;
6189	struct {
6190	uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
6191	uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
6192	} B;
6193	} PCR28_t;
6194
6195	typedef union uPCR29 {
6196	uint16_t R;
6197	struct {
6198	uint16_t EXTERN_OFFSET_CORRECTION:3;
6199	uint16_t MINISLOTS_MAX:13;
6200	} B;
6201	} PCR29_t;
6202
6203	typedef union uPCR30 {
6204	uint16_t R;
6205	struct {
6206	uint16_t:12;
6207	uint16_t SYNC_NODE_MAX:4;
6208	} B;
6209	} PCR30_t;
6210
6211	typedef struct uMSG_BUFF_CCS {
6212	union {
6213	uint16_t R;
6214	struct {
6215	uint16_t:1;
6216	uint16_t MCM:1; /* message buffer commit mode */
6217	uint16_t MBT:1; /* message buffer type */
6218	uint16_t MTD:1; /* message buffer direction */
6219	uint16_t CMT:1; /* commit for transmission */
6220	uint16_t EDT:1; /* enable / disable trigger */
6221	uint16_t LCKT:1; /* lock request trigger */
6222	uint16_t MBIE:1; /* message buffer interrupt enable */
6223	uint16_t:3;
6224	uint16_t DUP:1; /* data updated */
6225	uint16_t DVAL:1; /* data valid */
6226	uint16_t EDS:1; /* lock status */
6227	uint16_t LCKS:1; /* enable / disable status */
6228	uint16_t MBIF:1; /* message buffer interrupt flag */
6229	} B;
6230	} MBCCSR;
6231	union {
6232	uint16_t R;
6233	struct {
6234	uint16_t MTM:1; /* message buffer transmission mode */
6235	uint16_t CHNLA:1; /* channel assignement */
6236	uint16_t CHNLB:1; /* channel assignement */
6237	uint16_t CCFE:1; /* cycle counter filter enable */
6238	uint16_t CCFMSK:6; /* cycle counter filter mask */
6239	uint16_t CCFVAL:6; /* cycle counter filter value */
6240	} B;
6241	} MBCCFR;
6242	union {
6243	uint16_t R;
6244	struct {
6245	uint16_t:5;
6246	uint16_t FID:11; /* frame ID */
6247	} B;
6248	} MBFIDR;
6249	union {
6250	uint16_t R;
6251	struct {
6252	uint16_t:8;
6253	uint16_t MBIDX:8; /* message buffer index */
6254	} B;
6255	} MBIDXR;
6256	} MSG_BUFF_CCS_t;
6257	typedef union uSYSBADHR {
6258	uint16_t R;
6259	} SYSBADHR_t;
6260	typedef union uSYSBADLR {
6261	uint16_t R;
6262	} SYSBADLR_t;
6263	typedef union uPDAR {
6264	uint16_t R;
6265	} PDAR_t;
6266	typedef union uCASERCR {
6267	uint16_t R;
6268	} CASERCR_t;
6269	typedef union uCBSERCR {
6270	uint16_t R;
6271	} CBSERCR_t;
6272	typedef union uCYCTR {
6273	uint16_t R;
6274	} CYCTR_t;
6275	typedef union uMTCTR {
6276	uint16_t R;
6277	} MTCTR_t;
6278	typedef union uSLTCTAR {
6279	uint16_t R;
6280	} SLTCTAR_t;
6281	typedef union uSLTCTBR {
6282	uint16_t R;
6283	} SLTCTBR_t;
6284	typedef union uRTCORVR {
6285	uint16_t R;
6286	} RTCORVR_t;
6287	typedef union uOFCORVR {
6288	uint16_t R;
6289	} OFCORVR_t;
6290	typedef union uSFTOR {
6291	uint16_t R;
6292	} SFTOR_t;
6293	typedef union uSFIDAFVR {
6294	uint16_t R;
6295	} SFIDAFVR_t;
6296	typedef union uSFIDAFMR {
6297	uint16_t R;
6298	} SFIDAFMR_t;
6299	typedef union uNMVR {
6300	uint16_t R;
6301	} NMVR_t;
6302	typedef union uNMVLR {
6303	uint16_t R;
6304	} NMVLR_t;
6305	typedef union uT1MTOR {
6306	uint16_t R;
6307	} T1MTOR_t;
6308	typedef union uTI2CR0 {
6309	uint16_t R;
6310	} TI2CR0_t;
6311	typedef union uTI2CR1 {
6312	uint16_t R;
6313	} TI2CR1_t;
6314	typedef union uSSCR {
6315	uint16_t R;
6316	} SSCR_t;
6317	typedef union uRFSR {
6318	uint16_t R;
6319	} RFSR_t;
6320	typedef union uRFSIR {
6321	uint16_t R;
6322	} RFSIR_t;
6323	typedef union uRFARIR {
6324	uint16_t R;
6325	} RFARIR_t;
6326	typedef union uRFBRIR {
6327	uint16_t R;
6328	} RFBRIR_t;
6329	typedef union uRFMIDAFVR {
6330	uint16_t R;
6331	} RFMIDAFVR_t;
6332	typedef union uRFMIAFMR {
6333	uint16_t R;
6334	} RFMIAFMR_t;
6335	typedef union uRFFIDRFVR {
6336	uint16_t R;
6337	} RFFIDRFVR_t;
6338	typedef union uRFFIDRFMR {
6339	uint16_t R;
6340	} RFFIDRFMR_t;
6341	typedef union uLDTXSLAR {
6342	uint16_t R;
6343	} LDTXSLAR_t;
6344	typedef union uLDTXSLBR {
6345	uint16_t R;
6346	} LDTXSLBR_t;
6347
6348	typedef struct FR_tag {
6349	volatile MVR_t MVR; /module version register //0 /
6350	volatile MCR_t MCR; /module configuration register //2 /
6351	volatile SYSBADHR_t SYSBADHR; /system memory base address high register //4 /
6352	volatile SYSBADLR_t SYSBADLR; /system memory base address low register //6 /
6353	volatile STBSCR_t STBSCR; /strobe signal control register //8 /
6354	volatile STBPCR_t STBPCR; /strobe port control register //A /
6355	volatile MBDSR_t MBDSR; /message buffer data size register //C /
6356	volatile MBSSUTR_t MBSSUTR; /message buffer segment size and utilization register //E /
6357	uint16_t reserved3a[1]; /10 /
6358	volatile PDAR_t PDAR; /PE data register //12 /
6359	volatile POCR_t POCR; /Protocol operation control register //14 /
6360	volatile GIFER_t GIFER; /global interrupt flag and enable register //16 /
6361	volatile PIFR0_t PIFR0; /protocol interrupt flag register 0 //18 /
6362	volatile PIFR1_t PIFR1; /protocol interrupt flag register 1 //1A /
6363	volatile PIER0_t PIER0; /protocol interrupt enable register 0 //1C /
6364	volatile PIER1_t PIER1; /protocol interrupt enable register 1 //1E /
6365	volatile CHIERFR_t CHIERFR; /CHI error flag register //20 /
6366	volatile MBIVEC_t MBIVEC; /message buffer interrupt vector register //22 /
6367	volatile CASERCR_t CASERCR; /channel A status error counter register //24 /
6368	volatile CBSERCR_t CBSERCR; /channel B status error counter register //26 /
6369	volatile PSR0_t PSR0; /protocol status register 0 //28 /
6370	volatile PSR1_t PSR1; /protocol status register 1 //2A /
6371	volatile PSR2_t PSR2; /protocol status register 2 //2C /
6372	volatile PSR3_t PSR3; /protocol status register 3 //2E /
6373	volatile MTCTR_t MTCTR; /macrotick counter register //30 /
6374	volatile CYCTR_t CYCTR; /cycle counter register //32 /
6375	volatile SLTCTAR_t SLTCTAR; /slot counter channel A register //34 /
6376	volatile SLTCTBR_t SLTCTBR; /slot counter channel B register //36 /
6377	volatile RTCORVR_t RTCORVR; /rate correction value register //38 /
6378	volatile OFCORVR_t OFCORVR; /offset correction value register //3A /
6379	volatile CIFRR_t CIFRR; /combined interrupt flag register //3C /
6380	uint16_t reserved3[1]; /3E /
6381	volatile SFCNTR_t SFCNTR; /sync frame counter register //40 /
6382	volatile SFTOR_t SFTOR; /sync frame table offset register //42 /
6383	volatile SFTCCSR_t SFTCCSR; /sync frame table configuration, control, status register //44 /
6384	volatile SFIDRFR_t SFIDRFR; /sync frame ID rejection filter register //46 /
6385	volatile SFIDAFVR_t SFIDAFVR; /sync frame ID acceptance filter value regiater //48 /
6386	volatile SFIDAFMR_t SFIDAFMR; /sync frame ID acceptance filter mask register //4A /
6387	volatile NMVR_t NMVR[6]; /network management vector registers (12 bytes) //4C /
6388	volatile NMVLR_t NMVLR; /network management vector length register //58 /
6389	volatile TICCR_t TICCR; /timer configuration and control register //5A /
6390	volatile TI1CYSR_t TI1CYSR; /timer 1 cycle set register //5C /
6391	volatile T1MTOR_t T1MTOR; /timer 1 macrotick offset register //5E /
6392	volatile TI2CR0_t TI2CR0; /timer 2 configuration register 0 //60 /
6393	volatile TI2CR1_t TI2CR1; /timer 2 configuration register 1 //62 /
6394	volatile SSSR_t SSSR; /slot status selection register //64 /
6395	volatile SSCCR_t SSCCR; /slot status counter condition register //66 /
6396	volatile SSR_t SSR[8]; /slot status registers 0-7 //68 /
6397	volatile SSCR_t SSCR[4]; /slot status counter registers 0-3 //78 /
6398	volatile MTSCFR_t MTSACFR; /mts a config register //80 /
6399	volatile MTSCFR_t MTSBCFR; /mts b config register //82 /
6400	volatile RSBIR_t RSBIR; /receive shadow buffer index register //84 /
6401	volatile RFSR_t RFSR; /receive fifo selection register //86 /
6402	volatile RFSIR_t RFSIR; /receive fifo start index register //88 /
6403	volatile RFDSR_t RFDSR; /receive fifo depth and size register //8A /
6404	volatile RFARIR_t RFARIR; /receive fifo a read index register //8C /
6405	volatile RFBRIR_t RFBRIR; /receive fifo b read index register //8E /
6406	volatile RFMIDAFVR_t RFMIDAFVR; /receive fifo message ID acceptance filter value register //90 /
6407	volatile RFMIAFMR_t RFMIAFMR; /receive fifo message ID acceptance filter mask register //92 /
6408	volatile RFFIDRFVR_t RFFIDRFVR; /receive fifo frame ID rejection filter value register //94 /
6409	volatile RFFIDRFMR_t RFFIDRFMR; /receive fifo frame ID rejection filter mask register //96 /
6410	volatile RFRFCFR_t RFRFCFR; /receive fifo range filter configuration register //98 /
6411	volatile RFRFCTR_t RFRFCTR; /receive fifo range filter control register //9A /
6412	volatile LDTXSLAR_t LDTXSLAR; /last dynamic transmit slot channel A register //9C /
6413	volatile LDTXSLBR_t LDTXSLBR; /last dynamic transmit slot channel B register //9E /
6414	volatile PCR0_t PCR0; /protocol configuration register 0 //A0 /
6415	volatile PCR1_t PCR1; /protocol configuration register 1 //A2 /
6416	volatile PCR2_t PCR2; /protocol configuration register 2 //A4 /
6417	volatile PCR3_t PCR3; /protocol configuration register 3 //A6 /
6418	volatile PCR4_t PCR4; /protocol configuration register 4 //A8 /
6419	volatile PCR5_t PCR5; /protocol configuration register 5 //AA /
6420	volatile PCR6_t PCR6; /protocol configuration register 6 //AC /
6421	volatile PCR7_t PCR7; /protocol configuration register 7 //AE /
6422	volatile PCR8_t PCR8; /protocol configuration register 8 //B0 /
6423	volatile PCR9_t PCR9; /protocol configuration register 9 //B2 /
6424	volatile PCR10_t PCR10; /protocol configuration register 10 //B4 /
6425	volatile PCR11_t PCR11; /protocol configuration register 11 //B6 /
6426	volatile PCR12_t PCR12; /protocol configuration register 12 //B8 /
6427	volatile PCR13_t PCR13; /protocol configuration register 13 //BA /
6428	volatile PCR14_t PCR14; /protocol configuration register 14 //BC /
6429	volatile PCR15_t PCR15; /protocol configuration register 15 //BE /
6430	volatile PCR16_t PCR16; /protocol configuration register 16 //C0 /
6431	volatile PCR17_t PCR17; /protocol configuration register 17 //C2 /
6432	volatile PCR18_t PCR18; /protocol configuration register 18 //C4 /
6433	volatile PCR19_t PCR19; /protocol configuration register 19 //C6 /
6434	volatile PCR20_t PCR20; /protocol configuration register 20 //C8 /
6435	volatile PCR21_t PCR21; /protocol configuration register 21 //CA /
6436	volatile PCR22_t PCR22; /protocol configuration register 22 //CC /
6437	volatile PCR23_t PCR23; /protocol configuration register 23 //CE /
6438	volatile PCR24_t PCR24; /protocol configuration register 24 //D0 /
6439	volatile PCR25_t PCR25; /protocol configuration register 25 //D2 /
6440	volatile PCR26_t PCR26; /protocol configuration register 26 //D4 /
6441	volatile PCR27_t PCR27; /protocol configuration register 27 //D6 /
6442	volatile PCR28_t PCR28; /protocol configuration register 28 //D8 /
6443	volatile PCR29_t PCR29; /protocol configuration register 29 //DA /
6444	volatile PCR30_t PCR30; /protocol configuration register 30 //DC /
6445	uint16_t reserved2[17];
6446	volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 //100 */
6447	} FR_tag_t;
6448
6449	typedef union uF_HEADER /* frame header */
6450	{
6451	struct {
6452	uint16_t:5;
6453	uint16_t HDCRC:11; /* Header CRC */
6454	uint16_t:2;
6455	uint16_t CYCCNT:6; /* Cycle Count */
6456	uint16_t:1;
6457	uint16_t PLDLEN:7; /* Payload Length */
6458	uint16_t:1;
6459	uint16_t PPI:1; /* Payload Preamble Indicator */
6460	uint16_t NUF:1; /* Null Frame Indicator */
6461	uint16_t SYF:1; /* Sync Frame Indicator */
6462	uint16_t SUF:1; /* Startup Frame Indicator */
6463	uint16_t FID:11; /* Frame ID */
6464	} B;
6465	uint16_t WORDS[3];
6466	} F_HEADER_t;
6467	typedef union uS_STSTUS /* slot status */
6468	{
6469	struct {
6470	uint16_t VFB:1; /* Valid Frame on channel B */
6471	uint16_t SYB:1; /* Sync Frame Indicator channel B */
6472	uint16_t NFB:1; /* Null Frame Indicator channel B */
6473	uint16_t SUB:1; /* Startup Frame Indicator channel B */
6474	uint16_t SEB:1; /* Syntax Error on channel B */
6475	uint16_t CEB:1; /* Content Error on channel B */
6476	uint16_t BVB:1; /* Boundary Violation on channel B */
6477	uint16_t CH:1; /* Channel */
6478	uint16_t VFA:1; /* Valid Frame on channel A */
6479	uint16_t SYA:1; /* Sync Frame Indicator channel A */
6480	uint16_t NFA:1; /* Null Frame Indicator channel A */
6481	uint16_t SUA:1; /* Startup Frame Indicator channel A */
6482	uint16_t SEA:1; /* Syntax Error on channel A */
6483	uint16_t CEA:1; /* Content Error on channel A */
6484	uint16_t BVA:1; /* Boundary Violation on channel A */
6485	uint16_t:1;
6486	} RX;
6487	struct {
6488	uint16_t VFB:1; /* Valid Frame on channel B */
6489	uint16_t SYB:1; /* Sync Frame Indicator channel B */
6490	uint16_t NFB:1; /* Null Frame Indicator channel B */
6491	uint16_t SUB:1; /* Startup Frame Indicator channel B */
6492	uint16_t SEB:1; /* Syntax Error on channel B */
6493	uint16_t CEB:1; /* Content Error on channel B */
6494	uint16_t BVB:1; /* Boundary Violation on channel B */
6495	uint16_t TCB:1; /* Tx Conflict on channel B */
6496	uint16_t VFA:1; /* Valid Frame on channel A */
6497	uint16_t SYA:1; /* Sync Frame Indicator channel A */
6498	uint16_t NFA:1; /* Null Frame Indicator channel A */
6499	uint16_t SUA:1; /* Startup Frame Indicator channel A */
6500	uint16_t SEA:1; /* Syntax Error on channel A */
6501	uint16_t CEA:1; /* Content Error on channel A */
6502	uint16_t BVA:1; /* Boundary Violation on channel A */
6503	uint16_t TCA:1; /* Tx Conflict on channel A */
6504	} TX;
6505	uint16_t R;
6506	} S_STATUS_t;
6507
6508	typedef struct uMB_HEADER /* message buffer header */
6509	{
6510	F_HEADER_t FRAME_HEADER;
6511	uint16_t DATA_OFFSET;
6512	S_STATUS_t SLOT_STATUS;
6513	} MB_HEADER_t;
6514
6515	/* Define memories */
6516
6517	#define SRAM_START 0x40000000
6518	#define SRAM_SIZE 0x40000
6519	#define SRAM_END 0x4003FFFF
6520
6521	#define FLASH_START 0x00000000
6522	#define FLASH_SIZE 0x400000
6523	#define FLASH_END 0x003FFFFF
6524
6525	/* Define instances of modules */
6526	#define PBRIDGE_A (( volatile struct PBRIDGE_A_tag ) 0xC3F00000)
6527	#define FMPLL (( volatile struct FMPLL_tag ) 0xC3F80000)
6528	#define EBI (( volatile struct EBI_tag ) 0xC3F84000)
6529	#define FLASH_A (( volatile struct FLASH_tag ) 0xC3F88000)
6530	#define FLASH FLASH_A
6531	#define FLASH_B (( volatile struct FLASH_tag ) 0xC3F8C000)
6532	#define SIU (( volatile struct SIU_tag ) 0xC3F90000)
6533
6534	#define EMIOS (( volatile struct EMIOS_tag ) 0xC3FA0000)
6535	#define PMC (( volatile struct PMC_tag ) 0xC3FBC000)
6536
6537	#define ETPU (( volatile struct ETPU_tag ) 0xC3FC0000)
6538	#define ETPU_DATA_RAM (( uint32_t ) 0xC3FC8000)
6539	#define ETPU_DATA_RAM_END 0xC3FC8FFC
6540	#define ETPU_DATA_RAM_EXT (( uint32_t ) 0xC3FCC000)
6541	#define CODE_RAM (( uint32_t ) 0xC3FD0000)
6542	#define ETPU_CODE_RAM (( uint32_t ) 0xC3FD0000)
6543
6544	#define PIT (( volatile struct PIT_tag ) 0xC3FF0000)
6545
6546	#define PBRIDGE_B (( volatile struct PBRIDGE_B_tag ) 0xFFF00000)
6547	#define XBAR (( volatile struct XBAR_tag ) 0xFFF04000)
6548	#define MPU (( volatile struct MPU_tag ) 0xFFF10000)
6549	#define SWT (( volatile struct SWT_tag ) 0xFFF38000)
6550	#define STM (( volatile struct STM_tag ) 0xFFF3C000)
6551	#define ECSM (( volatile struct ECSM_tag ) 0xFFF40000)
6552	#define EDMA_A (( volatile struct EDMA_tag ) 0xFFF44000)
6553	#define EDMA EDMA_A
6554	#define INTC (( volatile struct INTC_tag ) 0xFFF48000)
6555	#define EDMA_B (( volatile struct EDMA_tag ) 0xFFF54000)
6556
6557	#define EQADC_A (( volatile struct EQADC_tag ) 0xFFF80000)
6558	#define EQADC_B (( volatile struct EQADC_tag ) 0xFFF84000)
6559
6560	#define DECFIL_A (( volatile struct DECFIL_tag ) 0xFFF88000)
6561	#define DECFIL_B (( volatile struct DECFIL_tag ) 0xFFF88800)
6562	#define DECFIL_C (( volatile struct DECFIL_tag ) 0xFFF89000)
6563	#define DECFIL_D (( volatile struct DECFIL_tag ) 0xFFF89800)
6564	#define DECFIL_E (( volatile struct DECFIL_tag ) 0xFFF8A000)
6565	#define DECFIL_F (( volatile struct DECFIL_tag ) 0xFFF8A800)
6566	#define DECFIL_G (( volatile struct DECFIL_tag ) 0xFFF8B000)
6567	#define DECFIL_H (( volatile struct DECFIL_tag ) 0xFFF8B800)
6568
6569	#define DSPI_A (( volatile struct DSPI_tag ) 0xFFF90000)
6570	#define DSPI_B (( volatile struct DSPI_tag ) 0xFFF94000)
6571	#define DSPI_C (( volatile struct DSPI_tag ) 0xFFF98000)
6572	#define DSPI_D (( volatile struct DSPI_tag ) 0xFFF9C000)
6573
6574	#define ESCI_A (( volatile struct ESCI_tag ) 0xFFFB0000)
6575	#define ESCI_B (( volatile struct ESCI_tag ) 0xFFFB4000)
6576	#define ESCI_C (( volatile struct ESCI_tag ) 0xFFFB8000)
6577	#define ESCI_D (( volatile struct ESCI_tag ) 0xFFFBC000)
6578
6579	#define CAN_A (( volatile struct FLEXCAN2_tag ) 0xFFFC0000)
6580	#define CAN_B (( volatile struct FLEXCAN2_tag ) 0xFFFC4000)
6581	#define CAN_C (( volatile struct FLEXCAN2_tag ) 0xFFFC8000)
6582	#define CAN_D (( volatile struct FLEXCAN2_tag ) 0xFFFCC000)
6583
6584	#define FR (( volatile struct FR_tag ) 0xFFFE0000)
6585	#define TSENS (( volatile struct TSENS_tag ) 0xFFFEC000)
6586
6587	#ifdef __MWERKS__
6588	#pragma pop
6589	#endif
6590
6591	#ifdef __cplusplus
6592	}
6593	#endif
6594	#endif /* ifdef _MPC5674_H */
6595	/*********************************************************************
6596	*
6597	* Copyright:
6598	* Freescale Semiconductor, INC. All Rights Reserved.
6599	* You are hereby granted a copyright license to use, modify, and
6600	* distribute the SOFTWARE so long as this entire notice is
6601	* retained without alteration in any modified and/or redistributed
6602	* versions, and that such modified versions are clearly identified
6603	* as such. No licenses are granted by implication, estoppel or
6604	* otherwise under any patents or trademarks of Freescale
6605	* Semiconductor, Inc. This software is provided on an "AS IS"
6606	* basis and without warranty.
6607	*
6608	* To the maximum extent permitted by applicable law, Freescale
6609	* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
6610	* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
6611	* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
6612	* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
6613	* AND ANY ACCOMPANYING WRITTEN MATERIALS.
6614	*
6615	* To the maximum extent permitted by applicable law, IN NO EVENT
6616	* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
6617	* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
6618	* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
6619	* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
6620	*
6621	* Freescale Semiconductor assumes no responsibility for the
6622	* maintenance and support of this software
6623	*
6624	********************************************************************/

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