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source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h @ 7a84689f

4.115

Last change on this file since 7a84689f was 7a84689f, checked in by Sebastian Huber <sebastian.huber@…>, on 09/01/11 at 08:09:28

2011-09-01 Sebastian Huber <sebastian.huber@…>

mpc55xx/include/fsl-mpc551x.h, mpc55xx/include/fsl-mpc556x.h, mpc55xx/include/fsl-mpc567x.h: Added missing FLASH types.

Property mode set to 100644

File size: 156.7 KB

Line
1	/*
2	* Modifications of the original file provided by Freescale are:
3	*
4	* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
5	*
6	* embedded brains GmbH
7	* Obere Lagerstr. 30
8	* 82178 Puchheim
9	* Germany
10	* <info@embedded-brains.de>
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	*
21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32	*/
33
34	/**************************************************************************/
35	/* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */
36	/* VERSION: 1.5 All Rights Reserved */
37	/* */
38	/* DESCRIPTION: */
39	/* This file contain all of the register and bit field definitions for */
40	/* MPC5567. */
41	/========================================================================/
42	/* UPDATE HISTORY */
43	/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
44	/* --- ----------- --------- --------------------- */
45	/* 1.0 G. Emerson 03/Jan/06 Initial version. */
46	/* 1.1 G. Emerson 27/Mar/06 Fix issue with Flexcan BCC field. */
47	/* 1.2 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */
48	/* Add Flexcan bits WRNEN, SRXDIS, */
49	/* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */
50	/* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */
51	/* to DPB to align with documentation. */
52	/* 1.4 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */
53	/* alternate configuration. */
54	/* INTC, correction to the number of PSR */
55	/* registers. */
56	/* Updates to bitfield sizes in MBSSUTR, */
57	/* MBIVEC, MBIDX & RSBIR. RSBIR, SELEC */
58	/* changed to SEL & RFRFCFR, FNUM changed */
59	/* to SEL to align with documentation. */
60	/* Various register/ bitfield updates to */
61	/* correct errors (MCR, TMODE bit removed.*/
62	/* PADR register removed. PIER1, DRDIE bit*/
63	/* removed & PIFR1, DRDIF removed. PCR1, */
64	/* Filter bypass bit removed). */
65	/* 1.5 S. Mathieson 25/Apr/07 SRAM size changed from 64K to 80K. */
66	/* */
67	/**************************************************************************/
68	/>>>>NOTE! this file is auto-generated please do not edit it!<<<</
69
70	#ifndef _MPC5567_H_
71	#define _MPC5567_H_
72
73	#include <stdint.h>
74
75	#include <mpc55xx/regs-edma.h>
76
77	#ifdef __cplusplus
78	extern "C" {
79	#endif
80
81	#ifdef __MWERKS__
82	#pragma push
83	#pragma ANSI_strict off
84	#endif
85
86	/****************************************************************************/
87	/* MODULE : PBRIDGE_A Peripheral Bridge */
88	/****************************************************************************/
89	struct PBRIDGE_A_tag {
90	union {
91	uint32_t R;
92	struct {
93	uint32_t MBW0:1;
94	uint32_t MTR0:1;
95	uint32_t MTW0:1;
96	uint32_t MPL0:1;
97	uint32_t MBW1:1;
98	uint32_t MTR1:1;
99	uint32_t MTW1:1;
100	uint32_t MPL1:1;
101	uint32_t MBW2:1;
102	uint32_t MTR2:1;
103	uint32_t MTW2:1;
104	uint32_t MPL2:1;
105	uint32_t MBW3:1;
106	uint32_t MTR3:1;
107	uint32_t MTW3:1;
108	uint32_t MPL3:1;
109
110	uint32_t MBW4:1; /* FEC */
111	uint32_t MTR4:1;
112	uint32_t MTW4:1;
113	uint32_t MPL4:1;
114
115	uint32_t:4;
116
117	uint32_t MBW6:1; /* FLEXRAY */
118	uint32_t MTR6:1;
119	uint32_t MTW6:1;
120	uint32_t MPL6:1;
121
122	uint32_t:4;
123	} B;
124	} MPCR; /* Master Privilege Control Register */
125
126	uint32_t pbridge_a_reserved2[7];
127
128	union {
129	uint32_t R;
130	struct {
131	uint32_t BW0:1;
132	uint32_t SP0:1;
133	uint32_t WP0:1;
134	uint32_t TP0:1;
135	uint32_t:28;
136	} B;
137	} PACR0;
138
139	uint32_t pbridge_a_reserved3[7];
140
141	union {
142	uint32_t R;
143	struct {
144	uint32_t BW0:1;
145	uint32_t SP0:1;
146	uint32_t WP0:1;
147	uint32_t TP0:1;
148	uint32_t BW1:1;
149	uint32_t SP1:1;
150	uint32_t WP1:1;
151	uint32_t TP1:1;
152	uint32_t BW2:1;
153	uint32_t SP2:1;
154	uint32_t WP2:1;
155	uint32_t TP2:1;
156	uint32_t:4;
157	uint32_t BW4:1;
158	uint32_t SP4:1;
159	uint32_t WP4:1;
160	uint32_t TP4:1;
161	uint32_t:12;
162	} B;
163	} OPACR0;
164
165	union {
166	uint32_t R;
167	struct {
168
169	uint32_t BW0:1; /* EMIOS */
170	uint32_t SP0:1;
171	uint32_t WP0:1;
172	uint32_t TP0:1;
173
174	uint32_t:28;
175	} B;
176	} OPACR1;
177
178	union {
179	uint32_t R;
180	struct {
181	uint32_t BW0:1;
182	uint32_t SP0:1;
183	uint32_t WP0:1;
184	uint32_t TP0:1;
185	uint32_t:4;
186	uint32_t BW2:1;
187	uint32_t SP2:1;
188	uint32_t WP2:1;
189	uint32_t TP2:1;
190	uint32_t BW3:1;
191	uint32_t SP3:1;
192	uint32_t WP3:1;
193	uint32_t TP3:1;
194	uint32_t BW4:1;
195	uint32_t SP4:1;
196	uint32_t WP4:1;
197	uint32_t TP4:1;
198	uint32_t:12;
199	} B;
200	} OPACR2;
201
202	};
203
204	/****************************************************************************/
205	/* MODULE : PBRIDGE_B Peripheral Bridge */
206	/****************************************************************************/
207	struct PBRIDGE_B_tag {
208	union {
209	uint32_t R;
210	struct {
211	uint32_t MBW0:1;
212	uint32_t MTR0:1;
213	uint32_t MTW0:1;
214	uint32_t MPL0:1;
215	uint32_t MBW1:1;
216	uint32_t MTR1:1;
217	uint32_t MTW1:1;
218	uint32_t MPL1:1;
219	uint32_t MBW2:1;
220	uint32_t MTR2:1;
221	uint32_t MTW2:1;
222	uint32_t MPL2:1;
223	uint32_t MBW3:1;
224	uint32_t MTR3:1;
225	uint32_t MTW3:1;
226	uint32_t MPL3:1;
227
228	uint32_t MBW4:1; /* FEC */
229	uint32_t MTR4:1;
230	uint32_t MTW4:1;
231	uint32_t MPL4:1;
232
233	uint32_t:4;
234
235	uint32_t MBW6:1; /* FLEXRAY */
236	uint32_t MTR6:1;
237	uint32_t MTW6:1;
238	uint32_t MPL6:1;
239
240	uint32_t:4;
241	} B;
242	} MPCR; /* Master Privilege Control Register */
243
244	uint32_t pbridge_b_reserved2[7];
245
246	union {
247	uint32_t R;
248	struct {
249	uint32_t BW0:1;
250	uint32_t SP0:1;
251	uint32_t WP0:1;
252	uint32_t TP0:1;
253	uint32_t BW1:1;
254	uint32_t SP1:1;
255	uint32_t WP1:1;
256	uint32_t TP1:1;
257	uint32_t:24;
258	} B;
259	} PACR0;
260
261	uint32_t pbridge_b_reserved3;
262
263	union {
264	uint32_t R;
265	struct {
266	uint32_t BW0:1;
267	uint32_t SP0:1;
268	uint32_t WP0:1;
269	uint32_t TP0:1;
270	uint32_t BW1:1;
271	uint32_t SP1:1;
272	uint32_t WP1:1;
273	uint32_t TP1:1;
274	uint32_t BW2:1;
275	uint32_t SP2:1;
276	uint32_t WP2:1;
277	uint32_t TP2:1;
278
279	uint32_t BW3:1; /* FEC */
280	uint32_t SP3:1;
281	uint32_t WP3:1;
282	uint32_t TP3:1;
283
284	uint32_t:16;
285
286	} B;
287	} PACR2;
288
289	uint32_t pbridge_b_reserved4[5];
290
291	union {
292	uint32_t R;
293	struct {
294	uint32_t BW0:1;
295	uint32_t SP0:1;
296	uint32_t WP0:1;
297	uint32_t TP0:1;
298	uint32_t:12;
299
300	uint32_t:4;
301
302	uint32_t BW5:1; /* DSPI_B */
303	uint32_t SP5:1;
304	uint32_t WP5:1;
305	uint32_t TP5:1;
306
307	uint32_t BW6:1;
308	uint32_t SP6:1;
309	uint32_t WP6:1;
310	uint32_t TP6:1;
311	uint32_t BW7:1;
312	uint32_t SP7:1;
313	uint32_t WP7:1;
314	uint32_t TP7:1;
315	} B;
316	} OPACR0;
317
318	union {
319	uint32_t R;
320	struct {
321	uint32_t:16;
322	uint32_t BW4:1;
323	uint32_t SP4:1;
324	uint32_t WP4:1;
325	uint32_t TP4:1;
326
327	uint32_t BW5:1; /* ESCI_B */
328	uint32_t SP5:1;
329	uint32_t WP5:1;
330	uint32_t TP5:1;
331
332	uint32_t:8;
333	} B;
334	} OPACR1;
335
336	union {
337	uint32_t R;
338	struct {
339	uint32_t BW0:1;
340	uint32_t SP0:1;
341	uint32_t WP0:1;
342	uint32_t TP0:1;
343
344	uint32_t BW1:1; /* CAN_B */
345	uint32_t SP1:1;
346	uint32_t WP1:1;
347	uint32_t TP1:1;
348
349	uint32_t BW2:1;
350	uint32_t SP2:1;
351	uint32_t WP2:1;
352	uint32_t TP2:1;
353
354	uint32_t BW3:1; /* CAN_D */
355	uint32_t SP3:1;
356	uint32_t WP3:1;
357	uint32_t TP3:1;
358
359	uint32_t BW4:1; /* CAN_E */
360	uint32_t SP4:1;
361	uint32_t WP4:1;
362	uint32_t TP4:1;
363
364	uint32_t:12;
365	} B;
366	} OPACR2;
367
368	union {
369	uint32_t R;
370	struct {
371
372	uint32_t BW0:1; /* FLEXRAY */
373	uint32_t SP0:1;
374	uint32_t WP0:1;
375	uint32_t TP0:1;
376
377	uint32_t:24;
378	uint32_t BW7:1;
379	uint32_t SP7:1;
380	uint32_t WP7:1;
381	uint32_t TP7:1;
382	} B;
383	} OPACR3;
384
385	};
386	/****************************************************************************/
387	/* MODULE : FMPLL */
388	/****************************************************************************/
389	struct FMPLL_tag {
390	union FMPLL_SYNCR_tag {
391	uint32_t R;
392	struct {
393	uint32_t:1;
394	uint32_t PREDIV:3;
395	uint32_t MFD:5;
396	uint32_t:1;
397	uint32_t RFD:3;
398	uint32_t LOCEN:1;
399	uint32_t LOLRE:1;
400	uint32_t LOCRE:1;
401	uint32_t DISCLK:1;
402	uint32_t LOLIRQ:1;
403	uint32_t LOCIRQ:1;
404	uint32_t RATE:1;
405	uint32_t DEPTH:2;
406	uint32_t EXP:10;
407	} B;
408	} SYNCR;
409
410	union FMPLL_SYNSR_tag {
411	uint32_t R;
412	struct {
413	uint32_t:22;
414	uint32_t LOLF:1;
415	uint32_t LOC:1;
416	uint32_t MODE:1;
417	uint32_t PLLSEL:1;
418	uint32_t PLLREF:1;
419	uint32_t LOCKS:1;
420	uint32_t LOCK:1;
421	uint32_t LOCF:1;
422	uint32_t CALDONE:1;
423	uint32_t CALPASS:1;
424	} B;
425	} SYNSR;
426
427	};
428	/****************************************************************************/
429	/* MODULE : External Bus Interface (EBI) */
430	/****************************************************************************/
431	struct EBI_CS_tag {
432	union { /* Base Register Bank */
433	uint32_t R;
434	struct {
435	uint32_t BA:17;
436	uint32_t:3;
437	uint32_t PS:1;
438	uint32_t:4;
439	uint32_t BL:1;
440	uint32_t WEBS:1;
441	uint32_t TBDIP:1;
442	uint32_t:2;
443	uint32_t BI:1;
444	uint32_t V:1;
445	} B;
446	} BR;
447
448	union { /* Option Register Bank */
449	uint32_t R;
450	struct {
451	uint32_t AM:17;
452	uint32_t:7;
453	uint32_t SCY:4;
454	uint32_t:1;
455	uint32_t BSCY:2;
456	uint32_t:1;
457	} B;
458	} OR;
459	};
460
461	struct EBI_CAL_CS_tag {
462	union { /* Calibration Base Register Bank */
463	uint32_t R;
464	struct {
465	uint32_t BA:17;
466	uint32_t:3;
467	uint32_t PS:1;
468	uint32_t:4;
469	uint32_t BL:1;
470	uint32_t WEBS:1;
471	uint32_t TBDIP:1;
472	uint32_t:2;
473	uint32_t BI:1;
474	uint32_t V:1;
475	} B;
476	} BR;
477
478	union { /* Calibration Option Register Bank */
479	uint32_t R;
480	struct {
481	uint32_t AM:17;
482	uint32_t:7;
483	uint32_t SCY:4;
484	uint32_t:1;
485	uint32_t BSCY:2;
486	uint32_t:1;
487	} B;
488	} OR;
489	};
490
491	struct EBI_tag {
492	union { /* Module Configuration Register */
493	uint32_t R;
494	struct {
495	uint32_t:5;
496	uint32_t SIZEEN:1;
497	uint32_t SIZE:2;
498	uint32_t:8;
499	uint32_t ACGE:1;
500	uint32_t EXTM:1;
501	uint32_t EARB:1;
502	uint32_t EARP:2;
503	uint32_t:4;
504	uint32_t MDIS:1;
505	uint32_t:5;
506	uint32_t DBM:1;
507	} B;
508	} MCR;
509
510	uint32_t EBI_reserved1;
511
512	union { /* Transfer Error Status Register */
513	uint32_t R;
514	struct {
515	uint32_t:30;
516	uint32_t TEAF:1;
517	uint32_t BMTF:1;
518	} B;
519	} TESR;
520
521	union { /* Bus Monitor Control Register */
522	uint32_t R;
523	struct {
524	uint32_t:16;
525	uint32_t BMT:8;
526	uint32_t BME:1;
527	uint32_t:7;
528	} B;
529	} BMCR;
530
531	struct EBI_CS_tag CS[4];
532
533	/* Calibration registers */
534	uint32_t EBI_reserved2[4];
535	struct EBI_CAL_CS_tag CAL_CS[4];
536
537	};
538	/****************************************************************************/
539	/* MODULE : FLASH */
540	/****************************************************************************/
541	struct FLASH_tag {
542	union { /* Module Configuration Register */
543	uint32_t R;
544	struct {
545	uint32_t:4;
546	uint32_t SIZE:4;
547	uint32_t:1;
548	uint32_t LAS:3;
549	uint32_t:3;
550	uint32_t MAS:1;
551	uint32_t EER:1;
552	uint32_t RWE:1;
553	uint32_t BBEPE:1;
554	uint32_t EPE:1;
555	uint32_t PEAS:1;
556	uint32_t DONE:1;
557	uint32_t PEG:1;
558
559	uint32_t:2;
560
561	uint32_t STOP:1;
562	uint32_t:1;
563	uint32_t PGM:1;
564	uint32_t PSUS:1;
565	uint32_t ERS:1;
566	uint32_t ESUS:1;
567	uint32_t EHV:1;
568	} B;
569	} MCR;
570
571	union LMLR_tag { /* LML Register */
572	uint32_t R;
573	struct {
574	uint32_t LME:1;
575	uint32_t:10;
576	uint32_t SLOCK:1;
577	uint32_t MLOCK:4;
578	uint32_t LLOCK:16;
579	} B;
580	} LMLR;
581
582	union HLR_tag { /* HL Register */
583	uint32_t R;
584	struct {
585	uint32_t HBE:1;
586	uint32_t:3;
587	uint32_t HBLOCK:28;
588	} B;
589	} HLR;
590
591	union SLMLR_tag { /* SLML Register */
592	uint32_t R;
593	struct {
594	uint32_t SLE:1;
595	uint32_t:10;
596	uint32_t SSLOCK:1;
597	uint32_t SMLOCK:4;
598	uint32_t SLLOCK:16;
599	} B;
600	} SLMLR;
601
602	union { /* LMS Register */
603	uint32_t R;
604	struct {
605	uint32_t:12;
606	uint32_t MSEL:4;
607	uint32_t LSEL:16;
608	} B;
609	} LMSR;
610
611	union {
612	uint32_t R;
613	struct {
614	uint32_t:4;
615	uint32_t HBSEL:28;
616	} B;
617	} HSR;
618
619	union {
620	uint32_t R;
621	struct {
622	uint32_t:10;
623	uint32_t ADDR:19;
624	uint32_t:3;
625	} B;
626	} AR;
627
628	union {
629	uint32_t R;
630	struct {
631
632	uint32_t:9;
633	uint32_t M6PFE:1; /* Flexray */
634	uint32_t:1;
635
636	uint32_t M4PFE:1; /* FEC */
637
638	uint32_t M3PFE:1;
639	uint32_t M2PFE:1;
640	uint32_t M1PFE:1;
641	uint32_t M0PFE:1;
642	uint32_t APC:3;
643	uint32_t WWSC:2;
644	uint32_t RWSC:3;
645
646	uint32_t DPFEN:2;
647	uint32_t IPFEN:2;
648
649	uint32_t PFLIM:3;
650	uint32_t BFEN:1;
651	} B;
652	} BIUCR;
653
654	union {
655	uint32_t R;
656	struct {
657
658	uint32_t:18;
659	uint32_t M6AP:2; /* Flexray */
660	uint32_t:2;
661
662	uint32_t M4AP:2; /* FEC */
663
664	uint32_t M3AP:2;
665	uint32_t M2AP:2;
666	uint32_t M1AP:2;
667	uint32_t M0AP:2;
668	} B;
669	} BIUAPR;
670	};
671	/****************************************************************************/
672	/* MODULE : SIU */
673	/****************************************************************************/
674	struct SIU_tag {
675	int32_t SIU_reserved0;
676
677	union { /* MCU ID Register */
678	uint32_t R;
679	struct {
680	uint32_t PARTNUM:16;
681	uint32_t MASKNUM:16;
682	} B;
683	} MIDR;
684	int32_t SIU_reserved00;
685
686	union { /* Reset Status Register */
687	uint32_t R;
688	struct {
689	uint32_t PORS:1;
690	uint32_t ERS:1;
691	uint32_t LLRS:1;
692	uint32_t LCRS:1;
693	uint32_t WDRS:1;
694	uint32_t CRS:1;
695	uint32_t:8;
696	uint32_t SSRS:1;
697	uint32_t SERF:1;
698	uint32_t WKPCFG:1;
699	uint32_t:12;
700	uint32_t BOOTCFG:2;
701	uint32_t RGF:1;
702	} B;
703	} RSR;
704
705	union { /* System Reset Control Register */
706	uint32_t R;
707	struct {
708	uint32_t SSR:1;
709	uint32_t SER:1;
710	uint32_t:14;
711	uint32_t CRE:1;
712	uint32_t:15;
713	} B;
714	} SRCR;
715
716	union SIU_EISR_tag { /* External Interrupt Status Register */
717	uint32_t R;
718	struct {
719	uint32_t:16;
720	uint32_t EIF15:1;
721	uint32_t EIF14:1;
722	uint32_t EIF13:1;
723	uint32_t EIF12:1;
724	uint32_t EIF11:1;
725	uint32_t EIF10:1;
726	uint32_t EIF9:1;
727	uint32_t EIF8:1;
728	uint32_t EIF7:1;
729	uint32_t EIF6:1;
730	uint32_t EIF5:1;
731	uint32_t EIF4:1;
732	uint32_t EIF3:1;
733	uint32_t EIF2:1;
734	uint32_t EIF1:1;
735	uint32_t EIF0:1;
736	} B;
737	} EISR;
738
739	union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
740	uint32_t R;
741	struct {
742	uint32_t:16;
743	uint32_t EIRE15:1;
744	uint32_t EIRE14:1;
745	uint32_t EIRE13:1;
746	uint32_t EIRE12:1;
747	uint32_t EIRE11:1;
748	uint32_t EIRE10:1;
749	uint32_t EIRE9:1;
750	uint32_t EIRE8:1;
751	uint32_t EIRE7:1;
752	uint32_t EIRE6:1;
753	uint32_t EIRE5:1;
754	uint32_t EIRE4:1;
755	uint32_t EIRE3:1;
756	uint32_t EIRE2:1;
757	uint32_t EIRE1:1;
758	uint32_t EIRE0:1;
759	} B;
760	} DIRER;
761
762	union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */
763	uint32_t R;
764	struct {
765	uint32_t:28;
766	uint32_t DIRS3:1;
767	uint32_t DIRS2:1;
768	uint32_t DIRS1:1;
769	uint32_t DIRS0:1;
770	} B;
771	} DIRSR;
772
773	union { /* Overrun Status Register */
774	uint32_t R;
775	struct {
776	uint32_t:16;
777	uint32_t OVF15:1;
778	uint32_t OVF14:1;
779	uint32_t OVF13:1;
780	uint32_t OVF12:1;
781	uint32_t OVF11:1;
782	uint32_t OVF10:1;
783	uint32_t OVF9:1;
784	uint32_t OVF8:1;
785	uint32_t OVF7:1;
786	uint32_t OVF6:1;
787	uint32_t OVF5:1;
788	uint32_t OVF4:1;
789	uint32_t OVF3:1;
790	uint32_t OVF2:1;
791	uint32_t OVF1:1;
792	uint32_t OVF0:1;
793	} B;
794	} OSR;
795
796	union SIU_ORER_tag { /* Overrun Request Enable Register */
797	uint32_t R;
798	struct {
799	uint32_t:16;
800	uint32_t ORE15:1;
801	uint32_t ORE14:1;
802	uint32_t ORE13:1;
803	uint32_t ORE12:1;
804	uint32_t ORE11:1;
805	uint32_t ORE10:1;
806	uint32_t ORE9:1;
807	uint32_t ORE8:1;
808	uint32_t ORE7:1;
809	uint32_t ORE6:1;
810	uint32_t ORE5:1;
811	uint32_t ORE4:1;
812	uint32_t ORE3:1;
813	uint32_t ORE2:1;
814	uint32_t ORE1:1;
815	uint32_t ORE0:1;
816	} B;
817	} ORER;
818
819	union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
820	uint32_t R;
821	struct {
822	uint32_t:16;
823	uint32_t IREE15:1;
824	uint32_t IREE14:1;
825	uint32_t IREE13:1;
826	uint32_t IREE12:1;
827	uint32_t IREE11:1;
828	uint32_t IREE10:1;
829	uint32_t IREE9:1;
830	uint32_t IREE8:1;
831	uint32_t IREE7:1;
832	uint32_t IREE6:1;
833	uint32_t IREE5:1;
834	uint32_t IREE4:1;
835	uint32_t IREE3:1;
836	uint32_t IREE2:1;
837	uint32_t IREE1:1;
838	uint32_t IREE0:1;
839	} B;
840	} IREER;
841
842	union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
843	uint32_t R;
844	struct {
845	uint32_t:16;
846	uint32_t IFEE15:1;
847	uint32_t IFEE14:1;
848	uint32_t IFEE13:1;
849	uint32_t IFEE12:1;
850	uint32_t IFEE11:1;
851	uint32_t IFEE10:1;
852	uint32_t IFEE9:1;
853	uint32_t IFEE8:1;
854	uint32_t IFEE7:1;
855	uint32_t IFEE6:1;
856	uint32_t IFEE5:1;
857	uint32_t IFEE4:1;
858	uint32_t IFEE3:1;
859	uint32_t IFEE2:1;
860	uint32_t IFEE1:1;
861	uint32_t IFEE0:1;
862	} B;
863	} IFEER;
864
865	union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
866	uint32_t R;
867	struct {
868	uint32_t:28;
869	uint32_t DFL:4;
870	} B;
871	} IDFR;
872
873	int32_t SIU_reserved1[3];
874
875	union SIU_PCR_tag { /* Pad Configuration Registers */
876	uint16_t R;
877	struct {
878	uint16_t:3;
879	uint16_t PA:3;
880	uint16_t OBE:1;
881	uint16_t IBE:1;
882	uint16_t DSC:2;
883	uint16_t ODE:1;
884	uint16_t HYS:1;
885	uint16_t SRC:2;
886	uint16_t WPE:1;
887	uint16_t WPS:1;
888	} B;
889	} PCR[512];
890
891	int16_t SIU_reserved_0[224];
892
893	union { /* GPIO Pin Data Output Registers */
894	uint8_t R;
895	struct {
896	uint8_t:7;
897	uint8_t PDO:1;
898	} B;
899	} GPDO[256];
900
901	int32_t SIU_reserved_3[64];
902
903	union { /* GPIO Pin Data Input Registers */
904	uint8_t R;
905	struct {
906	uint8_t:7;
907	uint8_t PDI:1;
908	} B;
909	} GPDI[256];
910
911	union { /* IMUX Register */
912	uint32_t R;
913	struct {
914	uint32_t TSEL5:2;
915	uint32_t TSEL4:2;
916	uint32_t TSEL3:2;
917	uint32_t TSEL2:2;
918	uint32_t TSEL1:2;
919	uint32_t TSEL0:2;
920	uint32_t:20;
921	} B;
922	} ETISR;
923
924	union { /* IMUX Register */
925	uint32_t R;
926	struct {
927	uint32_t ESEL15:2;
928	uint32_t ESEL14:2;
929	uint32_t ESEL13:2;
930	uint32_t ESEL12:2;
931	uint32_t ESEL11:2;
932	uint32_t ESEL10:2;
933	uint32_t ESEL9:2;
934	uint32_t ESEL8:2;
935	uint32_t ESEL7:2;
936	uint32_t ESEL6:2;
937	uint32_t ESEL5:2;
938	uint32_t ESEL4:2;
939	uint32_t ESEL3:2;
940	uint32_t ESEL2:2;
941	uint32_t ESEL1:2;
942	uint32_t ESEL0:2;
943	} B;
944	} EIISR;
945
946	union { /* IMUX Register */
947	uint32_t R;
948	struct {
949	uint32_t SINSELA:2;
950	uint32_t SSSELA:2;
951	uint32_t SCKSELA:2;
952	uint32_t TRIGSELA:2;
953	uint32_t SINSELB:2;
954	uint32_t SSSELB:2;
955	uint32_t SCKSELB:2;
956	uint32_t TRIGSELB:2;
957	uint32_t SINSELC:2;
958	uint32_t SSSELC:2;
959	uint32_t SCKSELC:2;
960	uint32_t TRIGSELC:2;
961	uint32_t SINSELD:2;
962	uint32_t SSSELD:2;
963	uint32_t SCKSELD:2;
964	uint32_t TRIGSELD:2;
965	} B;
966	} DISR;
967
968	int32_t SIU_reserved2[29];
969
970	union { /* Chip Configuration Register Register */
971	uint32_t R;
972	struct {
973	uint32_t:14;
974	uint32_t MATCH:1;
975	uint32_t DISNEX:1;
976	uint32_t:16;
977	} B;
978	} CCR;
979
980	union { /* External Clock Configuration Register Register */
981	uint32_t R;
982	struct {
983	uint32_t:18;
984	uint32_t ENGDIV:6;
985	uint32_t:4;
986	uint32_t EBTS:1;
987	uint32_t:1;
988	uint32_t EBDF:2;
989	} B;
990	} ECCR;
991
992	union {
993	uint32_t R;
994	} CARH;
995
996	union {
997	uint32_t R;
998	} CARL;
999
1000	union {
1001	uint32_t R;
1002	} CBRH;
1003
1004	union {
1005	uint32_t R;
1006	} CBRL;
1007
1008	};
1009	/****************************************************************************/
1010	/* MODULE : EMIOS */
1011	/****************************************************************************/
1012	struct EMIOS_tag {
1013	union EMIOS_MCR_tag {
1014	uint32_t R;
1015	struct {
1016	uint32_t:1;
1017	uint32_t MDIS:1;
1018	uint32_t FRZ:1;
1019	uint32_t GTBE:1;
1020	uint32_t ETB:1;
1021	uint32_t GPREN:1;
1022	uint32_t:6;
1023	uint32_t SRV:4;
1024	uint32_t GPRE:8;
1025	uint32_t:8;
1026	} B;
1027	} MCR; /* Module Configuration Register */
1028
1029	union {
1030	uint32_t R;
1031	struct {
1032	uint32_t:8;
1033	uint32_t F23:1;
1034	uint32_t F22:1;
1035	uint32_t F21:1;
1036	uint32_t F20:1;
1037	uint32_t F19:1;
1038	uint32_t F18:1;
1039	uint32_t F17:1;
1040	uint32_t F16:1;
1041	uint32_t F15:1;
1042	uint32_t F14:1;
1043	uint32_t F13:1;
1044	uint32_t F12:1;
1045	uint32_t F11:1;
1046	uint32_t F10:1;
1047	uint32_t F9:1;
1048	uint32_t F8:1;
1049	uint32_t F7:1;
1050	uint32_t F6:1;
1051	uint32_t F5:1;
1052	uint32_t F4:1;
1053	uint32_t F3:1;
1054	uint32_t F2:1;
1055	uint32_t F1:1;
1056	uint32_t F0:1;
1057	} B;
1058	} GFR; /* Global FLAG Register */
1059
1060	union {
1061	uint32_t R;
1062	struct {
1063	uint32_t:8;
1064	uint32_t OU23:1;
1065	uint32_t OU22:1;
1066	uint32_t OU21:1;
1067	uint32_t OU20:1;
1068	uint32_t OU19:1;
1069	uint32_t OU18:1;
1070	uint32_t OU17:1;
1071	uint32_t OU16:1;
1072	uint32_t OU15:1;
1073	uint32_t OU14:1;
1074	uint32_t OU13:1;
1075	uint32_t OU12:1;
1076	uint32_t OU11:1;
1077	uint32_t OU10:1;
1078	uint32_t OU9:1;
1079	uint32_t OU8:1;
1080	uint32_t OU7:1;
1081	uint32_t OU6:1;
1082	uint32_t OU5:1;
1083	uint32_t OU4:1;
1084	uint32_t OU3:1;
1085	uint32_t OU2:1;
1086	uint32_t OU1:1;
1087	uint32_t OU0:1;
1088	} B;
1089	} OUDR; /* Output Update Disable Register */
1090
1091	uint32_t emios_reserved[5];
1092
1093	struct EMIOS_CH_tag {
1094	union {
1095	uint32_t R; /* Channel A Data Register */
1096	} CADR;
1097
1098	union {
1099	uint32_t R; /* Channel B Data Register */
1100	} CBDR;
1101
1102	union {
1103	uint32_t R; /* Channel Counter Register */
1104	} CCNTR;
1105
1106	union EMIOS_CCR_tag {
1107	uint32_t R;
1108	struct {
1109	uint32_t FREN:1;
1110	uint32_t ODIS:1;
1111	uint32_t ODISSL:2;
1112	uint32_t UCPRE:2;
1113	uint32_t UCPREN:1;
1114	uint32_t DMA:1;
1115	uint32_t:1;
1116	uint32_t IF:4;
1117	uint32_t FCK:1;
1118	uint32_t FEN:1;
1119	uint32_t:3;
1120	uint32_t FORCMA:1;
1121	uint32_t FORCMB:1;
1122	uint32_t:1;
1123	uint32_t BSL:2;
1124	uint32_t EDSEL:1;
1125	uint32_t EDPOL:1;
1126	uint32_t MODE:7;
1127	} B;
1128	} CCR; /* Channel Control Register */
1129
1130	union EMIOS_CSR_tag {
1131	uint32_t R;
1132	struct {
1133	uint32_t OVR:1;
1134	uint32_t:15;
1135	uint32_t OVFL:1;
1136	uint32_t:12;
1137	uint32_t UCIN:1;
1138	uint32_t UCOUT:1;
1139	uint32_t FLAG:1;
1140	} B;
1141	} CSR; /* Channel Status Register */
1142
1143	union {
1144	uint32_t R; /* Alternate Channel A Data Register */
1145	} ALTCADR;
1146
1147	uint32_t emios_channel_reserved[2];
1148
1149	} CH[24];
1150
1151	};
1152	/****************************************************************************/
1153	/* MODULE :ETPU */
1154	/****************************************************************************/
1155
1156	/*************************Configuration Registers************************/
1157
1158	struct ETPU_tag {
1159	union { /* MODULE CONFIGURATION REGISTER */
1160	uint32_t R;
1161	struct {
1162	uint32_t GEC:1; /* Global Exception Clear */
1163	uint32_t:3;
1164	uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
1165
1166	uint32_t:1; /* For single ETPU implementations */
1167
1168	uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
1169
1170	uint32_t:1; /* For single ETPU implementations */
1171
1172	uint32_t:3;
1173	uint32_t SCMSIZE:5; /* Shared Code Memory size */
1174	uint32_t:5;
1175	uint32_t SCMMISF:1; /* SCM MISC Flag */
1176	uint32_t SCMMISEN:1; /* SCM MISC Enable */
1177	uint32_t:2;
1178	uint32_t VIS:1; /* SCM Visability */
1179	uint32_t:5;
1180	uint32_t GTBE:1; /* Global Time Base Enable */
1181	} B;
1182	} MCR;
1183
1184	union { /* COHERENT DUAL-PARAMETER CONTROL */
1185	uint32_t R;
1186	struct {
1187	uint32_t STS:1; /* Start Status bit */
1188	uint32_t CTBASE:5; /* Channel Transfer Base */
1189	uint32_t PBASE:10; /* Parameter Buffer Base Address */
1190	uint32_t PWIDTH:1; /* Parameter Width */
1191	uint32_t PARAM0:7; /* Channel Parameter 0 */
1192	uint32_t WR:1;
1193	uint32_t PARAM1:7; /* Channel Parameter 1 */
1194	} B;
1195	} CDCR;
1196
1197	uint32_t etpu_reserved1;
1198
1199	union { /* MISC Compare Register */
1200	uint32_t R;
1201	} MISCCMPR;
1202
1203	union { /* SCM off-range Date Register */
1204	uint32_t R;
1205	} SCMOFFDATAR;
1206
1207	union { /* ETPU_A Configuration Register */
1208	uint32_t R;
1209	struct {
1210	uint32_t FEND:1; /* Force END */
1211	uint32_t MDIS:1; /* Low power Stop */
1212	uint32_t:1;
1213	uint32_t STF:1; /* Stop Flag */
1214	uint32_t:4;
1215	uint32_t HLTF:1; /* Halt Mode Flag */
1216	uint32_t:4;
1217	uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1218	uint32_t CDFC:2;
1219	uint32_t:9;
1220	uint32_t ETB:5; /* Entry Table Base */
1221	} B;
1222	} ECR_A;
1223	uint32_t etpu_reserved3; /* For single ETPU implementations */
1224
1225	uint32_t etpu_reserved4;
1226
1227	union { /* ETPU_A Timebase Configuration Register */
1228	uint32_t R;
1229	struct {
1230	uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1231	uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1232	uint32_t:1;
1233	uint32_t AM:1; /* Angle Mode */
1234	uint32_t:3;
1235	uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1236	uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1237	uint32_t:6;
1238	uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1239	} B;
1240	} TBCR_A;
1241
1242	union { /* ETPU_A TCR1 Visibility Register */
1243	uint32_t R;
1244	} TB1R_A;
1245
1246	union { /* ETPU_A TCR2 Visibility Register */
1247	uint32_t R;
1248	} TB2R_A;
1249
1250	union { /* ETPU_A STAC Configuration Register */
1251	uint32_t R;
1252	struct {
1253	uint32_t REN1:1; /* Resource Enable TCR1 */
1254	uint32_t RSC1:1; /* Resource Control TCR1 */
1255	uint32_t:2;
1256	uint32_t SERVER_ID1:4;
1257	uint32_t:4;
1258	uint32_t SRV1:4; /* Resource Server Slot */
1259	uint32_t REN2:1; /* Resource Enable TCR2 */
1260	uint32_t RSC2:1; /* Resource Control TCR2 */
1261	uint32_t:2;
1262	uint32_t SERVER_ID2:4;
1263	uint32_t:4;
1264	uint32_t SRV2:4; /* Resource Server Slot */
1265	} B;
1266	} REDCR_A;
1267
1268	uint32_t etpu_reserved5[4];
1269	uint32_t etpu_reserved6[4]; /* For single ETPU implementations */
1270
1271	uint32_t etpu_reserved7[108];
1272
1273	/***************************Status and Control Registers************************/
1274
1275	union { /* ETPU_A Channel Interrut Status */
1276	uint32_t R;
1277	struct {
1278	uint32_t CIS31:1; /* Channel 31 Interrut Status */
1279	uint32_t CIS30:1; /* Channel 30 Interrut Status */
1280	uint32_t CIS29:1; /* Channel 29 Interrut Status */
1281	uint32_t CIS28:1; /* Channel 28 Interrut Status */
1282	uint32_t CIS27:1; /* Channel 27 Interrut Status */
1283	uint32_t CIS26:1; /* Channel 26 Interrut Status */
1284	uint32_t CIS25:1; /* Channel 25 Interrut Status */
1285	uint32_t CIS24:1; /* Channel 24 Interrut Status */
1286	uint32_t CIS23:1; /* Channel 23 Interrut Status */
1287	uint32_t CIS22:1; /* Channel 22 Interrut Status */
1288	uint32_t CIS21:1; /* Channel 21 Interrut Status */
1289	uint32_t CIS20:1; /* Channel 20 Interrut Status */
1290	uint32_t CIS19:1; /* Channel 19 Interrut Status */
1291	uint32_t CIS18:1; /* Channel 18 Interrut Status */
1292	uint32_t CIS17:1; /* Channel 17 Interrut Status */
1293	uint32_t CIS16:1; /* Channel 16 Interrut Status */
1294	uint32_t CIS15:1; /* Channel 15 Interrut Status */
1295	uint32_t CIS14:1; /* Channel 14 Interrut Status */
1296	uint32_t CIS13:1; /* Channel 13 Interrut Status */
1297	uint32_t CIS12:1; /* Channel 12 Interrut Status */
1298	uint32_t CIS11:1; /* Channel 11 Interrut Status */
1299	uint32_t CIS10:1; /* Channel 10 Interrut Status */
1300	uint32_t CIS9:1; /* Channel 9 Interrut Status */
1301	uint32_t CIS8:1; /* Channel 8 Interrut Status */
1302	uint32_t CIS7:1; /* Channel 7 Interrut Status */
1303	uint32_t CIS6:1; /* Channel 6 Interrut Status */
1304	uint32_t CIS5:1; /* Channel 5 Interrut Status */
1305	uint32_t CIS4:1; /* Channel 4 Interrut Status */
1306	uint32_t CIS3:1; /* Channel 3 Interrut Status */
1307	uint32_t CIS2:1; /* Channel 2 Interrut Status */
1308	uint32_t CIS1:1; /* Channel 1 Interrut Status */
1309	uint32_t CIS0:1; /* Channel 0 Interrut Status */
1310	} B;
1311	} CISR_A;
1312	uint32_t etpu_reserved8; /* For single ETPU implementations */
1313
1314	uint32_t etpu_reserved9[2];
1315
1316	union { /* ETPU_A Data Transfer Request Status */
1317	uint32_t R;
1318	struct {
1319	uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1320	uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1321	uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1322	uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1323	uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1324	uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1325	uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1326	uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1327	uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1328	uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1329	uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1330	uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1331	uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1332	uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1333	uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1334	uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1335	uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1336	uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1337	uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1338	uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1339	uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1340	uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1341	uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1342	uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1343	uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1344	uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1345	uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1346	uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1347	uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1348	uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1349	uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1350	uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1351	} B;
1352	} CDTRSR_A;
1353	uint32_t etpu_reserved10; /* For single ETPU implementations */
1354
1355	uint32_t etpu_reserved11[2];
1356
1357	union { /* ETPU_A Interruput Overflow Status */
1358	uint32_t R;
1359	struct {
1360	uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1361	uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1362	uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1363	uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1364	uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1365	uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1366	uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1367	uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1368	uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1369	uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1370	uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1371	uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1372	uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1373	uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1374	uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1375	uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1376	uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1377	uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1378	uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1379	uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1380	uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1381	uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1382	uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1383	uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1384	uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1385	uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1386	uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1387	uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1388	uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1389	uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1390	uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1391	uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1392	} B;
1393	} CIOSR_A;
1394	uint32_t etpu_reserved12; /* For single ETPU implementations */
1395
1396	uint32_t etpu_reserved13[2];
1397
1398	union { /* ETPU_A Data Transfer Overflow Status */
1399	uint32_t R;
1400	struct {
1401	uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1402	uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1403	uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1404	uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1405	uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1406	uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1407	uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1408	uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1409	uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1410	uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1411	uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1412	uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1413	uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1414	uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1415	uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1416	uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1417	uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1418	uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1419	uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1420	uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1421	uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1422	uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1423	uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1424	uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1425	uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1426	uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1427	uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1428	uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1429	uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1430	uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1431	uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1432	uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1433	} B;
1434	} CDTROSR_A;
1435	uint32_t etpu_reserved14; /* For single ETPU implementations */
1436
1437	uint32_t etpu_reserved15[2];
1438
1439	union { /* ETPU_A Channel Interruput Enable */
1440	uint32_t R;
1441	struct {
1442	uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1443	uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1444	uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1445	uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1446	uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1447	uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1448	uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1449	uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1450	uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1451	uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1452	uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1453	uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1454	uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1455	uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1456	uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1457	uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1458	uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1459	uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1460	uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1461	uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1462	uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1463	uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1464	uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1465	uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1466	uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1467	uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1468	uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1469	uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1470	uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1471	uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1472	uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1473	uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1474	} B;
1475	} CIER_A;
1476	uint32_t etpu_reserved16; /* For single ETPU implementations */
1477
1478	uint32_t etpu_reserved17[2];
1479
1480	union { /* ETPU_A Channel Data Transfer Request Enable */
1481	uint32_t R;
1482	struct {
1483	uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1484	uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1485	uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1486	uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1487	uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1488	uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1489	uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1490	uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1491	uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1492	uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1493	uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1494	uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1495	uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1496	uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1497	uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1498	uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1499	uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1500	uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1501	uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1502	uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1503	uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1504	uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1505	uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1506	uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1507	uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1508	uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1509	uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1510	uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1511	uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1512	uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1513	uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1514	uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1515	} B;
1516	} CDTRER_A;
1517	uint32_t etpu_reserved19; /* For single ETPU implementations */
1518
1519	uint32_t etpu_reserved20[10];
1520	union { /* ETPU_A Channel Pending Service Status */
1521	uint32_t R;
1522	struct {
1523	uint32_t SR31:1; /* Channel 31 Pending Service Status */
1524	uint32_t SR30:1; /* Channel 30 Pending Service Status */
1525	uint32_t SR29:1; /* Channel 29 Pending Service Status */
1526	uint32_t SR28:1; /* Channel 28 Pending Service Status */
1527	uint32_t SR27:1; /* Channel 27 Pending Service Status */
1528	uint32_t SR26:1; /* Channel 26 Pending Service Status */
1529	uint32_t SR25:1; /* Channel 25 Pending Service Status */
1530	uint32_t SR24:1; /* Channel 24 Pending Service Status */
1531	uint32_t SR23:1; /* Channel 23 Pending Service Status */
1532	uint32_t SR22:1; /* Channel 22 Pending Service Status */
1533	uint32_t SR21:1; /* Channel 21 Pending Service Status */
1534	uint32_t SR20:1; /* Channel 20 Pending Service Status */
1535	uint32_t SR19:1; /* Channel 19 Pending Service Status */
1536	uint32_t SR18:1; /* Channel 18 Pending Service Status */
1537	uint32_t SR17:1; /* Channel 17 Pending Service Status */
1538	uint32_t SR16:1; /* Channel 16 Pending Service Status */
1539	uint32_t SR15:1; /* Channel 15 Pending Service Status */
1540	uint32_t SR14:1; /* Channel 14 Pending Service Status */
1541	uint32_t SR13:1; /* Channel 13 Pending Service Status */
1542	uint32_t SR12:1; /* Channel 12 Pending Service Status */
1543	uint32_t SR11:1; /* Channel 11 Pending Service Status */
1544	uint32_t SR10:1; /* Channel 10 Pending Service Status */
1545	uint32_t SR9:1; /* Channel 9 Pending Service Status */
1546	uint32_t SR8:1; /* Channel 8 Pending Service Status */
1547	uint32_t SR7:1; /* Channel 7 Pending Service Status */
1548	uint32_t SR6:1; /* Channel 6 Pending Service Status */
1549	uint32_t SR5:1; /* Channel 5 Pending Service Status */
1550	uint32_t SR4:1; /* Channel 4 Pending Service Status */
1551	uint32_t SR3:1; /* Channel 3 Pending Service Status */
1552	uint32_t SR2:1; /* Channel 2 Pending Service Status */
1553	uint32_t SR1:1; /* Channel 1 Pending Service Status */
1554	uint32_t SR0:1; /* Channel 0 Pending Service Status */
1555	} B;
1556	} CPSSR_A;
1557	uint32_t etpu_reserved22; /* For single ETPU implementations */
1558
1559	uint32_t etpu_reserved20a[2];
1560
1561	union { /* ETPU_A Channel Service Status */
1562	uint32_t R;
1563	struct {
1564	uint32_t SS31:1; /* Channel 31 Service Status */
1565	uint32_t SS30:1; /* Channel 30 Service Status */
1566	uint32_t SS29:1; /* Channel 29 Service Status */
1567	uint32_t SS28:1; /* Channel 28 Service Status */
1568	uint32_t SS27:1; /* Channel 27 Service Status */
1569	uint32_t SS26:1; /* Channel 26 Service Status */
1570	uint32_t SS25:1; /* Channel 25 Service Status */
1571	uint32_t SS24:1; /* Channel 24 Service Status */
1572	uint32_t SS23:1; /* Channel 23 Service Status */
1573	uint32_t SS22:1; /* Channel 22 Service Status */
1574	uint32_t SS21:1; /* Channel 21 Service Status */
1575	uint32_t SS20:1; /* Channel 20 Service Status */
1576	uint32_t SS19:1; /* Channel 19 Service Status */
1577	uint32_t SS18:1; /* Channel 18 Service Status */
1578	uint32_t SS17:1; /* Channel 17 Service Status */
1579	uint32_t SS16:1; /* Channel 16 Service Status */
1580	uint32_t SS15:1; /* Channel 15 Service Status */
1581	uint32_t SS14:1; /* Channel 14 Service Status */
1582	uint32_t SS13:1; /* Channel 13 Service Status */
1583	uint32_t SS12:1; /* Channel 12 Service Status */
1584	uint32_t SS11:1; /* Channel 11 Service Status */
1585	uint32_t SS10:1; /* Channel 10 Service Status */
1586	uint32_t SS9:1; /* Channel 9 Service Status */
1587	uint32_t SS8:1; /* Channel 8 Service Status */
1588	uint32_t SS7:1; /* Channel 7 Service Status */
1589	uint32_t SS6:1; /* Channel 6 Service Status */
1590	uint32_t SS5:1; /* Channel 5 Service Status */
1591	uint32_t SS4:1; /* Channel 4 Service Status */
1592	uint32_t SS3:1; /* Channel 3 Service Status */
1593	uint32_t SS2:1; /* Channel 2 Service Status */
1594	uint32_t SS1:1; /* Channel 1 Service Status */
1595	uint32_t SS0:1; /* Channel 0 Service Status */
1596	} B;
1597	} CSSR_A;
1598	uint32_t etpu_reserved22a; /* For single ETPU implementations */
1599
1600	uint32_t etpu_reserved23[90];
1601
1602	/***************************Channels******************************/
1603
1604	struct {
1605	union {
1606	uint32_t R; /* Channel Configuration Register */
1607	struct {
1608	uint32_t CIE:1; /* Channel Interruput Enable */
1609	uint32_t DTRE:1; /* Data Transfer Request Enable */
1610	uint32_t CPR:2; /* Channel Priority */
1611	uint32_t:3;
1612	uint32_t ETCS:1; /* Entry Table Condition Select */
1613	uint32_t:3;
1614	uint32_t CFS:5; /* Channel Function Select */
1615	uint32_t ODIS:1; /* Output disable */
1616	uint32_t OPOL:1; /* output polarity */
1617	uint32_t:3;
1618	uint32_t CPBA:11; /* Channel Parameter Base Address */
1619	} B;
1620	} CR;
1621	union {
1622	uint32_t R; /* Channel Status Control Register */
1623	struct {
1624	uint32_t CIS:1; /* Channel Interruput Status */
1625	uint32_t CIOS:1; /* Channel Interruput Overflow Status */
1626	uint32_t:6;
1627	uint32_t DTRS:1; /* Data Transfer Status */
1628	uint32_t DTROS:1; /* Data Transfer Overflow Status */
1629	uint32_t:6;
1630	uint32_t IPS:1; /* Input Pin State */
1631	uint32_t OPS:1; /* Output Pin State */
1632	uint32_t OBE:1; /* Output Buffer Enable */
1633	uint32_t:11;
1634	uint32_t FM1:1; /* Function mode */
1635	uint32_t FM0:1; /* Function mode */
1636	} B;
1637	} SCR;
1638	union {
1639	uint32_t R; /* Channel Host Service Request Register */
1640	struct {
1641	uint32_t:29; /* Host Service Request */
1642	uint32_t HSR:3;
1643	} B;
1644	} HSRR;
1645	uint32_t etpu_reserved23;
1646	} CHAN[127];
1647
1648	};
1649	/****************************************************************************/
1650	/* MODULE : XBAR CrossBar */
1651	/****************************************************************************/
1652	struct XBAR_tag {
1653	union {
1654	uint32_t R;
1655	struct {
1656	uint32_t:4;
1657
1658	uint32_t:1;
1659	uint32_t MSTR6:3; /* FLEXRAY */
1660
1661	uint32_t:4;
1662
1663	uint32_t:4;
1664
1665	uint32_t:1;
1666	uint32_t MSTR3:3; /* FEC */
1667
1668	uint32_t:1;
1669	uint32_t MSTR2:3;
1670	uint32_t:1;
1671	uint32_t MSTR1:3;
1672	uint32_t:1;
1673	uint32_t MSTR0:3;
1674	} B;
1675	} MPR0; /* Master Priority Register for Slave Port 0 */
1676
1677	uint32_t xbar_reserved1[3];
1678
1679	union {
1680	uint32_t R;
1681	struct {
1682	uint32_t RO:1;
1683	uint32_t:21;
1684	uint32_t ARB:2;
1685	uint32_t:2;
1686	uint32_t PCTL:2;
1687	uint32_t:1;
1688	uint32_t PARK:3;
1689	} B;
1690	} SGPCR0; /* General Purpose Control Register for Slave Port 0 */
1691
1692	uint32_t xbar_reserved2[59];
1693
1694	union {
1695	uint32_t R;
1696	struct {
1697	uint32_t:4;
1698
1699	uint32_t:1;
1700	uint32_t MSTR6:3; /* FLEXRAY */
1701
1702	uint32_t:4;
1703
1704	uint32_t:4;
1705
1706	uint32_t:1;
1707	uint32_t MSTR3:3; /* FEC */
1708
1709	uint32_t:1;
1710	uint32_t MSTR2:3;
1711	uint32_t:1;
1712	uint32_t MSTR1:3;
1713	uint32_t:1;
1714	uint32_t MSTR0:3;
1715	} B;
1716	} MPR1; /* Master Priority Register for Slave Port 1 */
1717
1718	uint32_t xbar_reserved3[3];
1719
1720	union {
1721	uint32_t R;
1722	struct {
1723	uint32_t RO:1;
1724	uint32_t:21;
1725	uint32_t ARB:2;
1726	uint32_t:2;
1727	uint32_t PCTL:2;
1728	uint32_t:1;
1729	uint32_t PARK:3;
1730	} B;
1731	} SGPCR1; /* General Purpose Control Register for Slave Port 1 */
1732
1733	uint32_t xbar_reserved4[123];
1734
1735	union {
1736	uint32_t R;
1737	struct {
1738	uint32_t:4;
1739
1740	uint32_t:1;
1741	uint32_t MSTR6:3; /* FLEXRAY */
1742
1743	uint32_t:4;
1744
1745	uint32_t:4;
1746
1747	uint32_t:1;
1748	uint32_t MSTR3:3; /* FEC */
1749
1750	uint32_t:1;
1751	uint32_t MSTR2:3;
1752	uint32_t:1;
1753	uint32_t MSTR1:3;
1754	uint32_t:1;
1755	uint32_t MSTR0:3;
1756	} B;
1757	} MPR3; /* Master Priority Register for Slave Port 3 */
1758
1759	uint32_t xbar_reserved5[3];
1760
1761	union {
1762	uint32_t R;
1763	struct {
1764	uint32_t RO:1;
1765	uint32_t:21;
1766	uint32_t ARB:2;
1767	uint32_t:2;
1768	uint32_t PCTL:2;
1769	uint32_t:1;
1770	uint32_t PARK:3;
1771	} B;
1772	} SGPCR3; /* General Purpose Control Register for Slave Port 3 */
1773	uint32_t xbar_reserved6[187];
1774
1775	union {
1776	uint32_t R;
1777	struct {
1778	uint32_t:4;
1779
1780	uint32_t:1;
1781	uint32_t MSTR6:3; /* FLEXRAY */
1782
1783	uint32_t:4;
1784
1785	uint32_t:4;
1786
1787	uint32_t:1;
1788	uint32_t MSTR3:3; /* FEC */
1789
1790	uint32_t:1;
1791	uint32_t MSTR2:3;
1792	uint32_t:1;
1793	uint32_t MSTR1:3;
1794	uint32_t:1;
1795	uint32_t MSTR0:3;
1796	} B;
1797	} MPR6; /* Master Priority Register for Slave Port 6 */
1798
1799	uint32_t xbar_reserved7[3];
1800
1801	union {
1802	uint32_t R;
1803	struct {
1804	uint32_t RO:1;
1805	uint32_t:21;
1806	uint32_t ARB:2;
1807	uint32_t:2;
1808	uint32_t PCTL:2;
1809	uint32_t:1;
1810	uint32_t PARK:3;
1811	} B;
1812	} SGPCR6; /* General Purpose Control Register for Slave Port 6 */
1813
1814	uint32_t xbar_reserved8[59];
1815
1816	union {
1817	uint32_t R;
1818	struct {
1819	uint32_t:4;
1820
1821	uint32_t:1;
1822	uint32_t MSTR6:3; /* FLEXRAY */
1823
1824	uint32_t:4;
1825
1826	uint32_t:4;
1827
1828	uint32_t:1;
1829	uint32_t MSTR3:3; /* FEC */
1830
1831	uint32_t:1;
1832	uint32_t MSTR2:3;
1833	uint32_t:1;
1834	uint32_t MSTR1:3;
1835	uint32_t:1;
1836	uint32_t MSTR0:3;
1837	} B;
1838	} MPR7; /* Master Priority Register for Slave Port 7 */
1839
1840	uint32_t xbar_reserved9[3];
1841
1842	union {
1843	uint32_t R;
1844	struct {
1845	uint32_t RO:1;
1846	uint32_t:21;
1847	uint32_t ARB:2;
1848	uint32_t:2;
1849	uint32_t PCTL:2;
1850	uint32_t:1;
1851	uint32_t PARK:3;
1852	} B;
1853	} SGPCR7; /* General Purpose Control Register for Slave Port 7 */
1854
1855	};
1856	/****************************************************************************/
1857	/* MODULE : ECSM */
1858	/****************************************************************************/
1859	struct ECSM_tag {
1860
1861	uint32_t ecsm_reserved1[5];
1862
1863	uint16_t ecsm_reserved2;
1864
1865	union {
1866	uint16_t R;
1867	} SWTCR; //Software Watchdog Timer Control
1868
1869	uint8_t ecsm_reserved3[3];
1870
1871	union {
1872	uint8_t R;
1873	} SWTSR; //SWT Service Register
1874
1875	uint8_t ecsm_reserved4[3];
1876
1877	union {
1878	uint8_t R;
1879	} SWTIR; //SWT Interrupt Register
1880
1881	uint32_t ecsm_reserved5a[1];
1882
1883	union {
1884	uint32_t R;
1885	struct {
1886	uint32_t FSBCR0:1;
1887	uint32_t FSBCR1:1;
1888	uint32_t FSBCR2:1;
1889	uint32_t FSBCR3:1;
1890	uint32_t FSBCR4:1;
1891	uint32_t FSBCR5:1;
1892	uint32_t FSBCR6:1;
1893	uint32_t FSBCR7:1;
1894	uint32_t RBEN:1;
1895	uint32_t WBEN:1;
1896	uint32_t ACCERR:1;
1897	uint32_t:21;
1898	} B;
1899	} FSBMCR; /* FEC System Bus Master Control Register */
1900
1901	uint32_t ecsm_reserved5c[6];
1902
1903	uint8_t ecsm_reserved6[3];
1904
1905	union {
1906	uint8_t R;
1907	struct {
1908	uint8_t:6;
1909	uint8_t ERNCR:1;
1910	uint8_t EFNCR:1;
1911	} B;
1912	} ECR; //ECC Configuration Register
1913
1914	uint8_t mcm_reserved8[3];
1915
1916	union {
1917	uint8_t R;
1918	struct {
1919	uint8_t:6;
1920	uint8_t RNCE:1;
1921	uint8_t FNCE:1;
1922	} B;
1923	} ESR; //ECC Status Register
1924
1925	uint16_t ecsm_reserved9;
1926
1927	union {
1928	uint16_t R;
1929	struct {
1930	uint16_t:6;
1931	uint16_t FRCNCI:1;
1932	uint16_t FR1NCI:1;
1933	uint16_t:1;
1934	uint16_t ERRBIT:7;
1935	} B;
1936	} EEGR; //ECC Error Generation Register
1937
1938	uint32_t ecsm_reserved10;
1939
1940	union {
1941	uint32_t R;
1942	struct {
1943	uint32_t FEAR:32;
1944	} B;
1945	} FEAR; //Flash ECC Address Register
1946
1947	uint16_t ecsm_reserved11;
1948
1949	union {
1950	uint8_t R;
1951	struct {
1952	uint8_t:4;
1953	uint8_t FEMR:4;
1954	} B;
1955	} FEMR; //Flash ECC Master Register
1956
1957	union {
1958	uint8_t R;
1959	struct {
1960	uint8_t WRITE:1;
1961	uint8_t SIZE:3;
1962	uint8_t PROT0:1;
1963	uint8_t PROT1:1;
1964	uint8_t PROT2:1;
1965	uint8_t PROT3:1;
1966	} B;
1967	} FEAT; //Flash ECC Attributes Register
1968
1969	union {
1970	uint32_t R;
1971	struct {
1972	uint32_t FEDH:32;
1973	} B;
1974	} FEDRH; //Flash ECC Data High Register
1975
1976	union {
1977	uint32_t R;
1978	struct {
1979	uint32_t FEDL:32;
1980	} B;
1981	} FEDRL; //Flash ECC Data Low Register
1982
1983	union {
1984	uint32_t R;
1985	struct {
1986	uint32_t REAR:32;
1987	} B;
1988	} REAR; //RAM ECC Address
1989
1990	uint8_t ecsm_reserved12[2];
1991
1992	union {
1993	uint8_t R;
1994	struct {
1995	uint8_t:4;
1996	uint8_t REMR:4;
1997	} B;
1998	} REMR; //RAM ECC Master
1999
2000	union {
2001	uint8_t R;
2002	struct {
2003	uint8_t WRITE:1;
2004	uint8_t SIZE:3;
2005	uint8_t PROT0:1;
2006	uint8_t PROT1:1;
2007	uint8_t PROT2:1;
2008	uint8_t PROT3:1;
2009	} B;
2010	} REAT; // RAM ECC Attributes Register
2011
2012	union {
2013	uint32_t R;
2014	struct {
2015	uint32_t REDH:32;
2016	} B;
2017	} REDRH; //RAM ECC Data High Register
2018
2019	union {
2020	uint32_t R;
2021	struct {
2022	uint32_t REDL:32;
2023	} B;
2024	} REDRL; //RAMECC Data Low Register
2025
2026	};
2027	/****************************************************************************/
2028	/* MODULE : INTC */
2029	/****************************************************************************/
2030	struct INTC_tag {
2031	union {
2032	uint32_t R;
2033	struct {
2034	uint32_t:26;
2035	uint32_t VTES:1;
2036	uint32_t:4;
2037	uint32_t HVEN:1;
2038	} B;
2039	} MCR; /* Module Configuration Register */
2040
2041	int32_t INTC_reserved00;
2042
2043	union {
2044	uint32_t R;
2045	struct {
2046	uint32_t:28;
2047	uint32_t PRI:4;
2048	} B;
2049	} CPR; /* Current Priority Register */
2050
2051	uint32_t intc_reserved1;
2052
2053	union {
2054	uint32_t R;
2055	struct {
2056	uint32_t VTBA:21;
2057	uint32_t INTVEC:9;
2058	uint32_t:2;
2059	} B;
2060	} IACKR; /* Interrupt Acknowledge Register */
2061
2062	uint32_t intc_reserved2;
2063
2064	union {
2065	uint32_t R;
2066	struct {
2067	uint32_t:32;
2068	} B;
2069	} EOIR; /* End of Interrupt Register */
2070
2071	uint32_t intc_reserved3;
2072
2073	union {
2074	uint8_t R;
2075	struct {
2076	uint8_t:6;
2077	uint8_t SET:1;
2078	uint8_t CLR:1;
2079	} B;
2080	} SSCIR[8]; /* Software Set/Clear Interruput Register */
2081
2082	uint32_t intc_reserved4[6];
2083
2084	union {
2085	uint8_t R;
2086	struct {
2087	uint8_t:4;
2088	uint8_t PRI:4;
2089	} B;
2090	} PSR[358]; /* Software Set/Clear Interrupt Register */
2091
2092	};
2093	/****************************************************************************/
2094	/* MODULE : EQADC */
2095	/****************************************************************************/
2096	struct EQADC_tag {
2097	union {
2098	uint32_t R;
2099	struct {
2100	uint32_t:27;
2101	uint32_t ESSIE:2;
2102	uint32_t:1;
2103	uint32_t DBG:2;
2104	} B;
2105	} MCR; /* Module Configuration Register */
2106
2107	int32_t EQADC_reserved00;
2108
2109	union {
2110	uint32_t R;
2111	struct {
2112	uint32_t:6;
2113	uint32_t NMF:26;
2114	} B;
2115	} NMSFR; /* Null Message Send Format Register */
2116
2117	union {
2118	uint32_t R;
2119	struct {
2120	uint32_t:28;
2121	uint32_t DFL:4;
2122	} B;
2123	} ETDFR; /* External Trigger Digital Filter Register */
2124
2125	union {
2126	uint32_t R;
2127	struct {
2128	uint32_t CFPUSH:32;
2129	} B;
2130	} CFPR[6]; /* CFIFO Push Registers */
2131
2132	uint32_t eqadc_reserved1;
2133
2134	uint32_t eqadc_reserved2;
2135
2136	union {
2137	uint32_t R;
2138	struct {
2139	uint32_t:16;
2140	uint32_t RFPOP:16;
2141	} B;
2142	} RFPR[6]; /* Result FIFO Pop Registers */
2143
2144	uint32_t eqadc_reserved3;
2145
2146	uint32_t eqadc_reserved4;
2147
2148	union {
2149	uint16_t R;
2150	struct {
2151	uint16_t:5;
2152	uint16_t SSE:1;
2153	uint16_t CFINV:1;
2154	uint16_t:1;
2155	uint16_t MODE:4;
2156	uint16_t:4;
2157	} B;
2158	} CFCR[6]; /* CFIFO Control Registers */
2159
2160	uint32_t eqadc_reserved5;
2161
2162	union {
2163	uint16_t R;
2164	struct {
2165	uint16_t NCIE:1;
2166	uint16_t TORIE:1;
2167	uint16_t PIE:1;
2168	uint16_t EOQIE:1;
2169	uint16_t CFUIE:1;
2170	uint16_t:1;
2171	uint16_t CFFE:1;
2172	uint16_t CFFS:1;
2173	uint16_t:4;
2174	uint16_t RFOIE:1;
2175	uint16_t:1;
2176	uint16_t RFDE:1;
2177	uint16_t RFDS:1;
2178	} B;
2179	} IDCR[6]; /* Interrupt and DMA Control Registers */
2180
2181	uint32_t eqadc_reserved6;
2182
2183	union {
2184	uint32_t R;
2185	struct {
2186	uint32_t NCF:1;
2187	uint32_t TORF:1;
2188	uint32_t PF:1;
2189	uint32_t EOQF:1;
2190	uint32_t CFUF:1;
2191	uint32_t SSS:1;
2192	uint32_t CFFF:1;
2193	uint32_t:5;
2194	uint32_t RFOF:1;
2195	uint32_t:1;
2196	uint32_t RFDF:1;
2197	uint32_t:1;
2198	uint32_t CFCTR:4;
2199	uint32_t TNXTPTR:4;
2200	uint32_t RFCTR:4;
2201	uint32_t POPNXTPTR:4;
2202	} B;
2203	} FISR[6]; /* FIFO and Interrupt Status Registers */
2204
2205	uint32_t eqadc_reserved7;
2206
2207	uint32_t eqadc_reserved8;
2208
2209	union {
2210	uint16_t R;
2211	struct {
2212	uint16_t:5;
2213	uint16_t TCCF:11;
2214	} B;
2215	} CFTCR[6]; /* CFIFO Transfer Counter Registers */
2216
2217	uint32_t eqadc_reserved9;
2218
2219	union {
2220	uint32_t R;
2221	struct {
2222	uint32_t CFS0:2;
2223	uint32_t CFS1:2;
2224	uint32_t CFS2:2;
2225	uint32_t CFS3:2;
2226	uint32_t CFS4:2;
2227	uint32_t CFS5:2;
2228	uint32_t:5;
2229	uint32_t LCFTCB0:4;
2230	uint32_t TC_LCFTCB0:11;
2231	} B;
2232	} CFSSR0; /* CFIFO Status Register 0 */
2233
2234	union {
2235	uint32_t R;
2236	struct {
2237	uint32_t CFS0:2;
2238	uint32_t CFS1:2;
2239	uint32_t CFS2:2;
2240	uint32_t CFS3:2;
2241	uint32_t CFS4:2;
2242	uint32_t CFS5:2;
2243	uint32_t:5;
2244	uint32_t LCFTCB1:4;
2245	uint32_t TC_LCFTCB1:11;
2246	} B;
2247	} CFSSR1; /* CFIFO Status Register 1 */
2248
2249	union {
2250	uint32_t R;
2251	struct {
2252	uint32_t CFS0:2;
2253	uint32_t CFS1:2;
2254	uint32_t CFS2:2;
2255	uint32_t CFS3:2;
2256	uint32_t CFS4:2;
2257	uint32_t CFS5:2;
2258	uint32_t:4;
2259	uint32_t ECBNI:1;
2260	uint32_t LCFTSSI:4;
2261	uint32_t TC_LCFTSSI:11;
2262	} B;
2263	} CFSSR2; /* CFIFO Status Register 2 */
2264
2265	union {
2266	uint32_t R;
2267	struct {
2268	uint32_t CFS0:2;
2269	uint32_t CFS1:2;
2270	uint32_t CFS2:2;
2271	uint32_t CFS3:2;
2272	uint32_t CFS4:2;
2273	uint32_t CFS5:2;
2274	uint32_t:20;
2275	} B;
2276	} CFSR;
2277
2278	uint32_t eqadc_reserved11;
2279
2280	union {
2281	uint32_t R;
2282	struct {
2283	uint32_t:21;
2284	uint32_t MDT:3;
2285	uint32_t:4;
2286	uint32_t BR:4;
2287	} B;
2288	} SSICR; /* SSI Control Register */
2289
2290	union {
2291	uint32_t R;
2292	struct {
2293	uint32_t RDV:1;
2294	uint32_t:5;
2295	uint32_t RDATA:26;
2296	} B;
2297	} SSIRDR; /* SSI Recieve Data Register */
2298
2299	uint32_t eqadc_reserved12[17];
2300
2301	struct {
2302	union {
2303	uint32_t R;
2304	struct {
2305	uint32_t:32;
2306	} B;
2307	} R[4];
2308
2309	uint32_t eqadc_reserved13[12];
2310
2311	} CF[6];
2312
2313	uint32_t eqadc_reserved14[32];
2314
2315	struct {
2316	union {
2317	uint32_t R;
2318	struct {
2319	uint32_t:32;
2320	} B;
2321	} R[4];
2322
2323	uint32_t eqadc_reserved15[12];
2324
2325	} RF[6];
2326
2327	};
2328	/****************************************************************************/
2329	/* MODULE : DSPI */
2330	/****************************************************************************/
2331	struct DSPI_tag {
2332	union DSPI_MCR_tag {
2333	uint32_t R;
2334	struct {
2335	uint32_t MSTR:1;
2336	uint32_t CONT_SCKE:1;
2337	uint32_t DCONF:2;
2338	uint32_t FRZ:1;
2339	uint32_t MTFE:1;
2340	uint32_t PCSSE:1;
2341	uint32_t ROOE:1;
2342	uint32_t:2;
2343	uint32_t PCSIS5:1;
2344	uint32_t PCSIS4:1;
2345	uint32_t PCSIS3:1;
2346	uint32_t PCSIS2:1;
2347	uint32_t PCSIS1:1;
2348	uint32_t PCSIS0:1;
2349	uint32_t DOZE:1;
2350	uint32_t MDIS:1;
2351	uint32_t DIS_TXF:1;
2352	uint32_t DIS_RXF:1;
2353	uint32_t CLR_TXF:1;
2354	uint32_t CLR_RXF:1;
2355	uint32_t SMPL_PT:2;
2356	uint32_t:7;
2357	uint32_t HALT:1;
2358	} B;
2359	} MCR; /* Module Configuration Register */
2360
2361	uint32_t dspi_reserved1;
2362
2363	union {
2364	uint32_t R;
2365	struct {
2366	uint32_t TCNT:16;
2367	uint32_t:16;
2368	} B;
2369	} TCR;
2370
2371	union DSPI_CTAR_tag {
2372	uint32_t R;
2373	struct {
2374	uint32_t DBR:1;
2375	uint32_t FMSZ:4;
2376	uint32_t CPOL:1;
2377	uint32_t CPHA:1;
2378	uint32_t LSBFE:1;
2379	uint32_t PCSSCK:2;
2380	uint32_t PASC:2;
2381	uint32_t PDT:2;
2382	uint32_t PBR:2;
2383	uint32_t CSSCK:4;
2384	uint32_t ASC:4;
2385	uint32_t DT:4;
2386	uint32_t BR:4;
2387	} B;
2388	} CTAR[8]; /* Clock and Transfer Attributes Registers */
2389
2390	union DSPI_SR_tag {
2391	uint32_t R;
2392	struct {
2393	uint32_t TCF:1;
2394	uint32_t TXRXS:1;
2395	uint32_t:1;
2396	uint32_t EOQF:1;
2397	uint32_t TFUF:1;
2398	uint32_t:1;
2399	uint32_t TFFF:1;
2400	uint32_t:5;
2401	uint32_t RFOF:1;
2402	uint32_t:1;
2403	uint32_t RFDF:1;
2404	uint32_t:1;
2405	uint32_t TXCTR:4;
2406	uint32_t TXNXTPTR:4;
2407	uint32_t RXCTR:4;
2408	uint32_t POPNXTPTR:4;
2409	} B;
2410	} SR; /* Status Register */
2411
2412	union DSPI_RSER_tag {
2413	uint32_t R;
2414	struct {
2415	uint32_t TCFRE:1;
2416	uint32_t:2;
2417	uint32_t EOQFRE:1;
2418	uint32_t TFUFRE:1;
2419	uint32_t:1;
2420	uint32_t TFFFRE:1;
2421	uint32_t TFFFDIRS:1;
2422	uint32_t:4;
2423	uint32_t RFOFRE:1;
2424	uint32_t:1;
2425	uint32_t RFDFRE:1;
2426	uint32_t RFDFDIRS:1;
2427	uint32_t:16;
2428	} B;
2429	} RSER; /* DMA/Interrupt Request Select and Enable Register */
2430
2431	union DSPI_PUSHR_tag {
2432	uint32_t R;
2433	struct {
2434	uint32_t CONT:1;
2435	uint32_t CTAS:3;
2436	uint32_t EOQ:1;
2437	uint32_t CTCNT:1;
2438	uint32_t:4;
2439	uint32_t PCS5:1;
2440	uint32_t PCS4:1;
2441	uint32_t PCS3:1;
2442	uint32_t PCS2:1;
2443	uint32_t PCS1:1;
2444	uint32_t PCS0:1;
2445	uint32_t TXDATA:16;
2446	} B;
2447	} PUSHR; /* PUSH TX FIFO Register */
2448
2449	union DSPI_POPR_tag {
2450	uint32_t R;
2451	struct {
2452	uint32_t:16;
2453	uint32_t RXDATA:16;
2454	} B;
2455	} POPR; /* POP RX FIFO Register */
2456
2457	union {
2458	uint32_t R;
2459	struct {
2460	uint32_t TXCMD:16;
2461	uint32_t TXDATA:16;
2462	} B;
2463	} TXFR[4]; /* Transmit FIFO Registers */
2464
2465	uint32_t DSPI_reserved_txf[12];
2466
2467	union {
2468	uint32_t R;
2469	struct {
2470	uint32_t:16;
2471	uint32_t RXDATA:16;
2472	} B;
2473	} RXFR[4]; /* Transmit FIFO Registers */
2474
2475	uint32_t DSPI_reserved_rxf[12];
2476
2477	union {
2478	uint32_t R;
2479	struct {
2480	uint32_t MTOE:1;
2481	uint32_t:1;
2482	uint32_t MTOCNT:6;
2483	uint32_t:4;
2484	uint32_t TXSS:1;
2485	uint32_t TPOL:1;
2486	uint32_t TRRE:1;
2487	uint32_t CID:1;
2488	uint32_t DCONT:1;
2489	uint32_t DSICTAS:3;
2490	uint32_t:6;
2491	uint32_t DPCS5:1;
2492	uint32_t DPCS4:1;
2493	uint32_t DPCS3:1;
2494	uint32_t DPCS2:1;
2495	uint32_t DPCS1:1;
2496	uint32_t DPCS0:1;
2497	} B;
2498	} DSICR; /* DSI Configuration Register */
2499
2500	union {
2501	uint32_t R;
2502	struct {
2503	uint32_t:16;
2504	uint32_t SER_DATA:16;
2505	} B;
2506	} SDR; /* DSI Serialization Data Register */
2507
2508	union {
2509	uint32_t R;
2510	struct {
2511	uint32_t:16;
2512	uint32_t ASER_DATA:16;
2513	} B;
2514	} ASDR; /* DSI Alternate Serialization Data Register */
2515
2516	union {
2517	uint32_t R;
2518	struct {
2519	uint32_t:16;
2520	uint32_t COMP_DATA:16;
2521	} B;
2522	} COMPR; /* DSI Transmit Comparison Register */
2523
2524	union {
2525	uint32_t R;
2526	struct {
2527	uint32_t:16;
2528	uint32_t DESER_DATA:16;
2529	} B;
2530	} DDR; /* DSI deserialization Data Register */
2531
2532	};
2533	/****************************************************************************/
2534	/* MODULE : eSCI */
2535	/****************************************************************************/
2536	struct ESCI_tag {
2537	union ESCI_CR1_tag {
2538	uint32_t R;
2539	struct {
2540	uint32_t:3;
2541	uint32_t SBR:13;
2542	uint32_t LOOPS:1;
2543	uint32_t SCISDOZ:1;
2544	uint32_t RSRC:1;
2545	uint32_t M:1;
2546	uint32_t WAKE:1;
2547	uint32_t ILT:1;
2548	uint32_t PE:1;
2549	uint32_t PT:1;
2550	uint32_t TIE:1;
2551	uint32_t TCIE:1;
2552	uint32_t RIE:1;
2553	uint32_t ILIE:1;
2554	uint32_t TE:1;
2555	uint32_t RE:1;
2556	uint32_t RWU:1;
2557	uint32_t SBK:1;
2558	} B;
2559	} CR1; /* Control Register 1 */
2560
2561	union ESCI_CR2_tag {
2562	uint16_t R;
2563	struct {
2564	uint16_t MDIS:1;
2565	uint16_t FBR:1;
2566	uint16_t BSTP:1;
2567	uint16_t IEBERR:1;
2568	uint16_t RXDMA:1;
2569	uint16_t TXDMA:1;
2570	uint16_t BRK13:1;
2571	uint16_t:1;
2572	uint16_t BESM13:1;
2573	uint16_t SBSTP:1;
2574	uint16_t:2;
2575	uint16_t ORIE:1;
2576	uint16_t NFIE:1;
2577	uint16_t FEIE:1;
2578	uint16_t PFIE:1;
2579	} B;
2580	} CR2; /* Control Register 2 */
2581
2582	union ESCI_DR_tag {
2583	uint16_t R;
2584	struct {
2585	uint16_t R8:1;
2586	uint16_t T8:1;
2587	uint16_t:6;
2588	uint8_t D;
2589	} B;
2590	} DR; /* Data Register */
2591
2592	union ESCI_SR_tag {
2593	uint32_t R;
2594	struct {
2595	uint32_t TDRE:1;
2596	uint32_t TC:1;
2597	uint32_t RDRF:1;
2598	uint32_t IDLE:1;
2599	uint32_t OR:1;
2600	uint32_t NF:1;
2601	uint32_t FE:1;
2602	uint32_t PF:1;
2603	uint32_t:3;
2604	uint32_t BERR:1;
2605	uint32_t:3;
2606	uint32_t RAF:1;
2607	uint32_t RXRDY:1;
2608	uint32_t TXRDY:1;
2609	uint32_t LWAKE:1;
2610	uint32_t STO:1;
2611	uint32_t PBERR:1;
2612	uint32_t CERR:1;
2613	uint32_t CKERR:1;
2614	uint32_t FRC:1;
2615	uint32_t:7;
2616	uint32_t OVFL:1;
2617	} B;
2618	} SR; /* Status Register */
2619
2620	union {
2621	uint32_t R;
2622	struct {
2623	uint32_t LRES:1;
2624	uint32_t WU:1;
2625	uint32_t WUD0:1;
2626	uint32_t WUD1:1;
2627	uint32_t LDBG:1;
2628	uint32_t DSF:1;
2629	uint32_t PRTY:1;
2630	uint32_t LIN:1;
2631	uint32_t RXIE:1;
2632	uint32_t TXIE:1;
2633	uint32_t WUIE:1;
2634	uint32_t STIE:1;
2635	uint32_t PBIE:1;
2636	uint32_t CIE:1;
2637	uint32_t CKIE:1;
2638	uint32_t FCIE:1;
2639	uint32_t:7;
2640	uint32_t OFIE:1;
2641	uint32_t:8;
2642	} B;
2643	} LCR; /* LIN Control Register */
2644
2645	union {
2646	uint32_t R;
2647	} LTR; /* LIN Transmit Register */
2648
2649	union {
2650	uint32_t R;
2651	} LRR; /* LIN Recieve Register */
2652
2653	union {
2654	uint32_t R;
2655	} LPR; /* LIN CRC Polynom Register */
2656
2657	};
2658	/****************************************************************************/
2659	/* MODULE : FlexCAN */
2660	/****************************************************************************/
2661	struct FLEXCAN2_tag {
2662	union {
2663	uint32_t R;
2664	struct {
2665	uint32_t MDIS:1;
2666	uint32_t FRZ:1;
2667	uint32_t:1;
2668	uint32_t HALT:1;
2669	uint32_t NOTRDY:1;
2670	uint32_t:1;
2671	uint32_t SOFTRST:1;
2672	uint32_t FRZACK:1;
2673	uint32_t:1;
2674	uint32_t:1;
2675
2676	uint32_t WRNEN:1;
2677
2678	uint32_t MDISACK:1;
2679	uint32_t:1;
2680	uint32_t:1;
2681
2682	uint32_t SRXDIS:1;
2683	uint32_t MBFEN:1;
2684	uint32_t:10;
2685
2686	uint32_t MAXMB:6;
2687	} B;
2688	} MCR; /* Module Configuration Register */
2689
2690	union {
2691	uint32_t R;
2692	struct {
2693	uint32_t PRESDIV:8;
2694	uint32_t RJW:2;
2695	uint32_t PSEG1:3;
2696	uint32_t PSEG2:3;
2697	uint32_t BOFFMSK:1;
2698	uint32_t ERRMSK:1;
2699	uint32_t CLKSRC:1;
2700	uint32_t LPB:1;
2701
2702	uint32_t TWRNMSK:1;
2703	uint32_t RWRNMSK:1;
2704	uint32_t:2;
2705
2706	uint32_t SMP:1;
2707	uint32_t BOFFREC:1;
2708	uint32_t TSYN:1;
2709	uint32_t LBUF:1;
2710	uint32_t LOM:1;
2711	uint32_t PROPSEG:3;
2712	} B;
2713	} CR; /* Control Register */
2714
2715	union {
2716	uint32_t R;
2717	} TIMER; /* Free Running Timer */
2718	int32_t FLEXCAN_reserved00;
2719
2720	union {
2721	uint32_t R;
2722	struct {
2723	uint32_t:3;
2724	uint32_t MI:29;
2725	} B;
2726	} RXGMASK; /* RX Global Mask */
2727
2728	union {
2729	uint32_t R;
2730	struct {
2731	uint32_t:3;
2732	uint32_t MI:29;
2733	} B;
2734	} RX14MASK; /* RX 14 Mask */
2735
2736	union {
2737	uint32_t R;
2738	struct {
2739	uint32_t:3;
2740	uint32_t MI:29;
2741	} B;
2742	} RX15MASK; /* RX 15 Mask */
2743
2744	union {
2745	uint32_t R;
2746	struct {
2747	uint32_t:16;
2748	uint32_t RXECNT:8;
2749	uint32_t TXECNT:8;
2750	} B;
2751	} ECR; /* Error Counter Register */
2752
2753	union {
2754	uint32_t R;
2755	struct {
2756	uint32_t:14;
2757
2758	uint32_t TWRNINT:1;
2759	uint32_t RWRNINT:1;
2760
2761	uint32_t BIT1ERR:1;
2762	uint32_t BIT0ERR:1;
2763	uint32_t ACKERR:1;
2764	uint32_t CRCERR:1;
2765	uint32_t FRMERR:1;
2766	uint32_t STFERR:1;
2767	uint32_t TXWRN:1;
2768	uint32_t RXWRN:1;
2769	uint32_t IDLE:1;
2770	uint32_t TXRX:1;
2771	uint32_t FLTCONF:2;
2772	uint32_t:1;
2773	uint32_t BOFFINT:1;
2774	uint32_t ERRINT:1;
2775	uint32_t:1;
2776	} B;
2777	} ESR; /* Error and Status Register */
2778
2779	union {
2780	uint32_t R;
2781	struct {
2782	uint32_t BUF63M:1;
2783	uint32_t BUF62M:1;
2784	uint32_t BUF61M:1;
2785	uint32_t BUF60M:1;
2786	uint32_t BUF59M:1;
2787	uint32_t BUF58M:1;
2788	uint32_t BUF57M:1;
2789	uint32_t BUF56M:1;
2790	uint32_t BUF55M:1;
2791	uint32_t BUF54M:1;
2792	uint32_t BUF53M:1;
2793	uint32_t BUF52M:1;
2794	uint32_t BUF51M:1;
2795	uint32_t BUF50M:1;
2796	uint32_t BUF49M:1;
2797	uint32_t BUF48M:1;
2798	uint32_t BUF47M:1;
2799	uint32_t BUF46M:1;
2800	uint32_t BUF45M:1;
2801	uint32_t BUF44M:1;
2802	uint32_t BUF43M:1;
2803	uint32_t BUF42M:1;
2804	uint32_t BUF41M:1;
2805	uint32_t BUF40M:1;
2806	uint32_t BUF39M:1;
2807	uint32_t BUF38M:1;
2808	uint32_t BUF37M:1;
2809	uint32_t BUF36M:1;
2810	uint32_t BUF35M:1;
2811	uint32_t BUF34M:1;
2812	uint32_t BUF33M:1;
2813	uint32_t BUF32M:1;
2814	} B;
2815	} IMRH; /* Interruput Masks Register */
2816
2817	union {
2818	uint32_t R;
2819	struct {
2820	uint32_t BUF31M:1;
2821	uint32_t BUF30M:1;
2822	uint32_t BUF29M:1;
2823	uint32_t BUF28M:1;
2824	uint32_t BUF27M:1;
2825	uint32_t BUF26M:1;
2826	uint32_t BUF25M:1;
2827	uint32_t BUF24M:1;
2828	uint32_t BUF23M:1;
2829	uint32_t BUF22M:1;
2830	uint32_t BUF21M:1;
2831	uint32_t BUF20M:1;
2832	uint32_t BUF19M:1;
2833	uint32_t BUF18M:1;
2834	uint32_t BUF17M:1;
2835	uint32_t BUF16M:1;
2836	uint32_t BUF15M:1;
2837	uint32_t BUF14M:1;
2838	uint32_t BUF13M:1;
2839	uint32_t BUF12M:1;
2840	uint32_t BUF11M:1;
2841	uint32_t BUF10M:1;
2842	uint32_t BUF09M:1;
2843	uint32_t BUF08M:1;
2844	uint32_t BUF07M:1;
2845	uint32_t BUF06M:1;
2846	uint32_t BUF05M:1;
2847	uint32_t BUF04M:1;
2848	uint32_t BUF03M:1;
2849	uint32_t BUF02M:1;
2850	uint32_t BUF01M:1;
2851	uint32_t BUF00M:1;
2852	} B;
2853	} IMRL; /* Interruput Masks Register */
2854
2855	union {
2856	uint32_t R;
2857	struct {
2858	uint32_t BUF63I:1;
2859	uint32_t BUF62I:1;
2860	uint32_t BUF61I:1;
2861	uint32_t BUF60I:1;
2862	uint32_t BUF59I:1;
2863	uint32_t BUF58I:1;
2864	uint32_t BUF57I:1;
2865	uint32_t BUF56I:1;
2866	uint32_t BUF55I:1;
2867	uint32_t BUF54I:1;
2868	uint32_t BUF53I:1;
2869	uint32_t BUF52I:1;
2870	uint32_t BUF51I:1;
2871	uint32_t BUF50I:1;
2872	uint32_t BUF49I:1;
2873	uint32_t BUF48I:1;
2874	uint32_t BUF47I:1;
2875	uint32_t BUF46I:1;
2876	uint32_t BUF45I:1;
2877	uint32_t BUF44I:1;
2878	uint32_t BUF43I:1;
2879	uint32_t BUF42I:1;
2880	uint32_t BUF41I:1;
2881	uint32_t BUF40I:1;
2882	uint32_t BUF39I:1;
2883	uint32_t BUF38I:1;
2884	uint32_t BUF37I:1;
2885	uint32_t BUF36I:1;
2886	uint32_t BUF35I:1;
2887	uint32_t BUF34I:1;
2888	uint32_t BUF33I:1;
2889	uint32_t BUF32I:1;
2890	} B;
2891	} IFRH; /* Interruput Flag Register */
2892
2893	union {
2894	uint32_t R;
2895	struct {
2896	uint32_t BUF31I:1;
2897	uint32_t BUF30I:1;
2898	uint32_t BUF29I:1;
2899	uint32_t BUF28I:1;
2900	uint32_t BUF27I:1;
2901	uint32_t BUF26I:1;
2902	uint32_t BUF25I:1;
2903	uint32_t BUF24I:1;
2904	uint32_t BUF23I:1;
2905	uint32_t BUF22I:1;
2906	uint32_t BUF21I:1;
2907	uint32_t BUF20I:1;
2908	uint32_t BUF19I:1;
2909	uint32_t BUF18I:1;
2910	uint32_t BUF17I:1;
2911	uint32_t BUF16I:1;
2912	uint32_t BUF15I:1;
2913	uint32_t BUF14I:1;
2914	uint32_t BUF13I:1;
2915	uint32_t BUF12I:1;
2916	uint32_t BUF11I:1;
2917	uint32_t BUF10I:1;
2918	uint32_t BUF09I:1;
2919	uint32_t BUF08I:1;
2920	uint32_t BUF07I:1;
2921	uint32_t BUF06I:1;
2922	uint32_t BUF05I:1;
2923	uint32_t BUF04I:1;
2924	uint32_t BUF03I:1;
2925	uint32_t BUF02I:1;
2926	uint32_t BUF01I:1;
2927	uint32_t BUF00I:1;
2928	} B;
2929	} IFRL; /* Interruput Flag Register */
2930
2931	uint32_t flexcan2_reserved2[19];
2932
2933	struct canbuf_t {
2934	union {
2935	uint32_t R;
2936	struct {
2937	uint32_t:4;
2938	uint32_t CODE:4;
2939	uint32_t:1;
2940	uint32_t SRR:1;
2941	uint32_t IDE:1;
2942	uint32_t RTR:1;
2943	uint32_t LENGTH:4;
2944	uint32_t TIMESTAMP:16;
2945	} B;
2946	} CS;
2947
2948	union {
2949	uint32_t R;
2950	struct {
2951	uint32_t:3;
2952	uint32_t STD_ID:11;
2953	uint32_t EXT_ID:18;
2954	} B;
2955	} ID;
2956
2957	union {
2958	uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
2959	uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
2960	uint32_t W[2]; /* Data buffer in words (32 bits) */
2961	uint32_t R[2]; /* Data buffer in words (32 bits) */
2962	} DATA;
2963
2964	} BUF[64];
2965
2966	uint32_t flexcan2_reserved3[256];
2967
2968	union {
2969	uint32_t R;
2970	struct {
2971	uint32_t:3;
2972	uint32_t MI:29;
2973	} B;
2974	} RXIMR[64]; /* RX Individual Mask Registers */
2975
2976	};
2977	/****************************************************************************/
2978	/* MODULE : FEC */
2979	/****************************************************************************/
2980	struct FEC_tag {
2981
2982	uint32_t fec_reserved_start[0x1];
2983
2984	union {
2985	uint32_t R;
2986	struct {
2987	uint32_t HBERR:1;
2988	uint32_t BABR:1;
2989	uint32_t BABT:1;
2990	uint32_t GRA:1;
2991	uint32_t TXF:1;
2992	uint32_t TXB:1;
2993	uint32_t RXF:1;
2994	uint32_t RXB:1;
2995	uint32_t MII:1;
2996	uint32_t EBERR:1;
2997	uint32_t LC:1;
2998	uint32_t RL:1;
2999	uint32_t UN:1;
3000	uint32_t:19;
3001	} B;
3002	} EIR; /* Interrupt Event Register */
3003
3004	union {
3005	uint32_t R;
3006	struct {
3007	uint32_t HBERRM:1;
3008	uint32_t BABRM:1;
3009	uint32_t BABTM:1;
3010	uint32_t GRAM:1;
3011	uint32_t TXFM:1;
3012	uint32_t TXBM:1;
3013	uint32_t RXFM:1;
3014	uint32_t RXBM:1;
3015	uint32_t MIIM:1;
3016	uint32_t EBERRM:1;
3017	uint32_t LCM:1;
3018	uint32_t RLM:1;
3019	uint32_t UNM:1;
3020	uint32_t:19;
3021	} B;
3022	} EIMR; /* Interrupt Mask Register */
3023
3024	uint32_t fec_reserved_eimr;
3025
3026	union {
3027	uint32_t R;
3028	struct {
3029	uint32_t:7;
3030	uint32_t R_DES_ACTIVE:1;
3031	uint32_t:24;
3032	} B;
3033	} RDAR; /* Receive Descriptor Active Register */
3034
3035	union {
3036	uint32_t R;
3037	struct {
3038	uint32_t:7;
3039	uint32_t X_DES_ACTIVE:1;
3040	uint32_t:24;
3041	} B;
3042	} TDAR; /* Transmit Descriptor Active Register */
3043
3044	uint32_t fec_reserved_tdar[3];
3045
3046	union {
3047	uint32_t R;
3048	struct {
3049	uint32_t:30;
3050	uint32_t ETHER_EN:1;
3051	uint32_t RESET:1;
3052	} B;
3053	} ECR; /* Ethernet Control Register */
3054
3055	uint32_t fec_reserved_ecr[6];
3056
3057	union {
3058	uint32_t R;
3059	struct {
3060	uint32_t ST:2;
3061	uint32_t CP:2;
3062	uint32_t PA:5;
3063	uint32_t RA:5;
3064	uint32_t TA:2;
3065	uint32_t DATA:16;
3066	} B;
3067	} MDATA; /* MII Data Register */
3068
3069	union {
3070	uint32_t R;
3071	struct {
3072	uint32_t:24;
3073	uint32_t DIS_PREAMBLE:1;
3074	uint32_t MII_SPEED:6;
3075	uint32_t:1;
3076	} B;
3077	} MSCR; /* MII Speed Control Register */
3078
3079	uint32_t fec_reserved_mscr[7];
3080
3081	union {
3082	uint32_t R;
3083	struct {
3084	uint32_t MIB_DISABLE:1;
3085	uint32_t MIB_IDLE:1;
3086	uint32_t:30;
3087	} B;
3088	} MIBC; /* MIB Control Register */
3089
3090	uint32_t fec_reserved_mibc[7];
3091
3092	union {
3093	uint32_t R;
3094	struct {
3095	uint32_t:5;
3096	uint32_t MAX_FL:11;
3097	uint32_t:10;
3098	uint32_t FCE:1;
3099	uint32_t BC_REJ:1;
3100	uint32_t PROM:1;
3101	uint32_t MII_MODE:1;
3102	uint32_t DRT:1;
3103	uint32_t LOOP:1;
3104	} B;
3105	} RCR; /* Receive Control Register */
3106
3107	uint32_t fec_reserved_rcr[15];
3108
3109	union {
3110	uint32_t R;
3111	struct {
3112	uint32_t:27;
3113	uint32_t RFC_PAUSE:1;
3114	uint32_t TFC_PAUSE:1;
3115	uint32_t FDEN:1;
3116	uint32_t HBC:1;
3117	uint32_t GTS:1;
3118	} B;
3119	} TCR; /* Transmit Control Register */
3120
3121	uint32_t fec_reserved_tcr[7];
3122
3123	union {
3124	uint32_t R;
3125	struct {
3126	uint32_t PADDR1:32;
3127	} B;
3128	} PALR; /* Physical Address Low Register */
3129
3130	union {
3131	uint32_t R;
3132	struct {
3133	uint32_t PADDR2:16;
3134	uint32_t TYPE:16;
3135	} B;
3136	} PAUR; /* Physical Address High + Type Register */
3137
3138	union {
3139	uint32_t R;
3140	struct {
3141	uint32_t OPCODE:16;
3142	uint32_t PAUSE_DUR:16;
3143	} B;
3144	} OPD; /* Opcode/Pause Duration Register */
3145
3146	uint32_t fec_reserved_opd[10];
3147
3148	union {
3149	uint32_t R;
3150	struct {
3151	uint32_t IADDR1:32;
3152	} B;
3153	} IAUR; /* Descriptor Individual Upper Address Register */
3154
3155	union {
3156	uint32_t R;
3157	struct {
3158	uint32_t IADDR2:32;
3159	} B;
3160	} IALR; /* Descriptor Individual Lower Address Register */
3161
3162	union {
3163	uint32_t R;
3164	struct {
3165	uint32_t GADDR1:32;
3166	} B;
3167	} GAUR; /* Descriptor Group Upper Address Register */
3168
3169	union {
3170	uint32_t R;
3171	struct {
3172	uint32_t GADDR2:32;
3173	} B;
3174	} GALR; /* Descriptor Group Lower Address Register */
3175
3176	uint32_t fec_reserved_galr[7];
3177
3178	union {
3179	uint32_t R;
3180	struct {
3181	uint32_t:30;
3182	uint32_t X_WMRK:2;
3183	} B;
3184	} TFWR; /* FIFO Transmit FIFO Watermark Register */
3185
3186	uint32_t fec_reserved_tfwr;
3187
3188	union {
3189	uint32_t R;
3190	struct {
3191	uint32_t:22;
3192	uint32_t R_BOUND:8;
3193	uint32_t:2;
3194	} B;
3195	} FRBR; /* FIFO Receive Bound Register */
3196
3197	union {
3198	uint32_t R;
3199	struct {
3200	uint32_t:22;
3201	uint32_t R_FSTART:8;
3202	uint32_t:2;
3203	} B;
3204	} FRSR; /* FIFO Receive Start Register */
3205
3206	uint32_t fec_reserved_frsr[11];
3207
3208	union {
3209	uint32_t R;
3210	struct {
3211	uint32_t R_DES_START:30;
3212	uint32_t:2;
3213	} B;
3214	} ERDSR; /* Receive Descriptor Ring Start Register */
3215
3216	union {
3217	uint32_t R;
3218	struct {
3219	uint32_t X_DES_START:30;
3220	uint32_t:2;
3221	} B;
3222	} ETDSR; /* Transmit Descriptor Ring Start Register */
3223
3224	union {
3225	uint32_t R;
3226	struct {
3227	uint32_t:21;
3228	uint32_t R_BUF_SIZE:7;
3229	uint32_t:4;
3230	} B;
3231	} EMRBR; /* Receive Buffer Size Register */
3232
3233	uint32_t fec_reserved_emrbr[29];
3234
3235	union {
3236	uint32_t R;
3237	} RMON_T_DROP; /* Count of frames not counted correctly */
3238
3239	union {
3240	uint32_t R;
3241	} RMON_T_PACKETS; /* RMON Tx packet count */
3242
3243	union {
3244	uint32_t R;
3245	} RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */
3246
3247	union {
3248	uint32_t R;
3249	} RMON_T_MC_PKT; /* RMON Tx Multicast Packets */
3250
3251	union {
3252	uint32_t R;
3253	} RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */
3254
3255	union {
3256	uint32_t R;
3257	} RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */
3258
3259	union {
3260	uint32_t R;
3261	} RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */
3262
3263	union {
3264	uint32_t R;
3265	} RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */
3266
3267	union {
3268	uint32_t R;
3269	} RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */
3270
3271	union {
3272	uint32_t R;
3273	} RMON_T_COL; /* RMON Tx collision count */
3274
3275	union {
3276	uint32_t R;
3277	} RMON_T_P64; /* RMON Tx 64 byte packets */
3278
3279	union {
3280	uint32_t R;
3281	} RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */
3282
3283	union {
3284	uint32_t R;
3285	} RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */
3286
3287	union {
3288	uint32_t R;
3289	} RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */
3290
3291	union {
3292	uint32_t R;
3293	} RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */
3294
3295	union {
3296	uint32_t R;
3297	} RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */
3298
3299	union {
3300	uint32_t R;
3301	} RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */
3302
3303	union {
3304	uint32_t R;
3305	} RMON_T_OCTETS; /* RMON Tx Octets */
3306
3307	union {
3308	uint32_t R;
3309	} IEEE_T_DROP; /* Count of frames not counted correctly */
3310
3311	union {
3312	uint32_t R;
3313	} IEEE_T_FRAME_OK; /* Frames Transmitted OK */
3314
3315	union {
3316	uint32_t R;
3317	} IEEE_T_1COL; /* Frames Transmitted with Single Collision */
3318
3319	union {
3320	uint32_t R;
3321	} IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */
3322
3323	union {
3324	uint32_t R;
3325	} IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */
3326
3327	union {
3328	uint32_t R;
3329	} IEEE_T_LCOL; /* Frames Transmitted with Late Collision */
3330
3331	union {
3332	uint32_t R;
3333	} IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */
3334
3335	union {
3336	uint32_t R;
3337	} IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */
3338
3339	union {
3340	uint32_t R;
3341	} IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */
3342
3343	union {
3344	uint32_t R;
3345	} IEEE_T_SQE; /* Frames Transmitted with SQE Error */
3346
3347	union {
3348	uint32_t R;
3349	} IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */
3350
3351	union {
3352	uint32_t R;
3353	} IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */
3354
3355	uint32_t fec_reserved_rmon_t_octets_ok[2];
3356
3357	union {
3358	uint32_t R;
3359	} RMON_R_DROP; /* Count of frames not counted correctly */
3360
3361	union {
3362	uint32_t R;
3363	} RMON_R_PACKETS; /* RMON Rx packet count */
3364
3365	union {
3366	uint32_t R;
3367	} RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */
3368
3369	union {
3370	uint32_t R;
3371	} RMON_R_MC_PKT; /* RMON Rx Multicast Packets */
3372
3373	union {
3374	uint32_t R;
3375	} RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */
3376
3377	union {
3378	uint32_t R;
3379	} RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */
3380
3381	union {
3382	uint32_t R;
3383	} RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */
3384
3385	union {
3386	uint32_t R;
3387	} RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */
3388
3389	union {
3390	uint32_t R;
3391	} RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */
3392
3393	uint32_t fec_reserved_rmon_r_jab;
3394
3395	union {
3396	uint32_t R;
3397	} RMON_R_P64; /* RMON Rx 64 byte packets */
3398
3399	union {
3400	uint32_t R;
3401	} RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */
3402
3403	union {
3404	uint32_t R;
3405	} RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */
3406
3407	union {
3408	uint32_t R;
3409	} RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */
3410
3411	union {
3412	uint32_t R;
3413	} RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */
3414
3415	union {
3416	uint32_t R;
3417	} RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */
3418
3419	union {
3420	uint32_t R;
3421	} RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */
3422
3423	union {
3424	uint32_t R;
3425	} RMON_R_OCTETS; /* RMON Rx Octets */
3426
3427	union {
3428	uint32_t R;
3429	} IEEE_R_DROP; /* Count of frames not counted correctly */
3430
3431	union {
3432	uint32_t R;
3433	} IEEE_R_FRAME_OK; /* Frames Received OK */
3434
3435	union {
3436	uint32_t R;
3437	} IEEE_R_CRC; /* Frames Received with CRC Error */
3438
3439	union {
3440	uint32_t R;
3441	} IEEE_R_ALIGN; /* Frames Received with Alignment Error */
3442
3443	union {
3444	uint32_t R;
3445	} IEEE_R_MACERR; /* Receive Fifo Overflow count */
3446
3447	union {
3448	uint32_t R;
3449	} IEEE_R_FDXFC; /* Flow Control Pause frames received */
3450
3451	union {
3452	uint32_t R;
3453	} IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */
3454
3455	};
3456	/****************************************************************************/
3457	/* MODULE : FlexRay */
3458	/****************************************************************************/
3459
3460	typedef union uMVR {
3461	uint16_t R;
3462	struct {
3463	uint16_t CHIVER:8; /* CHI Version Number */
3464	uint16_t PEVER:8; /* PE Version Number */
3465	} B;
3466	} MVR_t;
3467
3468	typedef union uMCR {
3469	uint16_t R;
3470	struct {
3471	uint16_t MEN:1; /* module enable */
3472	uint16_t:1;
3473	uint16_t SCMD:1; /* single channel mode */
3474	uint16_t CHB:1; /* channel B enable */
3475	uint16_t CHA:1; /* channel A enable */
3476	uint16_t SFFE:1; /* synchronization frame filter enable */
3477	uint16_t:5;
3478	uint16_t CLKSEL:1; /* protocol engine clock source select */
3479	uint16_t PRESCALE:3; /* protocol engine clock prescaler */
3480	uint16_t:1;
3481	} B;
3482	} MCR_t;
3483	typedef union uSTBSCR {
3484	uint16_t R;
3485	struct {
3486	uint16_t WMD:1; /* write mode */
3487	uint16_t STBSSEL:7; /* strobe signal select */
3488	uint16_t:3;
3489	uint16_t ENB:1; /* strobe signal enable */
3490	uint16_t:2;
3491	uint16_t STBPSEL:2; /* strobe port select */
3492	} B;
3493	} STBSCR_t;
3494	typedef union uSTBPCR {
3495	uint16_t R;
3496	struct {
3497	uint16_t:12;
3498	uint16_t STB3EN:1; /* strobe port enable */
3499	uint16_t STB2EN:1; /* strobe port enable */
3500	uint16_t STB1EN:1; /* strobe port enable */
3501	uint16_t STB0EN:1; /* strobe port enable */
3502	} B;
3503	} STBPCR_t;
3504
3505	typedef union uMBDSR {
3506	uint16_t R;
3507	struct {
3508	uint16_t:1;
3509	uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
3510	uint16_t:1;
3511	uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
3512	} B;
3513	} MBDSR_t;
3514	typedef union uMBSSUTR {
3515	uint16_t R;
3516	struct {
3517
3518	uint16_t:1;
3519	uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */
3520	uint16_t:1;
3521	uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */
3522	} B;
3523	} MBSSUTR_t;
3524
3525	typedef union uPOCR {
3526	uint16_t R;
3527	uint8_t byte[2];
3528	struct {
3529	uint16_t WME:1; /* write mode external correction command */
3530	uint16_t:3;
3531	uint16_t EOC_AP:2; /* external offset correction application */
3532	uint16_t ERC_AP:2; /* external rate correction application */
3533	uint16_t BSY:1; /* command write busy / write mode command */
3534	uint16_t:3;
3535	uint16_t POCCMD:4; /* protocol command */
3536	} B;
3537	} POCR_t;
3538	/* protocol commands */
3539	typedef union uGIFER {
3540	uint16_t R;
3541	struct {
3542	uint16_t MIF:1; /* module interrupt flag */
3543	uint16_t PRIF:1; /* protocol interrupt flag */
3544	uint16_t CHIF:1; /* CHI interrupt flag */
3545	uint16_t WKUPIF:1; /* wakeup interrupt flag */
3546	uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
3547	uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
3548	uint16_t RBIF:1; /* receive message buffer interrupt flag */
3549	uint16_t TBIF:1; /* transmit buffer interrupt flag */
3550	uint16_t MIE:1; /* module interrupt enable */
3551	uint16_t PRIE:1; /* protocol interrupt enable */
3552	uint16_t CHIE:1; /* CHI interrupt enable */
3553	uint16_t WKUPIE:1; /* wakeup interrupt enable */
3554	uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
3555	uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
3556	uint16_t RBIE:1; /* receive message buffer interrupt enable */
3557	uint16_t TBIE:1; /* transmit buffer interrupt enable */
3558	} B;
3559	} GIFER_t;
3560	typedef union uPIFR0 {
3561	uint16_t R;
3562	struct {
3563	uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
3564	uint16_t INTLIF:1; /* internal protocol error interrupt flag */
3565	uint16_t ILCFIF:1; /* illegal protocol configuration flag */
3566	uint16_t CSAIF:1; /* cold start abort interrupt flag */
3567	uint16_t MRCIF:1; /* missing rate correctio interrupt flag */
3568	uint16_t MOCIF:1; /* missing offset correctio interrupt flag */
3569	uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
3570	uint16_t MXSIF:1; /* max sync frames detected interrupt flag */
3571	uint16_t MTXIF:1; /* media access test symbol received flag */
3572	uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
3573	uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
3574	uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
3575	uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
3576	uint16_t TI2IF:1; /* timer 2 expired interrupt flag */
3577	uint16_t TI1IF:1; /* timer 1 expired interrupt flag */
3578	uint16_t CYSIF:1; /* cycle start interrupt flag */
3579	} B;
3580	} PIFR0_t;
3581	typedef union uPIFR1 {
3582	uint16_t R;
3583	struct {
3584	uint16_t EMCIF:1; /* error mode changed interrupt flag */
3585	uint16_t IPCIF:1; /* illegal protocol command interrupt flag */
3586	uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
3587	uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
3588	uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
3589	uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
3590	uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
3591	uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
3592	uint16_t:2;
3593	uint16_t EVTIF:1; /* even cycle table written interrupt flag */
3594	uint16_t ODTIF:1; /* odd cycle table written interrupt flag */
3595	uint16_t:4;
3596	} B;
3597	} PIFR1_t;
3598	typedef union uPIER0 {
3599	uint16_t R;
3600	struct {
3601	uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
3602	uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
3603	uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
3604	uint16_t CSAIE:1; /* cold start abort interrupt enable */
3605	uint16_t MRCIE:1; /* missing rate correctio interrupt enable */
3606	uint16_t MOCIE:1; /* missing offset correctio interrupt enable */
3607	uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
3608	uint16_t MXSIE:1; /* max sync frames detected interrupt enable */
3609	uint16_t MTXIE:1; /* media access test symbol received interrupt enable */
3610	uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
3611	uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
3612	uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
3613	uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
3614	uint16_t TI2IE:1; /* timer 2 expired interrupt enable */
3615	uint16_t TI1IE:1; /* timer 1 expired interrupt enable */
3616	uint16_t CYSIE:1; /* cycle start interrupt enable */
3617	} B;
3618	} PIER0_t;
3619	typedef union uPIER1 {
3620	uint16_t R;
3621	struct {
3622	uint16_t EMCIE:1; /* error mode changed interrupt enable */
3623	uint16_t IPCIE:1; /* illegal protocol command interrupt enable */
3624	uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
3625	uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
3626	uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
3627	uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
3628	uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
3629	uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
3630	uint16_t:2;
3631	uint16_t EVTIE:1; /* even cycle table written interrupt enable */
3632	uint16_t ODTIE:1; /* odd cycle table written interrupt enable */
3633	uint16_t:4;
3634	} B;
3635	} PIER1_t;
3636	typedef union uCHIERFR {
3637	uint16_t R;
3638	struct {
3639	uint16_t FRLBEF:1; /* flame lost channel B error flag */
3640	uint16_t FRLAEF:1; /* frame lost channel A error flag */
3641	uint16_t PCMIEF:1; /* command ignored error flag */
3642	uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
3643	uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
3644	uint16_t MSBEF:1; /* message buffer search error flag */
3645	uint16_t MBUEF:1; /* message buffer utilization error flag */
3646	uint16_t LCKEF:1; /* lock error flag */
3647	uint16_t DBLEF:1; /* double transmit message buffer lock error flag */
3648	uint16_t SBCFEF:1; /* system bus communication failure error flag */
3649	uint16_t FIDEF:1; /* frame ID error flag */
3650	uint16_t DPLEF:1; /* dynamic payload length error flag */
3651	uint16_t SPLEF:1; /* static payload length error flag */
3652	uint16_t NMLEF:1; /* network management length error flag */
3653	uint16_t NMFEF:1; /* network management frame error flag */
3654	uint16_t ILSAEF:1; /* illegal access error flag */
3655	} B;
3656	} CHIERFR_t;
3657	typedef union uMBIVEC {
3658	uint16_t R;
3659	struct {
3660
3661	uint16_t:1;
3662	uint16_t TBIVEC:7; /* transmit buffer interrupt vector */
3663	uint16_t:1;
3664	uint16_t RBIVEC:7; /* receive buffer interrupt vector */
3665	} B;
3666	} MBIVEC_t;
3667
3668	typedef union uPSR0 {
3669	uint16_t R;
3670	struct {
3671	uint16_t ERRMODE:2; /* error mode */
3672	uint16_t SLOTMODE:2; /* slot mode */
3673	uint16_t:1;
3674	uint16_t PROTSTATE:3; /* protocol state */
3675	uint16_t SUBSTATE:4; /* protocol sub state */
3676	uint16_t:1;
3677	uint16_t WAKEUPSTATUS:3; /* wakeup status */
3678	} B;
3679	} PSR0_t;
3680
3681	/* protocol states */
3682	/* protocol sub-states */
3683	/* wakeup status */
3684	typedef union uPSR1 {
3685	uint16_t R;
3686	struct {
3687	uint16_t CSAA:1; /* cold start attempt abort flag */
3688	uint16_t SCP:1; /* cold start path */
3689	uint16_t:1;
3690	uint16_t REMCSAT:5; /* remanining coldstart attempts */
3691	uint16_t CPN:1; /* cold start noise path */
3692	uint16_t HHR:1; /* host halt request pending */
3693	uint16_t FRZ:1; /* freeze occured */
3694	uint16_t APTAC:5; /* allow passive to active counter */
3695	} B;
3696	} PSR1_t;
3697	typedef union uPSR2 {
3698	uint16_t R;
3699	struct {
3700	uint16_t NBVB:1; /* NIT boundary violation on channel B */
3701	uint16_t NSEB:1; /* NIT syntax error on channel B */
3702	uint16_t STCB:1; /* symbol window transmit conflict on channel B */
3703	uint16_t SBVB:1; /* symbol window boundary violation on channel B */
3704	uint16_t SSEB:1; /* symbol window syntax error on channel B */
3705	uint16_t MTB:1; /* media access test symbol MTS received on channel B */
3706	uint16_t NBVA:1; /* NIT boundary violation on channel A */
3707	uint16_t NSEA:1; /* NIT syntax error on channel A */
3708	uint16_t STCA:1; /* symbol window transmit conflict on channel A */
3709	uint16_t SBVA:1; /* symbol window boundary violation on channel A */
3710	uint16_t SSEA:1; /* symbol window syntax error on channel A */
3711	uint16_t MTA:1; /* media access test symbol MTS received on channel A */
3712	uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
3713	} B;
3714	} PSR2_t;
3715	typedef union uPSR3 {
3716	uint16_t R;
3717	struct {
3718	uint16_t:2;
3719	uint16_t WUB:1; /* wakeup symbol received on channel B */
3720	uint16_t ABVB:1; /* aggregated boundary violation on channel B */
3721	uint16_t AACB:1; /* aggregated additional communication on channel B */
3722	uint16_t ACEB:1; /* aggregated content error on channel B */
3723	uint16_t ASEB:1; /* aggregated syntax error on channel B */
3724	uint16_t AVFB:1; /* aggregated valid frame on channel B */
3725	uint16_t:2;
3726	uint16_t WUA:1; /* wakeup symbol received on channel A */
3727	uint16_t ABVA:1; /* aggregated boundary violation on channel A */
3728	uint16_t AACA:1; /* aggregated additional communication on channel A */
3729	uint16_t ACEA:1; /* aggregated content error on channel A */
3730	uint16_t ASEA:1; /* aggregated syntax error on channel A */
3731	uint16_t AVFA:1; /* aggregated valid frame on channel A */
3732	} B;
3733	} PSR3_t;
3734	typedef union uCIFRR {
3735	uint16_t R;
3736	struct {
3737	uint16_t:8;
3738	uint16_t MIFR:1; /* module interrupt flag */
3739	uint16_t PRIFR:1; /* protocol interrupt flag */
3740	uint16_t CHIFR:1; /* CHI interrupt flag */
3741	uint16_t WUPIFR:1; /* wakeup interrupt flag */
3742	uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
3743	uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
3744	uint16_t RBIFR:1; /* receive message buffer interrupt flag */
3745	uint16_t TBIFR:1; /* transmit buffer interrupt flag */
3746	} B;
3747	} CIFRR_t;
3748	typedef union uSFCNTR {
3749	uint16_t R;
3750	struct {
3751	uint16_t SFEVB:4; /* sync frames channel B, even cycle */
3752	uint16_t SFEVA:4; /* sync frames channel A, even cycle */
3753	uint16_t SFODB:4; /* sync frames channel B, odd cycle */
3754	uint16_t SFODA:4; /* sync frames channel A, odd cycle */
3755	} B;
3756	} SFCNTR_t;
3757
3758	typedef union uSFTCCSR {
3759	uint16_t R;
3760	struct {
3761	uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
3762	uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
3763	uint16_t CYCNUM:6; /* cycle number */
3764	uint16_t ELKS:1; /* even cycle tables lock status */
3765	uint16_t OLKS:1; /* odd cycle tables lock status */
3766	uint16_t EVAL:1; /* even cycle tables valid */
3767	uint16_t OVAL:1; /* odd cycle tables valid */
3768	uint16_t:1;
3769	uint16_t OPT:1; /one pair trigger /
3770	uint16_t SDVEN:1; /* sync frame deviation table enable */
3771	uint16_t SIDEN:1; /* sync frame ID table enable */
3772	} B;
3773	} SFTCCSR_t;
3774	typedef union uSFIDRFR {
3775	uint16_t R;
3776	struct {
3777	uint16_t:6;
3778	uint16_t SYNFRID:10; /* sync frame rejection ID */
3779	} B;
3780	} SFIDRFR_t;
3781
3782	typedef union uTICCR {
3783	uint16_t R;
3784	struct {
3785	uint16_t:2;
3786	uint16_t T2CFG:1; /* timer 2 configuration */
3787	uint16_t T2REP:1; /* timer 2 repetitive mode */
3788	uint16_t:1;
3789	uint16_t T2SP:1; /* timer 2 stop */
3790	uint16_t T2TR:1; /* timer 2 trigger */
3791	uint16_t T2ST:1; /* timer 2 state */
3792	uint16_t:3;
3793	uint16_t T1REP:1; /* timer 1 repetitive mode */
3794	uint16_t:1;
3795	uint16_t T1SP:1; /* timer 1 stop */
3796	uint16_t T1TR:1; /* timer 1 trigger */
3797	uint16_t T1ST:1; /* timer 1 state */
3798
3799	} B;
3800	} TICCR_t;
3801	typedef union uTI1CYSR {
3802	uint16_t R;
3803	struct {
3804	uint16_t:2;
3805	uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
3806	uint16_t:2;
3807	uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
3808
3809	} B;
3810	} TI1CYSR_t;
3811
3812	typedef union uSSSR {
3813	uint16_t R;
3814	struct {
3815	uint16_t WMD:1; /* write mode */
3816	uint16_t:1;
3817	uint16_t SEL:2; /* static slot number */
3818	uint16_t:1;
3819	uint16_t SLOTNUMBER:11; /* selector */
3820	} B;
3821	} SSSR_t;
3822
3823	typedef union uSSCCR {
3824	uint16_t R;
3825	struct {
3826	uint16_t WMD:1; /* write mode */
3827	uint16_t:1;
3828	uint16_t SEL:2; /* selector */
3829	uint16_t:1;
3830	uint16_t CNTCFG:2; /* counter configuration */
3831	uint16_t MCY:1; /* multi cycle selection */
3832	uint16_t VFR:1; /* valid frame selection */
3833	uint16_t SYF:1; /* sync frame selection */
3834	uint16_t NUF:1; /* null frame selection */
3835	uint16_t SUF:1; /* startup frame selection */
3836	uint16_t STATUSMASK:4; /* slot status mask */
3837	} B;
3838	} SSCCR_t;
3839	typedef union uSSR {
3840	uint16_t R;
3841	struct {
3842	uint16_t VFB:1; /* valid frame on channel B */
3843	uint16_t SYB:1; /* valid sync frame on channel B */
3844	uint16_t NFB:1; /* valid null frame on channel B */
3845	uint16_t SUB:1; /* valid startup frame on channel B */
3846	uint16_t SEB:1; /* syntax error on channel B */
3847	uint16_t CEB:1; /* content error on channel B */
3848	uint16_t BVB:1; /* boundary violation on channel B */
3849	uint16_t TCB:1; /* tx conflict on channel B */
3850	uint16_t VFA:1; /* valid frame on channel A */
3851	uint16_t SYA:1; /* valid sync frame on channel A */
3852	uint16_t NFA:1; /* valid null frame on channel A */
3853	uint16_t SUA:1; /* valid startup frame on channel A */
3854	uint16_t SEA:1; /* syntax error on channel A */
3855	uint16_t CEA:1; /* content error on channel A */
3856	uint16_t BVA:1; /* boundary violation on channel A */
3857	uint16_t TCA:1; /* tx conflict on channel A */
3858	} B;
3859	} SSR_t;
3860	typedef union uMTSCFR {
3861	uint16_t R;
3862	struct {
3863	uint16_t MTE:1; /* media access test symbol transmission enable */
3864	uint16_t:1;
3865	uint16_t CYCCNTMSK:6; /* cycle counter mask */
3866	uint16_t:2;
3867	uint16_t CYCCNTVAL:6; /* cycle counter value */
3868	} B;
3869	} MTSCFR_t;
3870	typedef union uRSBIR {
3871	uint16_t R;
3872	struct {
3873	uint16_t WMD:1; /* write mode */
3874	uint16_t:1;
3875	uint16_t SEL:2; /* selector */
3876	uint16_t:4;
3877	uint16_t RSBIDX:8; /* receive shadow buffer index */
3878	} B;
3879	} RSBIR_t;
3880	typedef union uRFDSR {
3881	uint16_t R;
3882	struct {
3883	uint16_t FIFODEPTH:8; /* fifo depth */
3884	uint16_t:1;
3885	uint16_t ENTRYSIZE:7; /* entry size */
3886	} B;
3887	} RFDSR_t;
3888
3889	typedef union uRFRFCFR {
3890	uint16_t R;
3891	struct {
3892	uint16_t WMD:1; /* write mode */
3893	uint16_t IBD:1; /* interval boundary */
3894	uint16_t SEL:2; /* filter number */
3895	uint16_t:1;
3896	uint16_t SID:11; /* slot ID */
3897	} B;
3898	} RFRFCFR_t;
3899
3900	typedef union uRFRFCTR {
3901	uint16_t R;
3902	struct {
3903	uint16_t:4;
3904	uint16_t F3MD:1; /* filter mode */
3905	uint16_t F2MD:1; /* filter mode */
3906	uint16_t F1MD:1; /* filter mode */
3907	uint16_t F0MD:1; /* filter mode */
3908	uint16_t:4;
3909	uint16_t F3EN:1; /* filter enable */
3910	uint16_t F2EN:1; /* filter enable */
3911	uint16_t F1EN:1; /* filter enable */
3912	uint16_t F0EN:1; /* filter enable */
3913	} B;
3914	} RFRFCTR_t;
3915	typedef union uPCR0 {
3916	uint16_t R;
3917	struct {
3918	uint16_t ACTION_POINT_OFFSET:6;
3919	uint16_t STATIC_SLOT_LENGTH:10;
3920	} B;
3921	} PCR0_t;
3922
3923	typedef union uPCR1 {
3924	uint16_t R;
3925	struct {
3926	uint16_t:2;
3927	uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3928	} B;
3929	} PCR1_t;
3930
3931	typedef union uPCR2 {
3932	uint16_t R;
3933	struct {
3934	uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3935	uint16_t NUMBER_OF_STATIC_SLOTS:10;
3936	} B;
3937	} PCR2_t;
3938
3939	typedef union uPCR3 {
3940	uint16_t R;
3941	struct {
3942	uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3943	uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3944	uint16_t COLDSTART_ATTEMPTS:5;
3945	} B;
3946	} PCR3_t;
3947
3948	typedef union uPCR4 {
3949	uint16_t R;
3950	struct {
3951	uint16_t CAS_RX_LOW_MAX:7;
3952	uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3953	} B;
3954	} PCR4_t;
3955
3956	typedef union uPCR5 {
3957	uint16_t R;
3958	struct {
3959	uint16_t TSS_TRANSMITTER:4;
3960	uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3961	uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3962	} B;
3963	} PCR5_t;
3964
3965	typedef union uPCR6 {
3966	uint16_t R;
3967	struct {
3968	uint16_t:1;
3969	uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3970	uint16_t MACRO_INITIAL_OFFSET_A:7;
3971	} B;
3972	} PCR6_t;
3973
3974	typedef union uPCR7 {
3975	uint16_t R;
3976	struct {
3977	uint16_t DECODING_CORRECTION_B:9;
3978	uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3979	} B;
3980	} PCR7_t;
3981
3982	typedef union uPCR8 {
3983	uint16_t R;
3984	struct {
3985	uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3986	uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3987	uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3988	} B;
3989	} PCR8_t;
3990
3991	typedef union uPCR9 {
3992	uint16_t R;
3993	struct {
3994	uint16_t MINISLOT_EXISTS:1;
3995	uint16_t SYMBOL_WINDOW_EXISTS:1;
3996	uint16_t OFFSET_CORRECTION_OUT:14;
3997	} B;
3998	} PCR9_t;
3999
4000	typedef union uPCR10 {
4001	uint16_t R;
4002	struct {
4003	uint16_t SINGLE_SLOT_ENABLED:1;
4004	uint16_t WAKEUP_CHANNEL:1;
4005	uint16_t MACRO_PER_CYCLE:14;
4006	} B;
4007	} PCR10_t;
4008
4009	typedef union uPCR11 {
4010	uint16_t R;
4011	struct {
4012	uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
4013	uint16_t KEY_SLOT_USED_FOR_SYNC:1;
4014	uint16_t OFFSET_CORRECTION_START:14;
4015	} B;
4016	} PCR11_t;
4017
4018	typedef union uPCR12 {
4019	uint16_t R;
4020	struct {
4021	uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
4022	uint16_t KEY_SLOT_HEADER_CRC:11;
4023	} B;
4024	} PCR12_t;
4025
4026	typedef union uPCR13 {
4027	uint16_t R;
4028	struct {
4029	uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
4030	uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
4031	} B;
4032	} PCR13_t;
4033
4034	typedef union uPCR14 {
4035	uint16_t R;
4036	struct {
4037	uint16_t RATE_CORRECTION_OUT:11;
4038	uint16_t LISTEN_TIMEOUT_H:5;
4039	} B;
4040	} PCR14_t;
4041
4042	typedef union uPCR15 {
4043	uint16_t R;
4044	struct {
4045	uint16_t LISTEN_TIMEOUT_L:16;
4046	} B;
4047	} PCR15_t;
4048
4049	typedef union uPCR16 {
4050	uint16_t R;
4051	struct {
4052	uint16_t MACRO_INITIAL_OFFSET_B:7;
4053	uint16_t NOISE_LISTEN_TIMEOUT_H:9;
4054	} B;
4055	} PCR16_t;
4056
4057	typedef union uPCR17 {
4058	uint16_t R;
4059	struct {
4060	uint16_t NOISE_LISTEN_TIMEOUT_L:16;
4061	} B;
4062	} PCR17_t;
4063
4064	typedef union uPCR18 {
4065	uint16_t R;
4066	struct {
4067	uint16_t WAKEUP_PATTERN:6;
4068	uint16_t KEY_SLOT_ID:10;
4069	} B;
4070	} PCR18_t;
4071
4072	typedef union uPCR19 {
4073	uint16_t R;
4074	struct {
4075	uint16_t DECODING_CORRECTION_A:9;
4076	uint16_t PAYLOAD_LENGTH_STATIC:7;
4077	} B;
4078	} PCR19_t;
4079
4080	typedef union uPCR20 {
4081	uint16_t R;
4082	struct {
4083	uint16_t MICRO_INITIAL_OFFSET_B:8;
4084	uint16_t MICRO_INITIAL_OFFSET_A:8;
4085	} B;
4086	} PCR20_t;
4087
4088	typedef union uPCR21 {
4089	uint16_t R;
4090	struct {
4091	uint16_t EXTERN_RATE_CORRECTION:3;
4092	uint16_t LATEST_TX:13;
4093	} B;
4094	} PCR21_t;
4095
4096	typedef union uPCR22 {
4097	uint16_t R;
4098	struct {
4099	uint16_t:1;
4100	uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
4101	uint16_t MICRO_PER_CYCLE_H:4;
4102	} B;
4103	} PCR22_t;
4104
4105	typedef union uPCR23 {
4106	uint16_t R;
4107	struct {
4108	uint16_t micro_per_cycle_l:16;
4109	} B;
4110	} PCR23_t;
4111
4112	typedef union uPCR24 {
4113	uint16_t R;
4114	struct {
4115	uint16_t CLUSTER_DRIFT_DAMPING:5;
4116	uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
4117	uint16_t MICRO_PER_CYCLE_MIN_H:4;
4118	} B;
4119	} PCR24_t;
4120
4121	typedef union uPCR25 {
4122	uint16_t R;
4123	struct {
4124	uint16_t MICRO_PER_CYCLE_MIN_L:16;
4125	} B;
4126	} PCR25_t;
4127
4128	typedef union uPCR26 {
4129	uint16_t R;
4130	struct {
4131	uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
4132	uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
4133	uint16_t MICRO_PER_CYCLE_MAX_H:4;
4134	} B;
4135	} PCR26_t;
4136
4137	typedef union uPCR27 {
4138	uint16_t R;
4139	struct {
4140	uint16_t MICRO_PER_CYCLE_MAX_L:16;
4141	} B;
4142	} PCR27_t;
4143
4144	typedef union uPCR28 {
4145	uint16_t R;
4146	struct {
4147	uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
4148	uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
4149	} B;
4150	} PCR28_t;
4151
4152	typedef union uPCR29 {
4153	uint16_t R;
4154	struct {
4155	uint16_t EXTERN_OFFSET_CORRECTION:3;
4156	uint16_t MINISLOTS_MAX:13;
4157	} B;
4158	} PCR29_t;
4159
4160	typedef union uPCR30 {
4161	uint16_t R;
4162	struct {
4163	uint16_t:12;
4164	uint16_t SYNC_NODE_MAX:4;
4165	} B;
4166	} PCR30_t;
4167
4168	typedef struct uMSG_BUFF_CCS {
4169	union {
4170	uint16_t R;
4171	struct {
4172	uint16_t:1;
4173	uint16_t MCM:1; /* message buffer commit mode */
4174	uint16_t MBT:1; /* message buffer type */
4175	uint16_t MTD:1; /* message buffer direction */
4176	uint16_t CMT:1; /* commit for transmission */
4177	uint16_t EDT:1; /* enable / disable trigger */
4178	uint16_t LCKT:1; /* lock request trigger */
4179	uint16_t MBIE:1; /* message buffer interrupt enable */
4180	uint16_t:3;
4181	uint16_t DUP:1; /* data updated */
4182	uint16_t DVAL:1; /* data valid */
4183	uint16_t EDS:1; /* lock status */
4184	uint16_t LCKS:1; /* enable / disable status */
4185	uint16_t MBIF:1; /* message buffer interrupt flag */
4186	} B;
4187	} MBCCSR;
4188	union {
4189	uint16_t R;
4190	struct {
4191	uint16_t MTM:1; /* message buffer transmission mode */
4192	uint16_t CHNLA:1; /* channel assignement */
4193	uint16_t CHNLB:1; /* channel assignement */
4194	uint16_t CCFE:1; /* cycle counter filter enable */
4195	uint16_t CCFMSK:6; /* cycle counter filter mask */
4196	uint16_t CCFVAL:6; /* cycle counter filter value */
4197	} B;
4198	} MBCCFR;
4199	union {
4200	uint16_t R;
4201	struct {
4202	uint16_t:5;
4203	uint16_t FID:11; /* frame ID */
4204	} B;
4205	} MBFIDR;
4206	union {
4207	uint16_t R;
4208	struct {
4209	uint16_t:8;
4210	uint16_t MBIDX:8; /* message buffer index */
4211	} B;
4212	} MBIDXR;
4213	} MSG_BUFF_CCS_t;
4214	typedef union uSYSBADHR {
4215	uint16_t R;
4216	} SYSBADHR_t;
4217	typedef union uSYSBADLR {
4218	uint16_t R;
4219	} SYSBADLR_t;
4220	typedef union uPDAR {
4221	uint16_t R;
4222	} PDAR_t;
4223	typedef union uCASERCR {
4224	uint16_t R;
4225	} CASERCR_t;
4226	typedef union uCBSERCR {
4227	uint16_t R;
4228	} CBSERCR_t;
4229	typedef union uCYCTR {
4230	uint16_t R;
4231	} CYCTR_t;
4232	typedef union uMTCTR {
4233	uint16_t R;
4234	} MTCTR_t;
4235	typedef union uSLTCTAR {
4236	uint16_t R;
4237	} SLTCTAR_t;
4238	typedef union uSLTCTBR {
4239	uint16_t R;
4240	} SLTCTBR_t;
4241	typedef union uRTCORVR {
4242	uint16_t R;
4243	} RTCORVR_t;
4244	typedef union uOFCORVR {
4245	uint16_t R;
4246	} OFCORVR_t;
4247	typedef union uSFTOR {
4248	uint16_t R;
4249	} SFTOR_t;
4250	typedef union uSFIDAFVR {
4251	uint16_t R;
4252	} SFIDAFVR_t;
4253	typedef union uSFIDAFMR {
4254	uint16_t R;
4255	} SFIDAFMR_t;
4256	typedef union uNMVR {
4257	uint16_t R;
4258	} NMVR_t;
4259	typedef union uNMVLR {
4260	uint16_t R;
4261	} NMVLR_t;
4262	typedef union uT1MTOR {
4263	uint16_t R;
4264	} T1MTOR_t;
4265	typedef union uTI2CR0 {
4266	uint16_t R;
4267	} TI2CR0_t;
4268	typedef union uTI2CR1 {
4269	uint16_t R;
4270	} TI2CR1_t;
4271	typedef union uSSCR {
4272	uint16_t R;
4273	} SSCR_t;
4274	typedef union uRFSR {
4275	uint16_t R;
4276	} RFSR_t;
4277	typedef union uRFSIR {
4278	uint16_t R;
4279	} RFSIR_t;
4280	typedef union uRFARIR {
4281	uint16_t R;
4282	} RFARIR_t;
4283	typedef union uRFBRIR {
4284	uint16_t R;
4285	} RFBRIR_t;
4286	typedef union uRFMIDAFVR {
4287	uint16_t R;
4288	} RFMIDAFVR_t;
4289	typedef union uRFMIAFMR {
4290	uint16_t R;
4291	} RFMIAFMR_t;
4292	typedef union uRFFIDRFVR {
4293	uint16_t R;
4294	} RFFIDRFVR_t;
4295	typedef union uRFFIDRFMR {
4296	uint16_t R;
4297	} RFFIDRFMR_t;
4298	typedef union uLDTXSLAR {
4299	uint16_t R;
4300	} LDTXSLAR_t;
4301	typedef union uLDTXSLBR {
4302	uint16_t R;
4303	} LDTXSLBR_t;
4304
4305	typedef struct FR_tag {
4306	volatile MVR_t MVR; /module version register //0 /
4307	volatile MCR_t MCR; /module configuration register //2 /
4308	volatile SYSBADHR_t SYSBADHR; /system memory base address high register //4 /
4309	volatile SYSBADLR_t SYSBADLR; /system memory base address low register //6 /
4310	volatile STBSCR_t STBSCR; /strobe signal control register //8 /
4311	volatile STBPCR_t STBPCR; /strobe port control register //A /
4312	volatile MBDSR_t MBDSR; /message buffer data size register //C /
4313	volatile MBSSUTR_t MBSSUTR; /message buffer segment size and utilization register //E /
4314	uint16_t reserved3a[1]; /10 /
4315	volatile PDAR_t PDAR; /PE data register //12 /
4316	volatile POCR_t POCR; /Protocol operation control register //14 /
4317	volatile GIFER_t GIFER; /global interrupt flag and enable register //16 /
4318	volatile PIFR0_t PIFR0; /protocol interrupt flag register 0 //18 /
4319	volatile PIFR1_t PIFR1; /protocol interrupt flag register 1 //1A /
4320	volatile PIER0_t PIER0; /protocol interrupt enable register 0 //1C /
4321	volatile PIER1_t PIER1; /protocol interrupt enable register 1 //1E /
4322	volatile CHIERFR_t CHIERFR; /CHI error flag register //20 /
4323	volatile MBIVEC_t MBIVEC; /message buffer interrupt vector register //22 /
4324	volatile CASERCR_t CASERCR; /channel A status error counter register //24 /
4325	volatile CBSERCR_t CBSERCR; /channel B status error counter register //26 /
4326	volatile PSR0_t PSR0; /protocol status register 0 //28 /
4327	volatile PSR1_t PSR1; /protocol status register 1 //2A /
4328	volatile PSR2_t PSR2; /protocol status register 2 //2C /
4329	volatile PSR3_t PSR3; /protocol status register 3 //2E /
4330	volatile MTCTR_t MTCTR; /macrotick counter register //30 /
4331	volatile CYCTR_t CYCTR; /cycle counter register //32 /
4332	volatile SLTCTAR_t SLTCTAR; /slot counter channel A register //34 /
4333	volatile SLTCTBR_t SLTCTBR; /slot counter channel B register //36 /
4334	volatile RTCORVR_t RTCORVR; /rate correction value register //38 /
4335	volatile OFCORVR_t OFCORVR; /offset correction value register //3A /
4336	volatile CIFRR_t CIFRR; /combined interrupt flag register //3C /
4337	uint16_t reserved3[1]; /3E /
4338	volatile SFCNTR_t SFCNTR; /sync frame counter register //40 /
4339	volatile SFTOR_t SFTOR; /sync frame table offset register //42 /
4340	volatile SFTCCSR_t SFTCCSR; /sync frame table configuration, control, status register //44 /
4341	volatile SFIDRFR_t SFIDRFR; /sync frame ID rejection filter register //46 /
4342	volatile SFIDAFVR_t SFIDAFVR; /sync frame ID acceptance filter value regiater //48 /
4343	volatile SFIDAFMR_t SFIDAFMR; /sync frame ID acceptance filter mask register //4A /
4344	volatile NMVR_t NMVR[6]; /network management vector registers (12 bytes) //4C /
4345	volatile NMVLR_t NMVLR; /network management vector length register //58 /
4346	volatile TICCR_t TICCR; /timer configuration and control register //5A /
4347	volatile TI1CYSR_t TI1CYSR; /timer 1 cycle set register //5C /
4348	volatile T1MTOR_t T1MTOR; /timer 1 macrotick offset register //5E /
4349	volatile TI2CR0_t TI2CR0; /timer 2 configuration register 0 //60 /
4350	volatile TI2CR1_t TI2CR1; /timer 2 configuration register 1 //62 /
4351	volatile SSSR_t SSSR; /slot status selection register //64 /
4352	volatile SSCCR_t SSCCR; /slot status counter condition register //66 /
4353	volatile SSR_t SSR[8]; /slot status registers 0-7 //68 /
4354	volatile SSCR_t SSCR[4]; /slot status counter registers 0-3 //78 /
4355	volatile MTSCFR_t MTSACFR; /mts a config register //80 /
4356	volatile MTSCFR_t MTSBCFR; /mts b config register //82 /
4357	volatile RSBIR_t RSBIR; /receive shadow buffer index register //84 /
4358	volatile RFSR_t RFSR; /receive fifo selection register //86 /
4359	volatile RFSIR_t RFSIR; /receive fifo start index register //88 /
4360	volatile RFDSR_t RFDSR; /receive fifo depth and size register //8A /
4361	volatile RFARIR_t RFARIR; /receive fifo a read index register //8C /
4362	volatile RFBRIR_t RFBRIR; /receive fifo b read index register //8E /
4363	volatile RFMIDAFVR_t RFMIDAFVR; /receive fifo message ID acceptance filter value register //90 /
4364	volatile RFMIAFMR_t RFMIAFMR; /receive fifo message ID acceptance filter mask register //92 /
4365	volatile RFFIDRFVR_t RFFIDRFVR; /receive fifo frame ID rejection filter value register //94 /
4366	volatile RFFIDRFMR_t RFFIDRFMR; /receive fifo frame ID rejection filter mask register //96 /
4367	volatile RFRFCFR_t RFRFCFR; /receive fifo range filter configuration register //98 /
4368	volatile RFRFCTR_t RFRFCTR; /receive fifo range filter control register //9A /
4369	volatile LDTXSLAR_t LDTXSLAR; /last dynamic transmit slot channel A register //9C /
4370	volatile LDTXSLBR_t LDTXSLBR; /last dynamic transmit slot channel B register //9E /
4371	volatile PCR0_t PCR0; /protocol configuration register 0 //A0 /
4372	volatile PCR1_t PCR1; /protocol configuration register 1 //A2 /
4373	volatile PCR2_t PCR2; /protocol configuration register 2 //A4 /
4374	volatile PCR3_t PCR3; /protocol configuration register 3 //A6 /
4375	volatile PCR4_t PCR4; /protocol configuration register 4 //A8 /
4376	volatile PCR5_t PCR5; /protocol configuration register 5 //AA /
4377	volatile PCR6_t PCR6; /protocol configuration register 6 //AC /
4378	volatile PCR7_t PCR7; /protocol configuration register 7 //AE /
4379	volatile PCR8_t PCR8; /protocol configuration register 8 //B0 /
4380	volatile PCR9_t PCR9; /protocol configuration register 9 //B2 /
4381	volatile PCR10_t PCR10; /protocol configuration register 10 //B4 /
4382	volatile PCR11_t PCR11; /protocol configuration register 11 //B6 /
4383	volatile PCR12_t PCR12; /protocol configuration register 12 //B8 /
4384	volatile PCR13_t PCR13; /protocol configuration register 13 //BA /
4385	volatile PCR14_t PCR14; /protocol configuration register 14 //BC /
4386	volatile PCR15_t PCR15; /protocol configuration register 15 //BE /
4387	volatile PCR16_t PCR16; /protocol configuration register 16 //C0 /
4388	volatile PCR17_t PCR17; /protocol configuration register 17 //C2 /
4389	volatile PCR18_t PCR18; /protocol configuration register 18 //C4 /
4390	volatile PCR19_t PCR19; /protocol configuration register 19 //C6 /
4391	volatile PCR20_t PCR20; /protocol configuration register 20 //C8 /
4392	volatile PCR21_t PCR21; /protocol configuration register 21 //CA /
4393	volatile PCR22_t PCR22; /protocol configuration register 22 //CC /
4394	volatile PCR23_t PCR23; /protocol configuration register 23 //CE /
4395	volatile PCR24_t PCR24; /protocol configuration register 24 //D0 /
4396	volatile PCR25_t PCR25; /protocol configuration register 25 //D2 /
4397	volatile PCR26_t PCR26; /protocol configuration register 26 //D4 /
4398	volatile PCR27_t PCR27; /protocol configuration register 27 //D6 /
4399	volatile PCR28_t PCR28; /protocol configuration register 28 //D8 /
4400	volatile PCR29_t PCR29; /protocol configuration register 29 //DA /
4401	volatile PCR30_t PCR30; /protocol configuration register 30 //DC /
4402	uint16_t reserved2[17];
4403	volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 //100 */
4404	} FR_tag_t;
4405
4406	typedef union uF_HEADER /* frame header */
4407	{
4408	struct {
4409	uint16_t:5;
4410	uint16_t HDCRC:11; /* Header CRC */
4411	uint16_t:2;
4412	uint16_t CYCCNT:6; /* Cycle Count */
4413	uint16_t:1;
4414	uint16_t PLDLEN:7; /* Payload Length */
4415	uint16_t:1;
4416	uint16_t PPI:1; /* Payload Preamble Indicator */
4417	uint16_t NUF:1; /* Null Frame Indicator */
4418	uint16_t SYF:1; /* Sync Frame Indicator */
4419	uint16_t SUF:1; /* Startup Frame Indicator */
4420	uint16_t FID:11; /* Frame ID */
4421	} B;
4422	uint16_t WORDS[3];
4423	} F_HEADER_t;
4424	typedef union uS_STSTUS /* slot status */
4425	{
4426	struct {
4427	uint16_t VFB:1; /* Valid Frame on channel B */
4428	uint16_t SYB:1; /* Sync Frame Indicator channel B */
4429	uint16_t NFB:1; /* Null Frame Indicator channel B */
4430	uint16_t SUB:1; /* Startup Frame Indicator channel B */
4431	uint16_t SEB:1; /* Syntax Error on channel B */
4432	uint16_t CEB:1; /* Content Error on channel B */
4433	uint16_t BVB:1; /* Boundary Violation on channel B */
4434	uint16_t CH:1; /* Channel */
4435	uint16_t VFA:1; /* Valid Frame on channel A */
4436	uint16_t SYA:1; /* Sync Frame Indicator channel A */
4437	uint16_t NFA:1; /* Null Frame Indicator channel A */
4438	uint16_t SUA:1; /* Startup Frame Indicator channel A */
4439	uint16_t SEA:1; /* Syntax Error on channel A */
4440	uint16_t CEA:1; /* Content Error on channel A */
4441	uint16_t BVA:1; /* Boundary Violation on channel A */
4442	uint16_t:1;
4443	} RX;
4444	struct {
4445	uint16_t VFB:1; /* Valid Frame on channel B */
4446	uint16_t SYB:1; /* Sync Frame Indicator channel B */
4447	uint16_t NFB:1; /* Null Frame Indicator channel B */
4448	uint16_t SUB:1; /* Startup Frame Indicator channel B */
4449	uint16_t SEB:1; /* Syntax Error on channel B */
4450	uint16_t CEB:1; /* Content Error on channel B */
4451	uint16_t BVB:1; /* Boundary Violation on channel B */
4452	uint16_t TCB:1; /* Tx Conflict on channel B */
4453	uint16_t VFA:1; /* Valid Frame on channel A */
4454	uint16_t SYA:1; /* Sync Frame Indicator channel A */
4455	uint16_t NFA:1; /* Null Frame Indicator channel A */
4456	uint16_t SUA:1; /* Startup Frame Indicator channel A */
4457	uint16_t SEA:1; /* Syntax Error on channel A */
4458	uint16_t CEA:1; /* Content Error on channel A */
4459	uint16_t BVA:1; /* Boundary Violation on channel A */
4460	uint16_t TCA:1; /* Tx Conflict on channel A */
4461	} TX;
4462	uint16_t R;
4463	} S_STATUS_t;
4464
4465	typedef struct uMB_HEADER /* message buffer header */
4466	{
4467	F_HEADER_t FRAME_HEADER;
4468	uint16_t DATA_OFFSET;
4469	S_STATUS_t SLOT_STATUS;
4470	} MB_HEADER_t;
4471
4472	/* Define memories */
4473
4474	#define SRAM_START 0x40000000
4475	#define SRAM_SIZE 0x14000
4476	#define SRAM_END 0x40013FFF
4477
4478	#define FLASH_START 0x0
4479	#define FLASH_SIZE 0x200000
4480	#define FLASH_END 0x1FFFFF
4481
4482	/* Define instances of modules */
4483	#define PBRIDGE_A ((volatile struct PBRIDGE_A_tag ) 0xC3F00000)
4484	#define FMPLL ((volatile struct FMPLL_tag ) 0xC3F80000)
4485	#define EBI ((volatile struct EBI_tag ) 0xC3F84000)
4486	#define FLASH ((volatile struct FLASH_tag ) 0xC3F88000)
4487	#define SIU ((volatile struct SIU_tag ) 0xC3F90000)
4488
4489	#define EMIOS ((volatile struct EMIOS_tag ) 0xC3FA0000)
4490	#define ETPU ((volatile struct ETPU_tag ) 0xC3FC0000)
4491	#define ETPU_DATA_RAM (( uint32_t ) 0xC3FC8000)
4492	#define ETPU_DATA_RAM_EXT (( uint32_t ) 0xC3FCC000)
4493	#define ETPU_DATA_RAM_END 0xC3FC89FC
4494	#define CODE_RAM (( uint32_t ) 0xC3FD0000)
4495	#define ETPU_CODE_RAM (( uint32_t ) 0xC3FD0000)
4496
4497	#define PBRIDGE_B ((volatile struct PBRIDGE_B_tag ) 0xFFF00000)
4498	#define XBAR ((volatile struct XBAR_tag ) 0xFFF04000)
4499	#define ECSM ((volatile struct ECSM_tag ) 0xFFF40000)
4500	#define EDMA ((volatile struct EDMA_tag ) 0xFFF44000)
4501	#define INTC ((volatile struct INTC_tag ) 0xFFF48000)
4502
4503	#define EQADC ((volatile struct EQADC_tag ) 0xFFF80000)
4504
4505	#define DSPI_A ((volatile struct DSPI_tag ) 0xFFF90000)
4506	#define DSPI_B ((volatile struct DSPI_tag ) 0xFFF94000)
4507	#define DSPI_C ((volatile struct DSPI_tag ) 0xFFF98000)
4508	#define DSPI_D ((volatile struct DSPI_tag ) 0xFFF9C000)
4509
4510	#define ESCI_A ((volatile struct ESCI_tag ) 0xFFFB0000)
4511	#define ESCI_B ((volatile struct ESCI_tag ) 0xFFFB4000)
4512
4513	#define CAN_A ((volatile struct FLEXCAN2_tag ) 0xFFFC0000)
4514	#define CAN_B ((volatile struct FLEXCAN2_tag ) 0xFFFC4000)
4515	#define CAN_C ((volatile struct FLEXCAN2_tag ) 0xFFFC8000)
4516	#define CAN_D ((volatile struct FLEXCAN2_tag ) 0xFFFCC000)
4517	#define CAN_E ((volatile struct FLEXCAN2_tag ) 0xFFFD0000)
4518
4519	#define FEC ((volatile struct FEC_tag ) 0xFFF4C000)
4520
4521	#define FR ((volatile struct FR_tag ) 0xFFFE0000)
4522
4523	#ifdef __MWERKS__
4524	#pragma pop
4525	#endif
4526
4527	#ifdef __cplusplus
4528	}
4529	#endif
4530	#endif /* ifdef _MPC5567_H */
4531	/*********************************************************************
4532	*
4533	* Copyright:
4534	* Freescale Semiconductor, INC. All Rights Reserved.
4535	* You are hereby granted a copyright license to use, modify, and
4536	* distribute the SOFTWARE so long as this entire notice is
4537	* retained without alteration in any modified and/or redistributed
4538	* versions, and that such modified versions are clearly identified
4539	* as such. No licenses are granted by implication, estoppel or
4540	* otherwise under any patents or trademarks of Freescale
4541	* Semiconductor, Inc. This software is provided on an "AS IS"
4542	* basis and without warranty.
4543	*
4544	* To the maximum extent permitted by applicable law, Freescale
4545	* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
4546	* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
4547	* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
4548	* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
4549	* AND ANY ACCOMPANYING WRITTEN MATERIALS.
4550	*
4551	* To the maximum extent permitted by applicable law, IN NO EVENT
4552	* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
4553	* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
4554	* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
4555	* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
4556	*
4557	* Freescale Semiconductor assumes no responsibility for the
4558	* maintenance and support of this software
4559	*
4560	********************************************************************/

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