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fsl-mpc555x.h @ 97fa2f1b

4.115

Last change on this file since 97fa2f1b was 97fa2f1b, checked in by Sebastian Huber <sebastian.huber@…>, on 08/31/11 at 15:50:30

2011-08-31 Sebastian Huber <sebastian.huber@…>

mpc55xx/include/fsl-mpc551x.h, mpc55xx/include/fsl-mpc555x.h, mpc55xx/include/fsl-mpc556x.h, mpc55xx/include/fsl-mpc567x.h, mpc55xx/include/regs-edma.h, mpc55xx/include/regs-mmu.h: New files.
Makefile.am, M preinstall.am: Reflect changes above.
mpc55xx/dspi/dspi.c: Update due to API changes.
mpc55xx/include/edma.h, mpc55xx/edma/edma.c: Rework to support multiple eDMA modules. Removed complex error interrupt handling.
mpc55xx/include/esci.h, mpc55xx/esci/esci.c: Support interrupt mode and printk(). Use configure options.
mpc55xx/include/irq.h: More defines. API changes.
mpc55xx/include/mpc55xx.h: API changes.
mpc55xx/include/reg-defs.h: Added register defines.
mpc55xx/include/regs.h: Use new register header files.
mpc55xx/include/siu.h: Fixed includes.
mpc55xx/misc/fmpll.S, mpc55xx/misc/copy.S, mpc55xx/misc/flash.S: Changed sections. API changes. Support MPC5674F.

Property mode set to 100644

File size: 125.5 KB

Line
1	/*
2	* Modifications of the original file provided by Freescale are:
3	*
4	* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
5	*
6	* embedded brains GmbH
7	* Obere Lagerstr. 30
8	* 82178 Puchheim
9	* Germany
10	* <info@embedded-brains.de>
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	*
21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32	*/
33
34	/**************************************************************************/
35	/* FILE NAME: mpc5554.h COPYRIGHT (c) Freescale 2007 */
36	/* VERSION: 1.7 All Rights Reserved */
37	/* */
38	/* DESCRIPTION: */
39	/* This file contain all of the register and bit field definitions for */
40	/* MPC5554. */
41	/========================================================================/
42	/* UPDATE HISTORY */
43	/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
44	/* --- ----------- --------- --------------------- */
45	/* 0.01 J. Loeliger 03/Mar/03 Initial version of file for MPC5554. */
46	/* Based on SoC version 0.7. */
47	/* 0.02 J. Loeliger 05/Mar/03 All registers and bit fields now */
48	/* defined. */
49	/* 0.03 J. Loeliger 05/May/03 Updated to current spec., fixed several*/
50	/* bugs and naming/formating issues. */
51	/* 0.04 J. Loeliger 16/May/03 More fixes and naming/formating issues.*/
52	/* 0.05 J. Loeliger 19/Aug/03 Updated for latest documentation. */
53	/* 0.06 J. Loeliger 03/Sep/03 Changed to include motint.h */
54	/* Updated many register names. */
55	/* 0.07 J. Loeliger 04/Nov/03 Changed to include typedefs.h and more */
56	/* register name updates. */
57	/* 0.08 J. Loeliger 25/Feb/04 Added MetroWerks #pragmas. */
58	/* Updated for user manual 1.0 */
59	/* 0.09 J. Loeliger 27/Feb/04 Updated eDMA tcd section and some more */
60	/* bit field names to match user's man. */
61	/* 0.10 J. Loeliger 01/Apr/04 Fixed register spacing in ADC and eTPU */
62	/* 0.11 J. Loeliger 16/Jun/04 Many fixes and updated to user's */
63	/* manual, also some testing done. */
64	/* 0.12 J. Loeliger 25/Jun/04 Fixed problems in edma and eTPU. */
65	/* 0.13 J. Loeliger 16/Jul/04 Fixed mistake in FlexCAN TIMER size and*/
66	/* changed eTPU memory defs to start with*/
67	/* ETPU_ */
68	/* 0.14 J. Loeliger 17/Nov/04 Added ETPU_CODE_RAM definition. */
69	/* All code moved to CVS repository. */
70	/* Updated copyright to Freescale. */
71	/* Added new SCMOFFDATAR register to eTPU*/
72	/* Fixed REDCR_A&B bit fields in eTPU. */
73	/* Added new DBR bit in CTAR for DSPI. */
74	/* 0.15 J. Loeliger 29/Nov/04 Added support for new eTPU util funcs. */
75	/* Added bit fields for FlexCAN buffer ID*/
76	/* 0.16 J. Loeliger 01/Dec/04 Corrected comments in release 0.16. */
77	/* 0.17 J. Loeliger 02/Dec/04 Moved eTPU variable definitions to a */
78	/* seperate new file. */
79	/* Removed SIU variable the GPIO */
80	/* routines do not need it. */
81	/* 1.0 G.Emerson 22/Feb/05 No real changes to this file. */
82	/* Joint generation with mpc5553.h */
83	/* 1.1 G. Emerson 6/Jun/05 Changes to SIU to allow for upward */
84	/* expansion of PCR/GPDI/GPDO */
85	/* Added #defines for memory sizes etc */
86	/* 1.2 G. Emerson 21/Sep/05 PBRIDGES fixes */
87	/* 1.3 G. Emerson 03/Jan/06 Pbridge MPCR/PACR/OPACR now generic */
88	/* XBAR MPR now generic */
89	/* ECSM has FSBMCR on all integrations */
90	/* 1.4 G. Emerson 24/Jan/06 Make Pbridges, XBAR, Flash BIU */
91	/* integration specific */
92	/* 1.5 S. Mathieson 28/Jul/06 Split out unused bit to support build */
93	/* process. No real change. */
94	/* 1.6 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */
95	/* to DPB to align with documentation. */
96	/* 1.7 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */
97	/* alternate configuration. INTC, */
98	/* correction to the number of PSR */
99	/* registers. */
100	/**************************************************************************/
101	/>>>>NOTE! this file is auto-generated please do not edit it!<<<</
102
103	#ifndef _MPC5554_H_
104	#define _MPC5554_H_
105
106	#include <stdint.h>
107
108	#include <mpc55xx/regs-edma.h>
109
110	#ifdef __cplusplus
111	extern "C" {
112	#endif
113
114	#ifdef __MWERKS__
115	#pragma push
116	#pragma ANSI_strict off
117	#endif
118
119	/****************************************************************************/
120	/* MODULE : PBRIDGE_A Peripheral Bridge */
121	/****************************************************************************/
122	struct PBRIDGE_A_tag {
123	union {
124	uint32_t R;
125	struct {
126	uint32_t MBW0:1;
127	uint32_t MTR0:1;
128	uint32_t MTW0:1;
129	uint32_t MPL0:1;
130	uint32_t MBW1:1;
131	uint32_t MTR1:1;
132	uint32_t MTW1:1;
133	uint32_t MPL1:1;
134	uint32_t MBW2:1;
135	uint32_t MTR2:1;
136	uint32_t MTW2:1;
137	uint32_t MPL2:1;
138	uint32_t MBW3:1;
139	uint32_t MTR3:1;
140	uint32_t MTW3:1;
141	uint32_t MPL3:1;
142
143	uint32_t:4;
144
145	uint32_t:4;
146
147	uint32_t:4;
148
149	uint32_t:4;
150	} B;
151	} MPCR; /* Master Privilege Control Register */
152
153	uint32_t pbridge_a_reserved2[7];
154
155	union {
156	uint32_t R;
157	struct {
158	uint32_t BW0:1;
159	uint32_t SP0:1;
160	uint32_t WP0:1;
161	uint32_t TP0:1;
162	uint32_t:28;
163	} B;
164	} PACR0;
165
166	uint32_t pbridge_a_reserved3[7];
167
168	union {
169	uint32_t R;
170	struct {
171	uint32_t BW0:1;
172	uint32_t SP0:1;
173	uint32_t WP0:1;
174	uint32_t TP0:1;
175	uint32_t BW1:1;
176	uint32_t SP1:1;
177	uint32_t WP1:1;
178	uint32_t TP1:1;
179	uint32_t BW2:1;
180	uint32_t SP2:1;
181	uint32_t WP2:1;
182	uint32_t TP2:1;
183	uint32_t:4;
184	uint32_t BW4:1;
185	uint32_t SP4:1;
186	uint32_t WP4:1;
187	uint32_t TP4:1;
188	uint32_t:12;
189	} B;
190	} OPACR0;
191
192	union {
193	uint32_t R;
194	struct {
195
196	uint32_t BW0:1; /* EMIOS */
197	uint32_t SP0:1;
198	uint32_t WP0:1;
199	uint32_t TP0:1;
200
201	uint32_t:28;
202	} B;
203	} OPACR1;
204
205	union {
206	uint32_t R;
207	struct {
208	uint32_t BW0:1;
209	uint32_t SP0:1;
210	uint32_t WP0:1;
211	uint32_t TP0:1;
212	uint32_t:4;
213	uint32_t BW2:1;
214	uint32_t SP2:1;
215	uint32_t WP2:1;
216	uint32_t TP2:1;
217	uint32_t BW3:1;
218	uint32_t SP3:1;
219	uint32_t WP3:1;
220	uint32_t TP3:1;
221	uint32_t BW4:1;
222	uint32_t SP4:1;
223	uint32_t WP4:1;
224	uint32_t TP4:1;
225	uint32_t:12;
226	} B;
227	} OPACR2;
228
229	};
230
231	/****************************************************************************/
232	/* MODULE : PBRIDGE_B Peripheral Bridge */
233	/****************************************************************************/
234	struct PBRIDGE_B_tag {
235	union {
236	uint32_t R;
237	struct {
238	uint32_t MBW0:1;
239	uint32_t MTR0:1;
240	uint32_t MTW0:1;
241	uint32_t MPL0:1;
242	uint32_t MBW1:1;
243	uint32_t MTR1:1;
244	uint32_t MTW1:1;
245	uint32_t MPL1:1;
246	uint32_t MBW2:1;
247	uint32_t MTR2:1;
248	uint32_t MTW2:1;
249	uint32_t MPL2:1;
250	uint32_t MBW3:1;
251	uint32_t MTR3:1;
252	uint32_t MTW3:1;
253	uint32_t MPL3:1;
254
255	uint32_t:4;
256
257	uint32_t:4;
258
259	uint32_t:4;
260
261	uint32_t:4;
262	} B;
263	} MPCR; /* Master Privilege Control Register */
264
265	uint32_t pbridge_b_reserved2[7];
266
267	union {
268	uint32_t R;
269	struct {
270	uint32_t BW0:1;
271	uint32_t SP0:1;
272	uint32_t WP0:1;
273	uint32_t TP0:1;
274	uint32_t BW1:1;
275	uint32_t SP1:1;
276	uint32_t WP1:1;
277	uint32_t TP1:1;
278	uint32_t:24;
279	} B;
280	} PACR0;
281
282	uint32_t pbridge_b_reserved3;
283
284	union {
285	uint32_t R;
286	struct {
287	uint32_t BW0:1;
288	uint32_t SP0:1;
289	uint32_t WP0:1;
290	uint32_t TP0:1;
291	uint32_t BW1:1;
292	uint32_t SP1:1;
293	uint32_t WP1:1;
294	uint32_t TP1:1;
295	uint32_t BW2:1;
296	uint32_t SP2:1;
297	uint32_t WP2:1;
298	uint32_t TP2:1;
299
300	uint32_t:4;
301
302	uint32_t:16;
303
304	} B;
305	} PACR2;
306
307	uint32_t pbridge_b_reserved4[5];
308
309	union {
310	uint32_t R;
311	struct {
312	uint32_t BW0:1;
313	uint32_t SP0:1;
314	uint32_t WP0:1;
315	uint32_t TP0:1;
316	uint32_t:12;
317
318	uint32_t BW4:1; /* DSPI_A */
319	uint32_t SP4:1;
320	uint32_t WP4:1;
321	uint32_t TP4:1;
322
323	uint32_t BW5:1; /* DSPI_B */
324	uint32_t SP5:1;
325	uint32_t WP5:1;
326	uint32_t TP5:1;
327
328	uint32_t BW6:1;
329	uint32_t SP6:1;
330	uint32_t WP6:1;
331	uint32_t TP6:1;
332	uint32_t BW7:1;
333	uint32_t SP7:1;
334	uint32_t WP7:1;
335	uint32_t TP7:1;
336	} B;
337	} OPACR0;
338
339	union {
340	uint32_t R;
341	struct {
342	uint32_t:16;
343	uint32_t BW4:1;
344	uint32_t SP4:1;
345	uint32_t WP4:1;
346	uint32_t TP4:1;
347
348	uint32_t BW5:1; /* ESCI_B */
349	uint32_t SP5:1;
350	uint32_t WP5:1;
351	uint32_t TP5:1;
352
353	uint32_t:8;
354	} B;
355	} OPACR1;
356
357	union {
358	uint32_t R;
359	struct {
360	uint32_t BW0:1;
361	uint32_t SP0:1;
362	uint32_t WP0:1;
363	uint32_t TP0:1;
364
365	uint32_t BW1:1; /* CAN_B */
366	uint32_t SP1:1;
367	uint32_t WP1:1;
368	uint32_t TP1:1;
369
370	uint32_t BW2:1;
371	uint32_t SP2:1;
372	uint32_t WP2:1;
373	uint32_t TP2:1;
374
375	uint32_t:4;
376
377	uint32_t:4;
378
379	uint32_t:12;
380	} B;
381	} OPACR2;
382
383	union {
384	uint32_t R;
385	struct {
386
387	uint32_t:4;
388
389	uint32_t:24;
390	uint32_t BW7:1;
391	uint32_t SP7:1;
392	uint32_t WP7:1;
393	uint32_t TP7:1;
394	} B;
395	} OPACR3;
396
397	};
398	/****************************************************************************/
399	/* MODULE : FMPLL */
400	/****************************************************************************/
401	struct FMPLL_tag {
402	union FMPLL_SYNCR_tag {
403	uint32_t R;
404	struct {
405	uint32_t:1;
406	uint32_t PREDIV:3;
407	uint32_t MFD:5;
408	uint32_t:1;
409	uint32_t RFD:3;
410	uint32_t LOCEN:1;
411	uint32_t LOLRE:1;
412	uint32_t LOCRE:1;
413	uint32_t DISCLK:1;
414	uint32_t LOLIRQ:1;
415	uint32_t LOCIRQ:1;
416	uint32_t RATE:1;
417	uint32_t DEPTH:2;
418	uint32_t EXP:10;
419	} B;
420	} SYNCR;
421
422	union FMPLL_SYNSR_tag {
423	uint32_t R;
424	struct {
425	uint32_t:22;
426	uint32_t LOLF:1;
427	uint32_t LOC:1;
428	uint32_t MODE:1;
429	uint32_t PLLSEL:1;
430	uint32_t PLLREF:1;
431	uint32_t LOCKS:1;
432	uint32_t LOCK:1;
433	uint32_t LOCF:1;
434	uint32_t CALDONE:1;
435	uint32_t CALPASS:1;
436	} B;
437	} SYNSR;
438
439	};
440	/****************************************************************************/
441	/* MODULE : External Bus Interface (EBI) */
442	/****************************************************************************/
443	struct EBI_CS_tag {
444	union { /* Base Register Bank */
445	uint32_t R;
446	struct {
447	uint32_t BA:17;
448	uint32_t:3;
449	uint32_t PS:1;
450	uint32_t:4;
451	uint32_t BL:1;
452	uint32_t WEBS:1;
453	uint32_t TBDIP:1;
454	uint32_t:2;
455	uint32_t BI:1;
456	uint32_t V:1;
457	} B;
458	} BR;
459
460	union { /* Option Register Bank */
461	uint32_t R;
462	struct {
463	uint32_t AM:17;
464	uint32_t:7;
465	uint32_t SCY:4;
466	uint32_t:1;
467	uint32_t BSCY:2;
468	uint32_t:1;
469	} B;
470	} OR;
471	};
472
473	struct EBI_CAL_CS_tag {
474	uint32_t ebi_cal_cs_reserved [2];
475	};
476
477	struct EBI_tag {
478	union { /* Module Configuration Register */
479	uint32_t R;
480	struct {
481	uint32_t:5;
482	uint32_t SIZEEN:1;
483	uint32_t SIZE:2;
484	uint32_t:8;
485	uint32_t ACGE:1;
486	uint32_t EXTM:1;
487	uint32_t EARB:1;
488	uint32_t EARP:2;
489	uint32_t:4;
490	uint32_t MDIS:1;
491	uint32_t:5;
492	uint32_t DBM:1;
493	} B;
494	} MCR;
495
496	uint32_t EBI_reserved1;
497
498	union { /* Transfer Error Status Register */
499	uint32_t R;
500	struct {
501	uint32_t:30;
502	uint32_t TEAF:1;
503	uint32_t BMTF:1;
504	} B;
505	} TESR;
506
507	union { /* Bus Monitor Control Register */
508	uint32_t R;
509	struct {
510	uint32_t:16;
511	uint32_t BMT:8;
512	uint32_t BME:1;
513	uint32_t:7;
514	} B;
515	} BMCR;
516
517	struct EBI_CS_tag CS[4];
518
519	uint32_t EBI_reserved2[4];
520
521	struct EBI_CAL_CS_tag CAL_CS[4];
522	};
523	/****************************************************************************/
524	/* MODULE : FLASH */
525	/****************************************************************************/
526	struct FLASH_tag {
527	union { /* Module Configuration Register */
528	uint32_t R;
529	struct {
530	uint32_t:4;
531	uint32_t SIZE:4;
532	uint32_t:1;
533	uint32_t LAS:3;
534	uint32_t:3;
535	uint32_t MAS:1;
536	uint32_t EER:1;
537	uint32_t RWE:1;
538	uint32_t BBEPE:1;
539	uint32_t EPE:1;
540	uint32_t PEAS:1;
541	uint32_t DONE:1;
542	uint32_t PEG:1;
543
544	uint32_t:2;
545
546	uint32_t STOP:1;
547	uint32_t:1;
548	uint32_t PGM:1;
549	uint32_t PSUS:1;
550	uint32_t ERS:1;
551	uint32_t ESUS:1;
552	uint32_t EHV:1;
553	} B;
554	} MCR;
555
556	union LMLR_tag { /* LML Register */
557	uint32_t R;
558	struct {
559	uint32_t LME:1;
560	uint32_t:10;
561	uint32_t SLOCK:1;
562	uint32_t MLOCK:4;
563	uint32_t LLOCK:16;
564	} B;
565	} LMLR;
566
567	union HLR_tag { /* HL Register */
568	uint32_t R;
569	struct {
570	uint32_t HBE:1;
571	uint32_t:3;
572	uint32_t HBLOCK:28;
573	} B;
574	} HLR;
575
576	union SLMLR_tag { /* SLML Register */
577	uint32_t R;
578	struct {
579	uint32_t SLE:1;
580	uint32_t:10;
581	uint32_t SSLOCK:1;
582	uint32_t SMLOCK:4;
583	uint32_t SLLOCK:16;
584	} B;
585	} SLMLR;
586
587	union { /* LMS Register */
588	uint32_t R;
589	struct {
590	uint32_t:12;
591	uint32_t MSEL:4;
592	uint32_t LSEL:16;
593	} B;
594	} LMSR;
595
596	union {
597	uint32_t R;
598	struct {
599	uint32_t:4;
600	uint32_t HBSEL:28;
601	} B;
602	} HSR;
603
604	union {
605	uint32_t R;
606	struct {
607	uint32_t:10;
608	uint32_t ADDR:19;
609	uint32_t:3;
610	} B;
611	} AR;
612
613	union {
614	uint32_t R;
615	struct {
616
617	uint32_t:11;
618
619	uint32_t:1;
620
621	uint32_t M3PFE:1;
622	uint32_t M2PFE:1;
623	uint32_t M1PFE:1;
624	uint32_t M0PFE:1;
625	uint32_t APC:3;
626	uint32_t WWSC:2;
627	uint32_t RWSC:3;
628
629	uint32_t DPFEN:2;
630	uint32_t IPFEN:2;
631
632	uint32_t PFLIM:3;
633	uint32_t BFEN:1;
634	} B;
635	} BIUCR;
636
637	union {
638	uint32_t R;
639	struct {
640
641	uint32_t:22;
642
643	uint32_t:2;
644
645	uint32_t M3AP:2;
646	uint32_t M2AP:2;
647	uint32_t M1AP:2;
648	uint32_t M0AP:2;
649	} B;
650	} BIUAPR;
651	};
652	/****************************************************************************/
653	/* MODULE : SIU */
654	/****************************************************************************/
655	struct SIU_tag {
656	int32_t SIU_reserved0;
657
658	union { /* MCU ID Register */
659	uint32_t R;
660	struct {
661	uint32_t PARTNUM:16;
662	uint32_t MASKNUM:16;
663	} B;
664	} MIDR;
665	int32_t SIU_reserved00;
666
667	union { /* Reset Status Register */
668	uint32_t R;
669	struct {
670	uint32_t PORS:1;
671	uint32_t ERS:1;
672	uint32_t LLRS:1;
673	uint32_t LCRS:1;
674	uint32_t WDRS:1;
675	uint32_t CRS:1;
676	uint32_t:8;
677	uint32_t SSRS:1;
678	uint32_t SERF:1;
679	uint32_t WKPCFG:1;
680	uint32_t:12;
681	uint32_t BOOTCFG:2;
682	uint32_t RGF:1;
683	} B;
684	} RSR;
685
686	union { /* System Reset Control Register */
687	uint32_t R;
688	struct {
689	uint32_t SSR:1;
690	uint32_t SER:1;
691	uint32_t:14;
692	uint32_t CRE:1;
693	uint32_t:15;
694	} B;
695	} SRCR;
696
697	union SIU_EISR_tag { /* External Interrupt Status Register */
698	uint32_t R;
699	struct {
700	uint32_t:16;
701	uint32_t EIF15:1;
702	uint32_t EIF14:1;
703	uint32_t EIF13:1;
704	uint32_t EIF12:1;
705	uint32_t EIF11:1;
706	uint32_t EIF10:1;
707	uint32_t EIF9:1;
708	uint32_t EIF8:1;
709	uint32_t EIF7:1;
710	uint32_t EIF6:1;
711	uint32_t EIF5:1;
712	uint32_t EIF4:1;
713	uint32_t EIF3:1;
714	uint32_t EIF2:1;
715	uint32_t EIF1:1;
716	uint32_t EIF0:1;
717	} B;
718	} EISR;
719
720	union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
721	uint32_t R;
722	struct {
723	uint32_t:16;
724	uint32_t EIRE15:1;
725	uint32_t EIRE14:1;
726	uint32_t EIRE13:1;
727	uint32_t EIRE12:1;
728	uint32_t EIRE11:1;
729	uint32_t EIRE10:1;
730	uint32_t EIRE9:1;
731	uint32_t EIRE8:1;
732	uint32_t EIRE7:1;
733	uint32_t EIRE6:1;
734	uint32_t EIRE5:1;
735	uint32_t EIRE4:1;
736	uint32_t EIRE3:1;
737	uint32_t EIRE2:1;
738	uint32_t EIRE1:1;
739	uint32_t EIRE0:1;
740	} B;
741	} DIRER;
742
743	union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */
744	uint32_t R;
745	struct {
746	uint32_t:28;
747	uint32_t DIRS3:1;
748	uint32_t DIRS2:1;
749	uint32_t DIRS1:1;
750	uint32_t DIRS0:1;
751	} B;
752	} DIRSR;
753
754	union { /* Overrun Status Register */
755	uint32_t R;
756	struct {
757	uint32_t:16;
758	uint32_t OVF15:1;
759	uint32_t OVF14:1;
760	uint32_t OVF13:1;
761	uint32_t OVF12:1;
762	uint32_t OVF11:1;
763	uint32_t OVF10:1;
764	uint32_t OVF9:1;
765	uint32_t OVF8:1;
766	uint32_t OVF7:1;
767	uint32_t OVF6:1;
768	uint32_t OVF5:1;
769	uint32_t OVF4:1;
770	uint32_t OVF3:1;
771	uint32_t OVF2:1;
772	uint32_t OVF1:1;
773	uint32_t OVF0:1;
774	} B;
775	} OSR;
776
777	union SIU_ORER_tag { /* Overrun Request Enable Register */
778	uint32_t R;
779	struct {
780	uint32_t:16;
781	uint32_t ORE15:1;
782	uint32_t ORE14:1;
783	uint32_t ORE13:1;
784	uint32_t ORE12:1;
785	uint32_t ORE11:1;
786	uint32_t ORE10:1;
787	uint32_t ORE9:1;
788	uint32_t ORE8:1;
789	uint32_t ORE7:1;
790	uint32_t ORE6:1;
791	uint32_t ORE5:1;
792	uint32_t ORE4:1;
793	uint32_t ORE3:1;
794	uint32_t ORE2:1;
795	uint32_t ORE1:1;
796	uint32_t ORE0:1;
797	} B;
798	} ORER;
799
800	union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
801	uint32_t R;
802	struct {
803	uint32_t:16;
804	uint32_t IREE15:1;
805	uint32_t IREE14:1;
806	uint32_t IREE13:1;
807	uint32_t IREE12:1;
808	uint32_t IREE11:1;
809	uint32_t IREE10:1;
810	uint32_t IREE9:1;
811	uint32_t IREE8:1;
812	uint32_t IREE7:1;
813	uint32_t IREE6:1;
814	uint32_t IREE5:1;
815	uint32_t IREE4:1;
816	uint32_t IREE3:1;
817	uint32_t IREE2:1;
818	uint32_t IREE1:1;
819	uint32_t IREE0:1;
820	} B;
821	} IREER;
822
823	union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
824	uint32_t R;
825	struct {
826	uint32_t:16;
827	uint32_t IFEE15:1;
828	uint32_t IFEE14:1;
829	uint32_t IFEE13:1;
830	uint32_t IFEE12:1;
831	uint32_t IFEE11:1;
832	uint32_t IFEE10:1;
833	uint32_t IFEE9:1;
834	uint32_t IFEE8:1;
835	uint32_t IFEE7:1;
836	uint32_t IFEE6:1;
837	uint32_t IFEE5:1;
838	uint32_t IFEE4:1;
839	uint32_t IFEE3:1;
840	uint32_t IFEE2:1;
841	uint32_t IFEE1:1;
842	uint32_t IFEE0:1;
843	} B;
844	} IFEER;
845
846	union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
847	uint32_t R;
848	struct {
849	uint32_t:28;
850	uint32_t DFL:4;
851	} B;
852	} IDFR;
853
854	int32_t SIU_reserved1[3];
855
856	union SIU_PCR_tag { /* Pad Configuration Registers */
857	uint16_t R;
858	struct {
859	uint16_t:3;
860	uint16_t PA:3;
861	uint16_t OBE:1;
862	uint16_t IBE:1;
863	uint16_t DSC:2;
864	uint16_t ODE:1;
865	uint16_t HYS:1;
866	uint16_t SRC:2;
867	uint16_t WPE:1;
868	uint16_t WPS:1;
869	} B;
870	} PCR[512];
871
872	int16_t SIU_reserved_0[224];
873
874	union { /* GPIO Pin Data Output Registers */
875	uint8_t R;
876	struct {
877	uint8_t:7;
878	uint8_t PDO:1;
879	} B;
880	} GPDO[256];
881
882	int32_t SIU_reserved_3[64];
883
884	union { /* GPIO Pin Data Input Registers */
885	uint8_t R;
886	struct {
887	uint8_t:7;
888	uint8_t PDI:1;
889	} B;
890	} GPDI[256];
891
892	union { /* IMUX Register */
893	uint32_t R;
894	struct {
895	uint32_t TSEL5:2;
896	uint32_t TSEL4:2;
897	uint32_t TSEL3:2;
898	uint32_t TSEL2:2;
899	uint32_t TSEL1:2;
900	uint32_t TSEL0:2;
901	uint32_t:20;
902	} B;
903	} ETISR;
904
905	union { /* IMUX Register */
906	uint32_t R;
907	struct {
908	uint32_t ESEL15:2;
909	uint32_t ESEL14:2;
910	uint32_t ESEL13:2;
911	uint32_t ESEL12:2;
912	uint32_t ESEL11:2;
913	uint32_t ESEL10:2;
914	uint32_t ESEL9:2;
915	uint32_t ESEL8:2;
916	uint32_t ESEL7:2;
917	uint32_t ESEL6:2;
918	uint32_t ESEL5:2;
919	uint32_t ESEL4:2;
920	uint32_t ESEL3:2;
921	uint32_t ESEL2:2;
922	uint32_t ESEL1:2;
923	uint32_t ESEL0:2;
924	} B;
925	} EIISR;
926
927	union { /* IMUX Register */
928	uint32_t R;
929	struct {
930	uint32_t SINSELA:2;
931	uint32_t SSSELA:2;
932	uint32_t SCKSELA:2;
933	uint32_t TRIGSELA:2;
934	uint32_t SINSELB:2;
935	uint32_t SSSELB:2;
936	uint32_t SCKSELB:2;
937	uint32_t TRIGSELB:2;
938	uint32_t SINSELC:2;
939	uint32_t SSSELC:2;
940	uint32_t SCKSELC:2;
941	uint32_t TRIGSELC:2;
942	uint32_t SINSELD:2;
943	uint32_t SSSELD:2;
944	uint32_t SCKSELD:2;
945	uint32_t TRIGSELD:2;
946	} B;
947	} DISR;
948
949	int32_t SIU_reserved2[29];
950
951	union { /* Chip Configuration Register Register */
952	uint32_t R;
953	struct {
954	uint32_t:14;
955	uint32_t MATCH:1;
956	uint32_t DISNEX:1;
957	uint32_t:16;
958	} B;
959	} CCR;
960
961	union { /* External Clock Configuration Register Register */
962	uint32_t R;
963	struct {
964	uint32_t:18;
965	uint32_t ENGDIV:6;
966	uint32_t:4;
967	uint32_t EBTS:1;
968	uint32_t:1;
969	uint32_t EBDF:2;
970	} B;
971	} ECCR;
972
973	union {
974	uint32_t R;
975	} CARH;
976
977	union {
978	uint32_t R;
979	} CARL;
980
981	union {
982	uint32_t R;
983	} CBRH;
984
985	union {
986	uint32_t R;
987	} CBRL;
988
989	};
990	/****************************************************************************/
991	/* MODULE : EMIOS */
992	/****************************************************************************/
993	struct EMIOS_tag {
994	union EMIOS_MCR_tag {
995	uint32_t R;
996	struct {
997	uint32_t:1;
998	uint32_t MDIS:1;
999	uint32_t FRZ:1;
1000	uint32_t GTBE:1;
1001	uint32_t ETB:1;
1002	uint32_t GPREN:1;
1003	uint32_t:6;
1004	uint32_t SRV:4;
1005	uint32_t GPRE:8;
1006	uint32_t:8;
1007	} B;
1008	} MCR; /* Module Configuration Register */
1009
1010	union {
1011	uint32_t R;
1012	struct {
1013	uint32_t:8;
1014	uint32_t F23:1;
1015	uint32_t F22:1;
1016	uint32_t F21:1;
1017	uint32_t F20:1;
1018	uint32_t F19:1;
1019	uint32_t F18:1;
1020	uint32_t F17:1;
1021	uint32_t F16:1;
1022	uint32_t F15:1;
1023	uint32_t F14:1;
1024	uint32_t F13:1;
1025	uint32_t F12:1;
1026	uint32_t F11:1;
1027	uint32_t F10:1;
1028	uint32_t F9:1;
1029	uint32_t F8:1;
1030	uint32_t F7:1;
1031	uint32_t F6:1;
1032	uint32_t F5:1;
1033	uint32_t F4:1;
1034	uint32_t F3:1;
1035	uint32_t F2:1;
1036	uint32_t F1:1;
1037	uint32_t F0:1;
1038	} B;
1039	} GFR; /* Global FLAG Register */
1040
1041	union {
1042	uint32_t R;
1043	struct {
1044	uint32_t:8;
1045	uint32_t OU23:1;
1046	uint32_t OU22:1;
1047	uint32_t OU21:1;
1048	uint32_t OU20:1;
1049	uint32_t OU19:1;
1050	uint32_t OU18:1;
1051	uint32_t OU17:1;
1052	uint32_t OU16:1;
1053	uint32_t OU15:1;
1054	uint32_t OU14:1;
1055	uint32_t OU13:1;
1056	uint32_t OU12:1;
1057	uint32_t OU11:1;
1058	uint32_t OU10:1;
1059	uint32_t OU9:1;
1060	uint32_t OU8:1;
1061	uint32_t OU7:1;
1062	uint32_t OU6:1;
1063	uint32_t OU5:1;
1064	uint32_t OU4:1;
1065	uint32_t OU3:1;
1066	uint32_t OU2:1;
1067	uint32_t OU1:1;
1068	uint32_t OU0:1;
1069	} B;
1070	} OUDR; /* Output Update Disable Register */
1071
1072	uint32_t emios_reserved[5];
1073
1074	struct EMIOS_CH_tag {
1075	union {
1076	uint32_t R; /* Channel A Data Register */
1077	} CADR;
1078
1079	union {
1080	uint32_t R; /* Channel B Data Register */
1081	} CBDR;
1082
1083	union {
1084	uint32_t R; /* Channel Counter Register */
1085	} CCNTR;
1086
1087	union EMIOS_CCR_tag {
1088	uint32_t R;
1089	struct {
1090	uint32_t FREN:1;
1091	uint32_t ODIS:1;
1092	uint32_t ODISSL:2;
1093	uint32_t UCPRE:2;
1094	uint32_t UCPREN:1;
1095	uint32_t DMA:1;
1096	uint32_t:1;
1097	uint32_t IF:4;
1098	uint32_t FCK:1;
1099	uint32_t FEN:1;
1100	uint32_t:3;
1101	uint32_t FORCMA:1;
1102	uint32_t FORCMB:1;
1103	uint32_t:1;
1104	uint32_t BSL:2;
1105	uint32_t EDSEL:1;
1106	uint32_t EDPOL:1;
1107	uint32_t MODE:7;
1108	} B;
1109	} CCR; /* Channel Control Register */
1110
1111	union EMIOS_CSR_tag {
1112	uint32_t R;
1113	struct {
1114	uint32_t OVR:1;
1115	uint32_t:15;
1116	uint32_t OVFL:1;
1117	uint32_t:12;
1118	uint32_t UCIN:1;
1119	uint32_t UCOUT:1;
1120	uint32_t FLAG:1;
1121	} B;
1122	} CSR; /* Channel Status Register */
1123	uint32_t emios_channel_reserved[3];
1124
1125	} CH[24];
1126
1127	};
1128	/****************************************************************************/
1129	/* MODULE :ETPU */
1130	/****************************************************************************/
1131
1132	/*************************Configuration Registers************************/
1133
1134	struct ETPU_tag {
1135	union { /* MODULE CONFIGURATION REGISTER */
1136	uint32_t R;
1137	struct {
1138	uint32_t GEC:1; /* Global Exception Clear */
1139	uint32_t:3;
1140	uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
1141
1142	uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */
1143
1144	uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
1145
1146	uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */
1147
1148	uint32_t:3;
1149	uint32_t SCMSIZE:5; /* Shared Code Memory size */
1150	uint32_t:5;
1151	uint32_t SCMMISF:1; /* SCM MISC Flag */
1152	uint32_t SCMMISEN:1; /* SCM MISC Enable */
1153	uint32_t:2;
1154	uint32_t VIS:1; /* SCM Visability */
1155	uint32_t:5;
1156	uint32_t GTBE:1; /* Global Time Base Enable */
1157	} B;
1158	} MCR;
1159
1160	union { /* COHERENT DUAL-PARAMETER CONTROL */
1161	uint32_t R;
1162	struct {
1163	uint32_t STS:1; /* Start Status bit */
1164	uint32_t CTBASE:5; /* Channel Transfer Base */
1165	uint32_t PBASE:10; /* Parameter Buffer Base Address */
1166	uint32_t PWIDTH:1; /* Parameter Width */
1167	uint32_t PARAM0:7; /* Channel Parameter 0 */
1168	uint32_t WR:1;
1169	uint32_t PARAM1:7; /* Channel Parameter 1 */
1170	} B;
1171	} CDCR;
1172
1173	uint32_t etpu_reserved1;
1174
1175	union { /* MISC Compare Register */
1176	uint32_t R;
1177	} MISCCMPR;
1178
1179	union { /* SCM off-range Date Register */
1180	uint32_t R;
1181	} SCMOFFDATAR;
1182
1183	union { /* ETPU_A Configuration Register */
1184	uint32_t R;
1185	struct {
1186	uint32_t FEND:1; /* Force END */
1187	uint32_t MDIS:1; /* Low power Stop */
1188	uint32_t:1;
1189	uint32_t STF:1; /* Stop Flag */
1190	uint32_t:4;
1191	uint32_t HLTF:1; /* Halt Mode Flag */
1192	uint32_t:4;
1193	uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1194	uint32_t CDFC:2;
1195	uint32_t:9;
1196	uint32_t ETB:5; /* Entry Table Base */
1197	} B;
1198	} ECR_A;
1199
1200	union { /* ETPU_B Configuration Register */
1201	uint32_t R;
1202	struct {
1203	uint32_t FEND:1; /* Force END */
1204	uint32_t MDIS:1; /* Low power Stop */
1205	uint32_t:1;
1206	uint32_t STF:1; /* Stop Flag */
1207	uint32_t:4;
1208	uint32_t HLTF:1; /* Halt Mode Flag */
1209	uint32_t:4;
1210	uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
1211	uint32_t CDFC:2;
1212	uint32_t:9;
1213	uint32_t ETB:5; /* Entry Table Base */
1214	} B;
1215	} ECR_B;
1216
1217	uint32_t etpu_reserved4;
1218
1219	union { /* ETPU_A Timebase Configuration Register */
1220	uint32_t R;
1221	struct {
1222	uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1223	uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1224	uint32_t:1;
1225	uint32_t AM:1; /* Angle Mode */
1226	uint32_t:3;
1227	uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1228	uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1229	uint32_t:6;
1230	uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1231	} B;
1232	} TBCR_A;
1233
1234	union { /* ETPU_A TCR1 Visibility Register */
1235	uint32_t R;
1236	} TB1R_A;
1237
1238	union { /* ETPU_A TCR2 Visibility Register */
1239	uint32_t R;
1240	} TB2R_A;
1241
1242	union { /* ETPU_A STAC Configuration Register */
1243	uint32_t R;
1244	struct {
1245	uint32_t REN1:1; /* Resource Enable TCR1 */
1246	uint32_t RSC1:1; /* Resource Control TCR1 */
1247	uint32_t:2;
1248	uint32_t SERVER_ID1:4;
1249	uint32_t:4;
1250	uint32_t SRV1:4; /* Resource Server Slot */
1251	uint32_t REN2:1; /* Resource Enable TCR2 */
1252	uint32_t RSC2:1; /* Resource Control TCR2 */
1253	uint32_t:2;
1254	uint32_t SERVER_ID2:4;
1255	uint32_t:4;
1256	uint32_t SRV2:4; /* Resource Server Slot */
1257	} B;
1258	} REDCR_A;
1259
1260	uint32_t etpu_reserved5[4];
1261
1262	union { /* ETPU_B Timebase Configuration Register */
1263	uint32_t R;
1264	struct {
1265	uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
1266	uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
1267	uint32_t:1;
1268	uint32_t AM:1; /* Angle Mode */
1269	uint32_t:3;
1270	uint32_t TCR2P:6; /* TCR2 Prescaler Control */
1271	uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
1272	uint32_t:6;
1273	uint32_t TCR1P:8; /* TCR1 Prescaler Control */
1274	} B;
1275	} TBCR_B;
1276
1277	union { /* ETPU_B TCR1 Visibility Register */
1278	uint32_t R;
1279	} TB1R_B;
1280
1281	union { /* ETPU_B TCR2 Visibility Register */
1282	uint32_t R;
1283	} TB2R_B;
1284
1285	union { /* ETPU_B STAC Configuration Register */
1286	uint32_t R;
1287	struct {
1288	uint32_t REN1:1; /* Resource Enable TCR1 */
1289	uint32_t RSC1:1; /* Resource Control TCR1 */
1290	uint32_t:2;
1291	uint32_t SERVER_ID1:4;
1292	uint32_t:4;
1293	uint32_t SRV1:4; /* Resource Server Slot */
1294	uint32_t REN2:1; /* Resource Enable TCR2 */
1295	uint32_t RSC2:1; /* Resource Control TCR2 */
1296	uint32_t:2;
1297	uint32_t SERVER_ID2:4;
1298	uint32_t:4;
1299	uint32_t SRV2:4; /* Resource Server Slot */
1300	} B;
1301	} REDCR_B;
1302
1303	uint32_t etpu_reserved7[108];
1304
1305	/***************************Status and Control Registers************************/
1306
1307	union { /* ETPU_A Channel Interrut Status */
1308	uint32_t R;
1309	struct {
1310	uint32_t CIS31:1; /* Channel 31 Interrut Status */
1311	uint32_t CIS30:1; /* Channel 30 Interrut Status */
1312	uint32_t CIS29:1; /* Channel 29 Interrut Status */
1313	uint32_t CIS28:1; /* Channel 28 Interrut Status */
1314	uint32_t CIS27:1; /* Channel 27 Interrut Status */
1315	uint32_t CIS26:1; /* Channel 26 Interrut Status */
1316	uint32_t CIS25:1; /* Channel 25 Interrut Status */
1317	uint32_t CIS24:1; /* Channel 24 Interrut Status */
1318	uint32_t CIS23:1; /* Channel 23 Interrut Status */
1319	uint32_t CIS22:1; /* Channel 22 Interrut Status */
1320	uint32_t CIS21:1; /* Channel 21 Interrut Status */
1321	uint32_t CIS20:1; /* Channel 20 Interrut Status */
1322	uint32_t CIS19:1; /* Channel 19 Interrut Status */
1323	uint32_t CIS18:1; /* Channel 18 Interrut Status */
1324	uint32_t CIS17:1; /* Channel 17 Interrut Status */
1325	uint32_t CIS16:1; /* Channel 16 Interrut Status */
1326	uint32_t CIS15:1; /* Channel 15 Interrut Status */
1327	uint32_t CIS14:1; /* Channel 14 Interrut Status */
1328	uint32_t CIS13:1; /* Channel 13 Interrut Status */
1329	uint32_t CIS12:1; /* Channel 12 Interrut Status */
1330	uint32_t CIS11:1; /* Channel 11 Interrut Status */
1331	uint32_t CIS10:1; /* Channel 10 Interrut Status */
1332	uint32_t CIS9:1; /* Channel 9 Interrut Status */
1333	uint32_t CIS8:1; /* Channel 8 Interrut Status */
1334	uint32_t CIS7:1; /* Channel 7 Interrut Status */
1335	uint32_t CIS6:1; /* Channel 6 Interrut Status */
1336	uint32_t CIS5:1; /* Channel 5 Interrut Status */
1337	uint32_t CIS4:1; /* Channel 4 Interrut Status */
1338	uint32_t CIS3:1; /* Channel 3 Interrut Status */
1339	uint32_t CIS2:1; /* Channel 2 Interrut Status */
1340	uint32_t CIS1:1; /* Channel 1 Interrut Status */
1341	uint32_t CIS0:1; /* Channel 0 Interrut Status */
1342	} B;
1343	} CISR_A;
1344
1345	union { /* ETPU_B Channel Interruput Status */
1346	uint32_t R;
1347	struct {
1348	uint32_t CIS31:1; /* Channel 31 Interrut Status */
1349	uint32_t CIS30:1; /* Channel 30 Interrut Status */
1350	uint32_t CIS29:1; /* Channel 29 Interrut Status */
1351	uint32_t CIS28:1; /* Channel 28 Interrut Status */
1352	uint32_t CIS27:1; /* Channel 27 Interrut Status */
1353	uint32_t CIS26:1; /* Channel 26 Interrut Status */
1354	uint32_t CIS25:1; /* Channel 25 Interrut Status */
1355	uint32_t CIS24:1; /* Channel 24 Interrut Status */
1356	uint32_t CIS23:1; /* Channel 23 Interrut Status */
1357	uint32_t CIS22:1; /* Channel 22 Interrut Status */
1358	uint32_t CIS21:1; /* Channel 21 Interrut Status */
1359	uint32_t CIS20:1; /* Channel 20 Interrut Status */
1360	uint32_t CIS19:1; /* Channel 19 Interrut Status */
1361	uint32_t CIS18:1; /* Channel 18 Interrut Status */
1362	uint32_t CIS17:1; /* Channel 17 Interrut Status */
1363	uint32_t CIS16:1; /* Channel 16 Interrut Status */
1364	uint32_t CIS15:1; /* Channel 15 Interrut Status */
1365	uint32_t CIS14:1; /* Channel 14 Interrut Status */
1366	uint32_t CIS13:1; /* Channel 13 Interrut Status */
1367	uint32_t CIS12:1; /* Channel 12 Interrut Status */
1368	uint32_t CIS11:1; /* Channel 11 Interrut Status */
1369	uint32_t CIS10:1; /* Channel 10 Interrut Status */
1370	uint32_t CIS9:1; /* Channel 9 Interrut Status */
1371	uint32_t CIS8:1; /* Channel 8 Interrut Status */
1372	uint32_t CIS7:1; /* Channel 7 Interrut Status */
1373	uint32_t CIS6:1; /* Channel 6 Interrut Status */
1374	uint32_t CIS5:1; /* Channel 5 Interrut Status */
1375	uint32_t CIS4:1; /* Channel 4 Interrut Status */
1376	uint32_t CIS3:1; /* Channel 3 Interrut Status */
1377	uint32_t CIS2:1; /* Channel 2 Interrut Status */
1378	uint32_t CIS1:1; /* Channel 1 Interrupt Status */
1379	uint32_t CIS0:1; /* Channel 0 Interrupt Status */
1380	} B;
1381	} CISR_B;
1382
1383	uint32_t etpu_reserved9[2];
1384
1385	union { /* ETPU_A Data Transfer Request Status */
1386	uint32_t R;
1387	struct {
1388	uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1389	uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1390	uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1391	uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1392	uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1393	uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1394	uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1395	uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1396	uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1397	uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1398	uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1399	uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1400	uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1401	uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1402	uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1403	uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1404	uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1405	uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1406	uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1407	uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1408	uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1409	uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1410	uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1411	uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1412	uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1413	uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1414	uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1415	uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1416	uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1417	uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1418	uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1419	uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1420	} B;
1421	} CDTRSR_A;
1422
1423	union { /* ETPU_B Data Transfer Request Status */
1424	uint32_t R;
1425	struct {
1426	uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
1427	uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
1428	uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
1429	uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
1430	uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
1431	uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
1432	uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
1433	uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
1434	uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
1435	uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
1436	uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
1437	uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
1438	uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
1439	uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
1440	uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
1441	uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
1442	uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
1443	uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
1444	uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
1445	uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
1446	uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
1447	uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
1448	uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
1449	uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
1450	uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
1451	uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
1452	uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
1453	uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
1454	uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
1455	uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
1456	uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
1457	uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
1458	} B;
1459	} CDTRSR_B;
1460
1461	uint32_t etpu_reserved11[2];
1462
1463	union { /* ETPU_A Interruput Overflow Status */
1464	uint32_t R;
1465	struct {
1466	uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1467	uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1468	uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1469	uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1470	uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1471	uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1472	uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1473	uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1474	uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1475	uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1476	uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1477	uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1478	uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1479	uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1480	uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1481	uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1482	uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1483	uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1484	uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1485	uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1486	uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1487	uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1488	uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1489	uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1490	uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1491	uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1492	uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1493	uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1494	uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1495	uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1496	uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1497	uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1498	} B;
1499	} CIOSR_A;
1500
1501	union { /* ETPU_B Interruput Overflow Status */
1502	uint32_t R;
1503	struct {
1504	uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
1505	uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
1506	uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
1507	uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
1508	uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
1509	uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
1510	uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
1511	uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
1512	uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
1513	uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
1514	uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
1515	uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
1516	uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
1517	uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
1518	uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
1519	uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
1520	uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
1521	uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
1522	uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
1523	uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
1524	uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
1525	uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
1526	uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
1527	uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
1528	uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
1529	uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
1530	uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
1531	uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
1532	uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
1533	uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
1534	uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
1535	uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
1536	} B;
1537	} CIOSR_B;
1538
1539	uint32_t etpu_reserved13[2];
1540
1541	union { /* ETPU_A Data Transfer Overflow Status */
1542	uint32_t R;
1543	struct {
1544	uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1545	uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1546	uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1547	uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1548	uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1549	uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1550	uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1551	uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1552	uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1553	uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1554	uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1555	uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1556	uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1557	uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1558	uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1559	uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1560	uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1561	uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1562	uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1563	uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1564	uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1565	uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1566	uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1567	uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1568	uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1569	uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1570	uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1571	uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1572	uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1573	uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1574	uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1575	uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1576	} B;
1577	} CDTROSR_A;
1578
1579	union { /* ETPU_B Data Transfer Overflow Status */
1580	uint32_t R;
1581	struct {
1582	uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
1583	uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
1584	uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
1585	uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
1586	uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
1587	uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
1588	uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
1589	uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
1590	uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
1591	uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
1592	uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
1593	uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
1594	uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
1595	uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
1596	uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
1597	uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
1598	uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
1599	uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
1600	uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
1601	uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
1602	uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
1603	uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
1604	uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
1605	uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
1606	uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
1607	uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
1608	uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
1609	uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
1610	uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
1611	uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
1612	uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
1613	uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
1614	} B;
1615	} CDTROSR_B;
1616
1617	uint32_t etpu_reserved15[2];
1618
1619	union { /* ETPU_A Channel Interruput Enable */
1620	uint32_t R;
1621	struct {
1622	uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1623	uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1624	uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1625	uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1626	uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1627	uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1628	uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1629	uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1630	uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1631	uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1632	uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1633	uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1634	uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1635	uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1636	uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1637	uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1638	uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1639	uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1640	uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1641	uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1642	uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1643	uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1644	uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1645	uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1646	uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1647	uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1648	uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1649	uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1650	uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1651	uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1652	uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1653	uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1654	} B;
1655	} CIER_A;
1656
1657	union { /* ETPU_B Channel Interruput Enable */
1658	uint32_t R;
1659	struct {
1660	uint32_t CIE31:1; /* Channel 31 Interruput Enable */
1661	uint32_t CIE30:1; /* Channel 30 Interruput Enable */
1662	uint32_t CIE29:1; /* Channel 29 Interruput Enable */
1663	uint32_t CIE28:1; /* Channel 28 Interruput Enable */
1664	uint32_t CIE27:1; /* Channel 27 Interruput Enable */
1665	uint32_t CIE26:1; /* Channel 26 Interruput Enable */
1666	uint32_t CIE25:1; /* Channel 25 Interruput Enable */
1667	uint32_t CIE24:1; /* Channel 24 Interruput Enable */
1668	uint32_t CIE23:1; /* Channel 23 Interruput Enable */
1669	uint32_t CIE22:1; /* Channel 22 Interruput Enable */
1670	uint32_t CIE21:1; /* Channel 21 Interruput Enable */
1671	uint32_t CIE20:1; /* Channel 20 Interruput Enable */
1672	uint32_t CIE19:1; /* Channel 19 Interruput Enable */
1673	uint32_t CIE18:1; /* Channel 18 Interruput Enable */
1674	uint32_t CIE17:1; /* Channel 17 Interruput Enable */
1675	uint32_t CIE16:1; /* Channel 16 Interruput Enable */
1676	uint32_t CIE15:1; /* Channel 15 Interruput Enable */
1677	uint32_t CIE14:1; /* Channel 14 Interruput Enable */
1678	uint32_t CIE13:1; /* Channel 13 Interruput Enable */
1679	uint32_t CIE12:1; /* Channel 12 Interruput Enable */
1680	uint32_t CIE11:1; /* Channel 11 Interruput Enable */
1681	uint32_t CIE10:1; /* Channel 10 Interruput Enable */
1682	uint32_t CIE9:1; /* Channel 9 Interruput Enable */
1683	uint32_t CIE8:1; /* Channel 8 Interruput Enable */
1684	uint32_t CIE7:1; /* Channel 7 Interruput Enable */
1685	uint32_t CIE6:1; /* Channel 6 Interruput Enable */
1686	uint32_t CIE5:1; /* Channel 5 Interruput Enable */
1687	uint32_t CIE4:1; /* Channel 4 Interruput Enable */
1688	uint32_t CIE3:1; /* Channel 3 Interruput Enable */
1689	uint32_t CIE2:1; /* Channel 2 Interruput Enable */
1690	uint32_t CIE1:1; /* Channel 1 Interruput Enable */
1691	uint32_t CIE0:1; /* Channel 0 Interruput Enable */
1692	} B;
1693	} CIER_B;
1694
1695	uint32_t etpu_reserved17[2];
1696
1697	union { /* ETPU_A Channel Data Transfer Request Enable */
1698	uint32_t R;
1699	struct {
1700	uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1701	uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1702	uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1703	uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1704	uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1705	uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1706	uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1707	uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1708	uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1709	uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1710	uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1711	uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1712	uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1713	uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1714	uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1715	uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1716	uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1717	uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1718	uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1719	uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1720	uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1721	uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1722	uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1723	uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1724	uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1725	uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1726	uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1727	uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1728	uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1729	uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1730	uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1731	uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1732	} B;
1733	} CDTRER_A;
1734
1735	union { /* ETPU_B Channel Data Transfer Request Enable */
1736	uint32_t R;
1737	struct {
1738	uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
1739	uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
1740	uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
1741	uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
1742	uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
1743	uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
1744	uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
1745	uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
1746	uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
1747	uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
1748	uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
1749	uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
1750	uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
1751	uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
1752	uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
1753	uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
1754	uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
1755	uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
1756	uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
1757	uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
1758	uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
1759	uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
1760	uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
1761	uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
1762	uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
1763	uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
1764	uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
1765	uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
1766	uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
1767	uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
1768	uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
1769	uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
1770	} B;
1771	} CDTRER_B;
1772
1773	uint32_t etpu_reserved20[10];
1774	union { /* ETPU_A Channel Pending Service Status */
1775	uint32_t R;
1776	struct {
1777	uint32_t SR31:1; /* Channel 31 Pending Service Status */
1778	uint32_t SR30:1; /* Channel 30 Pending Service Status */
1779	uint32_t SR29:1; /* Channel 29 Pending Service Status */
1780	uint32_t SR28:1; /* Channel 28 Pending Service Status */
1781	uint32_t SR27:1; /* Channel 27 Pending Service Status */
1782	uint32_t SR26:1; /* Channel 26 Pending Service Status */
1783	uint32_t SR25:1; /* Channel 25 Pending Service Status */
1784	uint32_t SR24:1; /* Channel 24 Pending Service Status */
1785	uint32_t SR23:1; /* Channel 23 Pending Service Status */
1786	uint32_t SR22:1; /* Channel 22 Pending Service Status */
1787	uint32_t SR21:1; /* Channel 21 Pending Service Status */
1788	uint32_t SR20:1; /* Channel 20 Pending Service Status */
1789	uint32_t SR19:1; /* Channel 19 Pending Service Status */
1790	uint32_t SR18:1; /* Channel 18 Pending Service Status */
1791	uint32_t SR17:1; /* Channel 17 Pending Service Status */
1792	uint32_t SR16:1; /* Channel 16 Pending Service Status */
1793	uint32_t SR15:1; /* Channel 15 Pending Service Status */
1794	uint32_t SR14:1; /* Channel 14 Pending Service Status */
1795	uint32_t SR13:1; /* Channel 13 Pending Service Status */
1796	uint32_t SR12:1; /* Channel 12 Pending Service Status */
1797	uint32_t SR11:1; /* Channel 11 Pending Service Status */
1798	uint32_t SR10:1; /* Channel 10 Pending Service Status */
1799	uint32_t SR9:1; /* Channel 9 Pending Service Status */
1800	uint32_t SR8:1; /* Channel 8 Pending Service Status */
1801	uint32_t SR7:1; /* Channel 7 Pending Service Status */
1802	uint32_t SR6:1; /* Channel 6 Pending Service Status */
1803	uint32_t SR5:1; /* Channel 5 Pending Service Status */
1804	uint32_t SR4:1; /* Channel 4 Pending Service Status */
1805	uint32_t SR3:1; /* Channel 3 Pending Service Status */
1806	uint32_t SR2:1; /* Channel 2 Pending Service Status */
1807	uint32_t SR1:1; /* Channel 1 Pending Service Status */
1808	uint32_t SR0:1; /* Channel 0 Pending Service Status */
1809	} B;
1810	} CPSSR_A;
1811
1812	union { /* ETPU_B Channel Pending Service Status */
1813	uint32_t R;
1814	struct {
1815	uint32_t SR31:1; /* Channel 31 Pending Service Status */
1816	uint32_t SR30:1; /* Channel 30 Pending Service Status */
1817	uint32_t SR29:1; /* Channel 29 Pending Service Status */
1818	uint32_t SR28:1; /* Channel 28 Pending Service Status */
1819	uint32_t SR27:1; /* Channel 27 Pending Service Status */
1820	uint32_t SR26:1; /* Channel 26 Pending Service Status */
1821	uint32_t SR25:1; /* Channel 25 Pending Service Status */
1822	uint32_t SR24:1; /* Channel 24 Pending Service Status */
1823	uint32_t SR23:1; /* Channel 23 Pending Service Status */
1824	uint32_t SR22:1; /* Channel 22 Pending Service Status */
1825	uint32_t SR21:1; /* Channel 21 Pending Service Status */
1826	uint32_t SR20:1; /* Channel 20 Pending Service Status */
1827	uint32_t SR19:1; /* Channel 19 Pending Service Status */
1828	uint32_t SR18:1; /* Channel 18 Pending Service Status */
1829	uint32_t SR17:1; /* Channel 17 Pending Service Status */
1830	uint32_t SR16:1; /* Channel 16 Pending Service Status */
1831	uint32_t SR15:1; /* Channel 15 Pending Service Status */
1832	uint32_t SR14:1; /* Channel 14 Pending Service Status */
1833	uint32_t SR13:1; /* Channel 13 Pending Service Status */
1834	uint32_t SR12:1; /* Channel 12 Pending Service Status */
1835	uint32_t SR11:1; /* Channel 11 Pending Service Status */
1836	uint32_t SR10:1; /* Channel 10 Pending Service Status */
1837	uint32_t SR9:1; /* Channel 9 Pending Service Status */
1838	uint32_t SR8:1; /* Channel 8 Pending Service Status */
1839	uint32_t SR7:1; /* Channel 7 Pending Service Status */
1840	uint32_t SR6:1; /* Channel 6 Pending Service Status */
1841	uint32_t SR5:1; /* Channel 5 Pending Service Status */
1842	uint32_t SR4:1; /* Channel 4 Pending Service Status */
1843	uint32_t SR3:1; /* Channel 3 Pending Service Status */
1844	uint32_t SR2:1; /* Channel 2 Pending Service Status */
1845	uint32_t SR1:1; /* Channel 1 Pending Service Status */
1846	uint32_t SR0:1; /* Channel 0 Pending Service Status */
1847	} B;
1848	} CPSSR_B;
1849
1850	uint32_t etpu_reserved20a[2];
1851
1852	union { /* ETPU_A Channel Service Status */
1853	uint32_t R;
1854	struct {
1855	uint32_t SS31:1; /* Channel 31 Service Status */
1856	uint32_t SS30:1; /* Channel 30 Service Status */
1857	uint32_t SS29:1; /* Channel 29 Service Status */
1858	uint32_t SS28:1; /* Channel 28 Service Status */
1859	uint32_t SS27:1; /* Channel 27 Service Status */
1860	uint32_t SS26:1; /* Channel 26 Service Status */
1861	uint32_t SS25:1; /* Channel 25 Service Status */
1862	uint32_t SS24:1; /* Channel 24 Service Status */
1863	uint32_t SS23:1; /* Channel 23 Service Status */
1864	uint32_t SS22:1; /* Channel 22 Service Status */
1865	uint32_t SS21:1; /* Channel 21 Service Status */
1866	uint32_t SS20:1; /* Channel 20 Service Status */
1867	uint32_t SS19:1; /* Channel 19 Service Status */
1868	uint32_t SS18:1; /* Channel 18 Service Status */
1869	uint32_t SS17:1; /* Channel 17 Service Status */
1870	uint32_t SS16:1; /* Channel 16 Service Status */
1871	uint32_t SS15:1; /* Channel 15 Service Status */
1872	uint32_t SS14:1; /* Channel 14 Service Status */
1873	uint32_t SS13:1; /* Channel 13 Service Status */
1874	uint32_t SS12:1; /* Channel 12 Service Status */
1875	uint32_t SS11:1; /* Channel 11 Service Status */
1876	uint32_t SS10:1; /* Channel 10 Service Status */
1877	uint32_t SS9:1; /* Channel 9 Service Status */
1878	uint32_t SS8:1; /* Channel 8 Service Status */
1879	uint32_t SS7:1; /* Channel 7 Service Status */
1880	uint32_t SS6:1; /* Channel 6 Service Status */
1881	uint32_t SS5:1; /* Channel 5 Service Status */
1882	uint32_t SS4:1; /* Channel 4 Service Status */
1883	uint32_t SS3:1; /* Channel 3 Service Status */
1884	uint32_t SS2:1; /* Channel 2 Service Status */
1885	uint32_t SS1:1; /* Channel 1 Service Status */
1886	uint32_t SS0:1; /* Channel 0 Service Status */
1887	} B;
1888	} CSSR_A;
1889
1890	union { /* ETPU_B Channel Service Status */
1891	uint32_t R;
1892	struct {
1893	uint32_t SS31:1; /* Channel 31 Service Status */
1894	uint32_t SS30:1; /* Channel 30 Service Status */
1895	uint32_t SS29:1; /* Channel 29 Service Status */
1896	uint32_t SS28:1; /* Channel 28 Service Status */
1897	uint32_t SS27:1; /* Channel 27 Service Status */
1898	uint32_t SS26:1; /* Channel 26 Service Status */
1899	uint32_t SS25:1; /* Channel 25 Service Status */
1900	uint32_t SS24:1; /* Channel 24 Service Status */
1901	uint32_t SS23:1; /* Channel 23 Service Status */
1902	uint32_t SS22:1; /* Channel 22 Service Status */
1903	uint32_t SS21:1; /* Channel 21 Service Status */
1904	uint32_t SS20:1; /* Channel 20 Service Status */
1905	uint32_t SS19:1; /* Channel 19 Service Status */
1906	uint32_t SS18:1; /* Channel 18 Service Status */
1907	uint32_t SS17:1; /* Channel 17 Service Status */
1908	uint32_t SS16:1; /* Channel 16 Service Status */
1909	uint32_t SS15:1; /* Channel 15 Service Status */
1910	uint32_t SS14:1; /* Channel 14 Service Status */
1911	uint32_t SS13:1; /* Channel 13 Service Status */
1912	uint32_t SS12:1; /* Channel 12 Service Status */
1913	uint32_t SS11:1; /* Channel 11 Service Status */
1914	uint32_t SS10:1; /* Channel 10 Service Status */
1915	uint32_t SS9:1; /* Channel 9 Service Status */
1916	uint32_t SS8:1; /* Channel 8 Service Status */
1917	uint32_t SS7:1; /* Channel 7 Service Status */
1918	uint32_t SS6:1; /* Channel 6 Service Status */
1919	uint32_t SS5:1; /* Channel 5 Service Status */
1920	uint32_t SS4:1; /* Channel 4 Service Status */
1921	uint32_t SS3:1; /* Channel 3 Service Status */
1922	uint32_t SS2:1; /* Channel 2 Service Status */
1923	uint32_t SS1:1; /* Channel 1 Service Status */
1924	uint32_t SS0:1; /* Channel 0 Service Status */
1925	} B;
1926	} CSSR_B;
1927
1928	uint32_t etpu_reserved23[90];
1929
1930	/***************************Channels******************************/
1931
1932	struct {
1933	union {
1934	uint32_t R; /* Channel Configuration Register */
1935	struct {
1936	uint32_t CIE:1; /* Channel Interruput Enable */
1937	uint32_t DTRE:1; /* Data Transfer Request Enable */
1938	uint32_t CPR:2; /* Channel Priority */
1939	uint32_t:3;
1940	uint32_t ETCS:1; /* Entry Table Condition Select */
1941	uint32_t:3;
1942	uint32_t CFS:5; /* Channel Function Select */
1943	uint32_t ODIS:1; /* Output disable */
1944	uint32_t OPOL:1; /* output polarity */
1945	uint32_t:3;
1946	uint32_t CPBA:11; /* Channel Parameter Base Address */
1947	} B;
1948	} CR;
1949	union {
1950	uint32_t R; /* Channel Status Control Register */
1951	struct {
1952	uint32_t CIS:1; /* Channel Interruput Status */
1953	uint32_t CIOS:1; /* Channel Interruput Overflow Status */
1954	uint32_t:6;
1955	uint32_t DTRS:1; /* Data Transfer Status */
1956	uint32_t DTROS:1; /* Data Transfer Overflow Status */
1957	uint32_t:6;
1958	uint32_t IPS:1; /* Input Pin State */
1959	uint32_t OPS:1; /* Output Pin State */
1960	uint32_t OBE:1; /* Output Buffer Enable */
1961	uint32_t:11;
1962	uint32_t FM1:1; /* Function mode */
1963	uint32_t FM0:1; /* Function mode */
1964	} B;
1965	} SCR;
1966	union {
1967	uint32_t R; /* Channel Host Service Request Register */
1968	struct {
1969	uint32_t:29; /* Host Service Request */
1970	uint32_t HSR:3;
1971	} B;
1972	} HSRR;
1973	uint32_t etpu_reserved23;
1974	} CHAN[127];
1975
1976	};
1977	/****************************************************************************/
1978	/* MODULE : XBAR CrossBar */
1979	/****************************************************************************/
1980	struct XBAR_tag {
1981	union {
1982	uint32_t R;
1983	struct {
1984	uint32_t:4;
1985
1986	uint32_t:4;
1987
1988	uint32_t:4;
1989
1990	uint32_t:4;
1991
1992	uint32_t:4;
1993
1994	uint32_t:1;
1995	uint32_t MSTR2:3;
1996	uint32_t:1;
1997	uint32_t MSTR1:3;
1998	uint32_t:1;
1999	uint32_t MSTR0:3;
2000	} B;
2001	} MPR0; /* Master Priority Register for Slave Port 0 */
2002
2003	uint32_t xbar_reserved1[3];
2004
2005	union {
2006	uint32_t R;
2007	struct {
2008	uint32_t RO:1;
2009	uint32_t:21;
2010	uint32_t ARB:2;
2011	uint32_t:2;
2012	uint32_t PCTL:2;
2013	uint32_t:1;
2014	uint32_t PARK:3;
2015	} B;
2016	} SGPCR0; /* General Purpose Control Register for Slave Port 0 */
2017
2018	uint32_t xbar_reserved2[59];
2019
2020	union {
2021	uint32_t R;
2022	struct {
2023	uint32_t:4;
2024
2025	uint32_t:4;
2026
2027	uint32_t:4;
2028
2029	uint32_t:4;
2030
2031	uint32_t:4;
2032
2033	uint32_t:1;
2034	uint32_t MSTR2:3;
2035	uint32_t:1;
2036	uint32_t MSTR1:3;
2037	uint32_t:1;
2038	uint32_t MSTR0:3;
2039	} B;
2040	} MPR1; /* Master Priority Register for Slave Port 1 */
2041
2042	uint32_t xbar_reserved3[3];
2043
2044	union {
2045	uint32_t R;
2046	struct {
2047	uint32_t RO:1;
2048	uint32_t:21;
2049	uint32_t ARB:2;
2050	uint32_t:2;
2051	uint32_t PCTL:2;
2052	uint32_t:1;
2053	uint32_t PARK:3;
2054	} B;
2055	} SGPCR1; /* General Purpose Control Register for Slave Port 1 */
2056
2057	uint32_t xbar_reserved4[123];
2058
2059	union {
2060	uint32_t R;
2061	struct {
2062	uint32_t:4;
2063
2064	uint32_t:4;
2065
2066	uint32_t:4;
2067
2068	uint32_t:4;
2069
2070	uint32_t:4;
2071
2072	uint32_t:1;
2073	uint32_t MSTR2:3;
2074	uint32_t:1;
2075	uint32_t MSTR1:3;
2076	uint32_t:1;
2077	uint32_t MSTR0:3;
2078	} B;
2079	} MPR3; /* Master Priority Register for Slave Port 3 */
2080
2081	uint32_t xbar_reserved5[3];
2082
2083	union {
2084	uint32_t R;
2085	struct {
2086	uint32_t RO:1;
2087	uint32_t:21;
2088	uint32_t ARB:2;
2089	uint32_t:2;
2090	uint32_t PCTL:2;
2091	uint32_t:1;
2092	uint32_t PARK:3;
2093	} B;
2094	} SGPCR3; /* General Purpose Control Register for Slave Port 3 */
2095	uint32_t xbar_reserved6[187];
2096
2097	union {
2098	uint32_t R;
2099	struct {
2100	uint32_t:4;
2101
2102	uint32_t:4;
2103
2104	uint32_t:4;
2105
2106	uint32_t:4;
2107
2108	uint32_t:4;
2109
2110	uint32_t:1;
2111	uint32_t MSTR2:3;
2112	uint32_t:1;
2113	uint32_t MSTR1:3;
2114	uint32_t:1;
2115	uint32_t MSTR0:3;
2116	} B;
2117	} MPR6; /* Master Priority Register for Slave Port 6 */
2118
2119	uint32_t xbar_reserved7[3];
2120
2121	union {
2122	uint32_t R;
2123	struct {
2124	uint32_t RO:1;
2125	uint32_t:21;
2126	uint32_t ARB:2;
2127	uint32_t:2;
2128	uint32_t PCTL:2;
2129	uint32_t:1;
2130	uint32_t PARK:3;
2131	} B;
2132	} SGPCR6; /* General Purpose Control Register for Slave Port 6 */
2133
2134	uint32_t xbar_reserved8[59];
2135
2136	union {
2137	uint32_t R;
2138	struct {
2139	uint32_t:4;
2140
2141	uint32_t:4;
2142
2143	uint32_t:4;
2144
2145	uint32_t:4;
2146
2147	uint32_t:4;
2148
2149	uint32_t:1;
2150	uint32_t MSTR2:3;
2151	uint32_t:1;
2152	uint32_t MSTR1:3;
2153	uint32_t:1;
2154	uint32_t MSTR0:3;
2155	} B;
2156	} MPR7; /* Master Priority Register for Slave Port 7 */
2157
2158	uint32_t xbar_reserved9[3];
2159
2160	union {
2161	uint32_t R;
2162	struct {
2163	uint32_t RO:1;
2164	uint32_t:21;
2165	uint32_t ARB:2;
2166	uint32_t:2;
2167	uint32_t PCTL:2;
2168	uint32_t:1;
2169	uint32_t PARK:3;
2170	} B;
2171	} SGPCR7; /* General Purpose Control Register for Slave Port 7 */
2172
2173	};
2174	/****************************************************************************/
2175	/* MODULE : ECSM */
2176	/****************************************************************************/
2177	struct ECSM_tag {
2178
2179	uint32_t ecsm_reserved1[5];
2180
2181	uint16_t ecsm_reserved2;
2182
2183	union {
2184	uint16_t R;
2185	} SWTCR; //Software Watchdog Timer Control
2186
2187	uint8_t ecsm_reserved3[3];
2188
2189	union {
2190	uint8_t R;
2191	} SWTSR; //SWT Service Register
2192
2193	uint8_t ecsm_reserved4[3];
2194
2195	union {
2196	uint8_t R;
2197	} SWTIR; //SWT Interrupt Register
2198
2199	uint32_t ecsm_reserved5a[1];
2200	uint32_t ecsm_reserved5b[1];
2201
2202	uint32_t ecsm_reserved5c[6];
2203
2204	uint8_t ecsm_reserved6[3];
2205
2206	union {
2207	uint8_t R;
2208	struct {
2209	uint8_t:6;
2210	uint8_t ERNCR:1;
2211	uint8_t EFNCR:1;
2212	} B;
2213	} ECR; //ECC Configuration Register
2214
2215	uint8_t mcm_reserved8[3];
2216
2217	union {
2218	uint8_t R;
2219	struct {
2220	uint8_t:6;
2221	uint8_t RNCE:1;
2222	uint8_t FNCE:1;
2223	} B;
2224	} ESR; //ECC Status Register
2225
2226	uint16_t ecsm_reserved9;
2227
2228	union {
2229	uint16_t R;
2230	struct {
2231	uint16_t:6;
2232	uint16_t FRCNCI:1;
2233	uint16_t FR1NCI:1;
2234	uint16_t:1;
2235	uint16_t ERRBIT:7;
2236	} B;
2237	} EEGR; //ECC Error Generation Register
2238
2239	uint32_t ecsm_reserved10;
2240
2241	union {
2242	uint32_t R;
2243	struct {
2244	uint32_t FEAR:32;
2245	} B;
2246	} FEAR; //Flash ECC Address Register
2247
2248	uint16_t ecsm_reserved11;
2249
2250	union {
2251	uint8_t R;
2252	struct {
2253	uint8_t:4;
2254	uint8_t FEMR:4;
2255	} B;
2256	} FEMR; //Flash ECC Master Register
2257
2258	union {
2259	uint8_t R;
2260	struct {
2261	uint8_t WRITE:1;
2262	uint8_t SIZE:3;
2263	uint8_t PROT0:1;
2264	uint8_t PROT1:1;
2265	uint8_t PROT2:1;
2266	uint8_t PROT3:1;
2267	} B;
2268	} FEAT; //Flash ECC Attributes Register
2269
2270	union {
2271	uint32_t R;
2272	struct {
2273	uint32_t FEDH:32;
2274	} B;
2275	} FEDRH; //Flash ECC Data High Register
2276
2277	union {
2278	uint32_t R;
2279	struct {
2280	uint32_t FEDL:32;
2281	} B;
2282	} FEDRL; //Flash ECC Data Low Register
2283
2284	union {
2285	uint32_t R;
2286	struct {
2287	uint32_t REAR:32;
2288	} B;
2289	} REAR; //RAM ECC Address
2290
2291	uint8_t ecsm_reserved12[2];
2292
2293	union {
2294	uint8_t R;
2295	struct {
2296	uint8_t:4;
2297	uint8_t REMR:4;
2298	} B;
2299	} REMR; //RAM ECC Master
2300
2301	union {
2302	uint8_t R;
2303	struct {
2304	uint8_t WRITE:1;
2305	uint8_t SIZE:3;
2306	uint8_t PROT0:1;
2307	uint8_t PROT1:1;
2308	uint8_t PROT2:1;
2309	uint8_t PROT3:1;
2310	} B;
2311	} REAT; // RAM ECC Attributes Register
2312
2313	union {
2314	uint32_t R;
2315	struct {
2316	uint32_t REDH:32;
2317	} B;
2318	} REDRH; //RAM ECC Data High Register
2319
2320	union {
2321	uint32_t R;
2322	struct {
2323	uint32_t REDL:32;
2324	} B;
2325	} REDRL; //RAMECC Data Low Register
2326
2327	};
2328	/****************************************************************************/
2329	/* MODULE : INTC */
2330	/****************************************************************************/
2331	struct INTC_tag {
2332	union {
2333	uint32_t R;
2334	struct {
2335	uint32_t:26;
2336	uint32_t VTES:1;
2337	uint32_t:4;
2338	uint32_t HVEN:1;
2339	} B;
2340	} MCR; /* Module Configuration Register */
2341
2342	int32_t INTC_reserved00;
2343
2344	union {
2345	uint32_t R;
2346	struct {
2347	uint32_t:28;
2348	uint32_t PRI:4;
2349	} B;
2350	} CPR; /* Current Priority Register */
2351
2352	uint32_t intc_reserved1;
2353
2354	union {
2355	uint32_t R;
2356	struct {
2357	uint32_t VTBA:21;
2358	uint32_t INTVEC:9;
2359	uint32_t:2;
2360	} B;
2361	} IACKR; /* Interrupt Acknowledge Register */
2362
2363	uint32_t intc_reserved2;
2364
2365	union {
2366	uint32_t R;
2367	struct {
2368	uint32_t:32;
2369	} B;
2370	} EOIR; /* End of Interrupt Register */
2371
2372	uint32_t intc_reserved3;
2373
2374	union {
2375	uint8_t R;
2376	struct {
2377	uint8_t:6;
2378	uint8_t SET:1;
2379	uint8_t CLR:1;
2380	} B;
2381	} SSCIR[8]; /* Software Set/Clear Interruput Register */
2382
2383	uint32_t intc_reserved4[6];
2384
2385	union {
2386	uint8_t R;
2387	struct {
2388	uint8_t:4;
2389	uint8_t PRI:4;
2390	} B;
2391	} PSR[358]; /* Software Set/Clear Interrupt Register */
2392
2393	};
2394	/****************************************************************************/
2395	/* MODULE : EQADC */
2396	/****************************************************************************/
2397	struct EQADC_tag {
2398	union {
2399	uint32_t R;
2400	struct {
2401	uint32_t:27;
2402	uint32_t ESSIE:2;
2403	uint32_t:1;
2404	uint32_t DBG:2;
2405	} B;
2406	} MCR; /* Module Configuration Register */
2407
2408	int32_t EQADC_reserved00;
2409
2410	union {
2411	uint32_t R;
2412	struct {
2413	uint32_t:6;
2414	uint32_t NMF:26;
2415	} B;
2416	} NMSFR; /* Null Message Send Format Register */
2417
2418	union {
2419	uint32_t R;
2420	struct {
2421	uint32_t:28;
2422	uint32_t DFL:4;
2423	} B;
2424	} ETDFR; /* External Trigger Digital Filter Register */
2425
2426	union {
2427	uint32_t R;
2428	struct {
2429	uint32_t CFPUSH:32;
2430	} B;
2431	} CFPR[6]; /* CFIFO Push Registers */
2432
2433	uint32_t eqadc_reserved1;
2434
2435	uint32_t eqadc_reserved2;
2436
2437	union {
2438	uint32_t R;
2439	struct {
2440	uint32_t:16;
2441	uint32_t RFPOP:16;
2442	} B;
2443	} RFPR[6]; /* Result FIFO Pop Registers */
2444
2445	uint32_t eqadc_reserved3;
2446
2447	uint32_t eqadc_reserved4;
2448
2449	union EQADC_CFCR_tag {
2450	uint16_t R;
2451	struct {
2452	uint16_t:5;
2453	uint16_t SSE:1;
2454	uint16_t CFINV:1;
2455	uint16_t:1;
2456	uint16_t MODE:4;
2457	uint16_t:4;
2458	} B;
2459	} CFCR[6]; /* CFIFO Control Registers */
2460
2461	uint32_t eqadc_reserved5;
2462
2463	union EQADC_IDCR_tag {
2464	uint16_t R;
2465	struct {
2466	uint16_t NCIE:1;
2467	uint16_t TORIE:1;
2468	uint16_t PIE:1;
2469	uint16_t EOQIE:1;
2470	uint16_t CFUIE:1;
2471	uint16_t:1;
2472	uint16_t CFFE:1;
2473	uint16_t CFFS:1;
2474	uint16_t:4;
2475	uint16_t RFOIE:1;
2476	uint16_t:1;
2477	uint16_t RFDE:1;
2478	uint16_t RFDS:1;
2479	} B;
2480	} IDCR[6]; /* Interrupt and DMA Control Registers */
2481
2482	uint32_t eqadc_reserved6;
2483
2484	union EQADC_FISR_tag {
2485	uint32_t R;
2486	struct {
2487	uint32_t NCF:1;
2488	uint32_t TORF:1;
2489	uint32_t PF:1;
2490	uint32_t EOQF:1;
2491	uint32_t CFUF:1;
2492	uint32_t SSS:1;
2493	uint32_t CFFF:1;
2494	uint32_t:5;
2495	uint32_t RFOF:1;
2496	uint32_t:1;
2497	uint32_t RFDF:1;
2498	uint32_t:1;
2499	uint32_t CFCTR:4;
2500	uint32_t TNXTPTR:4;
2501	uint32_t RFCTR:4;
2502	uint32_t POPNXTPTR:4;
2503	} B;
2504	} FISR[6]; /* FIFO and Interrupt Status Registers */
2505
2506	uint32_t eqadc_reserved7;
2507
2508	uint32_t eqadc_reserved8;
2509
2510	union {
2511	uint16_t R;
2512	struct {
2513	uint16_t:5;
2514	uint16_t TCCF:11;
2515	} B;
2516	} CFTCR[6]; /* CFIFO Transfer Counter Registers */
2517
2518	uint32_t eqadc_reserved9;
2519
2520	union {
2521	uint32_t R;
2522	struct {
2523	uint32_t CFS0:2;
2524	uint32_t CFS1:2;
2525	uint32_t CFS2:2;
2526	uint32_t CFS3:2;
2527	uint32_t CFS4:2;
2528	uint32_t CFS5:2;
2529	uint32_t:5;
2530	uint32_t LCFTCB0:4;
2531	uint32_t TC_LCFTCB0:11;
2532	} B;
2533	} CFSSR0; /* CFIFO Status Register 0 */
2534
2535	union {
2536	uint32_t R;
2537	struct {
2538	uint32_t CFS0:2;
2539	uint32_t CFS1:2;
2540	uint32_t CFS2:2;
2541	uint32_t CFS3:2;
2542	uint32_t CFS4:2;
2543	uint32_t CFS5:2;
2544	uint32_t:5;
2545	uint32_t LCFTCB1:4;
2546	uint32_t TC_LCFTCB1:11;
2547	} B;
2548	} CFSSR1; /* CFIFO Status Register 1 */
2549
2550	union {
2551	uint32_t R;
2552	struct {
2553	uint32_t CFS0:2;
2554	uint32_t CFS1:2;
2555	uint32_t CFS2:2;
2556	uint32_t CFS3:2;
2557	uint32_t CFS4:2;
2558	uint32_t CFS5:2;
2559	uint32_t:4;
2560	uint32_t ECBNI:1;
2561	uint32_t LCFTSSI:4;
2562	uint32_t TC_LCFTSSI:11;
2563	} B;
2564	} CFSSR2; /* CFIFO Status Register 2 */
2565
2566	union {
2567	uint32_t R;
2568	struct {
2569	uint32_t CFS0:2;
2570	uint32_t CFS1:2;
2571	uint32_t CFS2:2;
2572	uint32_t CFS3:2;
2573	uint32_t CFS4:2;
2574	uint32_t CFS5:2;
2575	uint32_t:20;
2576	} B;
2577	} CFSR;
2578
2579	uint32_t eqadc_reserved11;
2580
2581	union {
2582	uint32_t R;
2583	struct {
2584	uint32_t:21;
2585	uint32_t MDT:3;
2586	uint32_t:4;
2587	uint32_t BR:4;
2588	} B;
2589	} SSICR; /* SSI Control Register */
2590
2591	union {
2592	uint32_t R;
2593	struct {
2594	uint32_t RDV:1;
2595	uint32_t:5;
2596	uint32_t RDATA:26;
2597	} B;
2598	} SSIRDR; /* SSI Recieve Data Register */
2599
2600	uint32_t eqadc_reserved12[17];
2601
2602	struct {
2603	union {
2604	uint32_t R;
2605	struct {
2606	uint32_t:32;
2607	} B;
2608	} R[4];
2609
2610	uint32_t eqadc_reserved13[12];
2611
2612	} CF[6];
2613
2614	uint32_t eqadc_reserved14[32];
2615
2616	struct {
2617	union {
2618	uint32_t R;
2619	struct {
2620	uint32_t:32;
2621	} B;
2622	} R[4];
2623
2624	uint32_t eqadc_reserved15[12];
2625
2626	} RF[6];
2627
2628	};
2629
2630	/* Message Formats for On-Chip ADC Operation
2631	*/
2632	union EQADC_CONVERSION_COMMAND_tag {
2633	uint32_t R;
2634	struct {
2635	uint32_t EOQ:1;
2636	uint32_t PAUSE:1;
2637	uint32_t:3;
2638	uint32_t EB:1;
2639	uint32_t BN:1;
2640	uint32_t CAL:1;
2641	uint32_t MESSAGE_TAG:4;
2642	uint32_t LST:2;
2643	uint32_t TSR:1;
2644	uint32_t FMT:1;
2645	uint32_t CHANNEL_NUMBER:8;
2646	uint32_t:8;
2647	} B;
2648	}; /* Conversion command */
2649
2650	union EQADC_WRITE_CONFIGURATION_COMMAND_tag {
2651	uint32_t R;
2652	struct {
2653	uint32_t EOQ:1;
2654	uint32_t PAUSE:1;
2655	uint32_t:3;
2656	uint32_t EB:1;
2657	uint32_t BN:1;
2658	uint32_t RW:1;
2659	uint32_t VALUE:16;
2660	uint32_t ADDR:8;
2661	} B;
2662	}; /* Write configuration command */
2663
2664	/****************************************************************************/
2665	/* MODULE : DSPI */
2666	/****************************************************************************/
2667	struct DSPI_tag {
2668	union DSPI_MCR_tag {
2669	uint32_t R;
2670	struct {
2671	uint32_t MSTR:1;
2672	uint32_t CONT_SCKE:1;
2673	uint32_t DCONF:2;
2674	uint32_t FRZ:1;
2675	uint32_t MTFE:1;
2676	uint32_t PCSSE:1;
2677	uint32_t ROOE:1;
2678	uint32_t:2;
2679	uint32_t PCSIS5:1;
2680	uint32_t PCSIS4:1;
2681	uint32_t PCSIS3:1;
2682	uint32_t PCSIS2:1;
2683	uint32_t PCSIS1:1;
2684	uint32_t PCSIS0:1;
2685	uint32_t DOZE:1;
2686	uint32_t MDIS:1;
2687	uint32_t DIS_TXF:1;
2688	uint32_t DIS_RXF:1;
2689	uint32_t CLR_TXF:1;
2690	uint32_t CLR_RXF:1;
2691	uint32_t SMPL_PT:2;
2692	uint32_t:7;
2693	uint32_t HALT:1;
2694	} B;
2695	} MCR; /* Module Configuration Register */
2696
2697	uint32_t dspi_reserved1;
2698
2699	union {
2700	uint32_t R;
2701	struct {
2702	uint32_t TCNT:16;
2703	uint32_t:16;
2704	} B;
2705	} TCR;
2706
2707	union DSPI_CTAR_tag {
2708	uint32_t R;
2709	struct {
2710	uint32_t DBR:1;
2711	uint32_t FMSZ:4;
2712	uint32_t CPOL:1;
2713	uint32_t CPHA:1;
2714	uint32_t LSBFE:1;
2715	uint32_t PCSSCK:2;
2716	uint32_t PASC:2;
2717	uint32_t PDT:2;
2718	uint32_t PBR:2;
2719	uint32_t CSSCK:4;
2720	uint32_t ASC:4;
2721	uint32_t DT:4;
2722	uint32_t BR:4;
2723	} B;
2724	} CTAR[8]; /* Clock and Transfer Attributes Registers */
2725
2726	union DSPI_SR_tag {
2727	uint32_t R;
2728	struct {
2729	uint32_t TCF:1;
2730	uint32_t TXRXS:1;
2731	uint32_t:1;
2732	uint32_t EOQF:1;
2733	uint32_t TFUF:1;
2734	uint32_t:1;
2735	uint32_t TFFF:1;
2736	uint32_t:5;
2737	uint32_t RFOF:1;
2738	uint32_t:1;
2739	uint32_t RFDF:1;
2740	uint32_t:1;
2741	uint32_t TXCTR:4;
2742	uint32_t TXNXTPTR:4;
2743	uint32_t RXCTR:4;
2744	uint32_t POPNXTPTR:4;
2745	} B;
2746	} SR; /* Status Register */
2747
2748	union DSPI_RSER_tag {
2749	uint32_t R;
2750	struct {
2751	uint32_t TCFRE:1;
2752	uint32_t:2;
2753	uint32_t EOQFRE:1;
2754	uint32_t TFUFRE:1;
2755	uint32_t:1;
2756	uint32_t TFFFRE:1;
2757	uint32_t TFFFDIRS:1;
2758	uint32_t:4;
2759	uint32_t RFOFRE:1;
2760	uint32_t:1;
2761	uint32_t RFDFRE:1;
2762	uint32_t RFDFDIRS:1;
2763	uint32_t:16;
2764	} B;
2765	} RSER; /* DMA/Interrupt Request Select and Enable Register */
2766
2767	union DSPI_PUSHR_tag {
2768	uint32_t R;
2769	struct {
2770	uint32_t CONT:1;
2771	uint32_t CTAS:3;
2772	uint32_t EOQ:1;
2773	uint32_t CTCNT:1;
2774	uint32_t:4;
2775	uint32_t PCS5:1;
2776	uint32_t PCS4:1;
2777	uint32_t PCS3:1;
2778	uint32_t PCS2:1;
2779	uint32_t PCS1:1;
2780	uint32_t PCS0:1;
2781	uint32_t TXDATA:16;
2782	} B;
2783	} PUSHR; /* PUSH TX FIFO Register */
2784
2785	union DSPI_POPR_tag {
2786	uint32_t R;
2787	struct {
2788	uint32_t:16;
2789	uint32_t RXDATA:16;
2790	} B;
2791	} POPR; /* POP RX FIFO Register */
2792
2793	union {
2794	uint32_t R;
2795	struct {
2796	uint32_t TXCMD:16;
2797	uint32_t TXDATA:16;
2798	} B;
2799	} TXFR[4]; /* Transmit FIFO Registers */
2800
2801	uint32_t DSPI_reserved_txf[12];
2802
2803	union {
2804	uint32_t R;
2805	struct {
2806	uint32_t:16;
2807	uint32_t RXDATA:16;
2808	} B;
2809	} RXFR[4]; /* Transmit FIFO Registers */
2810
2811	uint32_t DSPI_reserved_rxf[12];
2812
2813	union {
2814	uint32_t R;
2815	struct {
2816	uint32_t MTOE:1;
2817	uint32_t:1;
2818	uint32_t MTOCNT:6;
2819	uint32_t:4;
2820	uint32_t TXSS:1;
2821	uint32_t TPOL:1;
2822	uint32_t TRRE:1;
2823	uint32_t CID:1;
2824	uint32_t DCONT:1;
2825	uint32_t DSICTAS:3;
2826	uint32_t:6;
2827	uint32_t DPCS5:1;
2828	uint32_t DPCS4:1;
2829	uint32_t DPCS3:1;
2830	uint32_t DPCS2:1;
2831	uint32_t DPCS1:1;
2832	uint32_t DPCS0:1;
2833	} B;
2834	} DSICR; /* DSI Configuration Register */
2835
2836	union {
2837	uint32_t R;
2838	struct {
2839	uint32_t:16;
2840	uint32_t SER_DATA:16;
2841	} B;
2842	} SDR; /* DSI Serialization Data Register */
2843
2844	union {
2845	uint32_t R;
2846	struct {
2847	uint32_t:16;
2848	uint32_t ASER_DATA:16;
2849	} B;
2850	} ASDR; /* DSI Alternate Serialization Data Register */
2851
2852	union {
2853	uint32_t R;
2854	struct {
2855	uint32_t:16;
2856	uint32_t COMP_DATA:16;
2857	} B;
2858	} COMPR; /* DSI Transmit Comparison Register */
2859
2860	union {
2861	uint32_t R;
2862	struct {
2863	uint32_t:16;
2864	uint32_t DESER_DATA:16;
2865	} B;
2866	} DDR; /* DSI deserialization Data Register */
2867
2868	};
2869	/****************************************************************************/
2870	/* MODULE : eSCI */
2871	/****************************************************************************/
2872	struct ESCI_tag {
2873	union ESCI_CR1_tag {
2874	uint32_t R;
2875	struct {
2876	uint32_t:3;
2877	uint32_t SBR:13;
2878	uint32_t LOOPS:1;
2879	uint32_t SCISDOZ:1;
2880	uint32_t RSRC:1;
2881	uint32_t M:1;
2882	uint32_t WAKE:1;
2883	uint32_t ILT:1;
2884	uint32_t PE:1;
2885	uint32_t PT:1;
2886	uint32_t TIE:1;
2887	uint32_t TCIE:1;
2888	uint32_t RIE:1;
2889	uint32_t ILIE:1;
2890	uint32_t TE:1;
2891	uint32_t RE:1;
2892	uint32_t RWU:1;
2893	uint32_t SBK:1;
2894	} B;
2895	} CR1; /* Control Register 1 */
2896
2897	union ESCI_CR2_tag {
2898	uint16_t R;
2899	struct {
2900	uint16_t MDIS:1;
2901	uint16_t FBR:1;
2902	uint16_t BSTP:1;
2903	uint16_t IEBERR:1;
2904	uint16_t RXDMA:1;
2905	uint16_t TXDMA:1;
2906	uint16_t BRK13:1;
2907	uint16_t:1;
2908	uint16_t BESM13:1;
2909	uint16_t SBSTP:1;
2910	uint16_t:2;
2911	uint16_t ORIE:1;
2912	uint16_t NFIE:1;
2913	uint16_t FEIE:1;
2914	uint16_t PFIE:1;
2915	} B;
2916	} CR2; /* Control Register 2 */
2917
2918	union ESCI_DR_tag {
2919	uint16_t R;
2920	struct {
2921	uint16_t R8:1;
2922	uint16_t T8:1;
2923	uint16_t:6;
2924	uint8_t D;
2925	} B;
2926	} DR; /* Data Register */
2927
2928	union ESCI_SR_tag {
2929	uint32_t R;
2930	struct {
2931	uint32_t TDRE:1;
2932	uint32_t TC:1;
2933	uint32_t RDRF:1;
2934	uint32_t IDLE:1;
2935	uint32_t OR:1;
2936	uint32_t NF:1;
2937	uint32_t FE:1;
2938	uint32_t PF:1;
2939	uint32_t:3;
2940	uint32_t BERR:1;
2941	uint32_t:3;
2942	uint32_t RAF:1;
2943	uint32_t RXRDY:1;
2944	uint32_t TXRDY:1;
2945	uint32_t LWAKE:1;
2946	uint32_t STO:1;
2947	uint32_t PBERR:1;
2948	uint32_t CERR:1;
2949	uint32_t CKERR:1;
2950	uint32_t FRC:1;
2951	uint32_t:7;
2952	uint32_t OVFL:1;
2953	} B;
2954	} SR; /* Status Register */
2955
2956	union {
2957	uint32_t R;
2958	struct {
2959	uint32_t LRES:1;
2960	uint32_t WU:1;
2961	uint32_t WUD0:1;
2962	uint32_t WUD1:1;
2963	uint32_t LDBG:1;
2964	uint32_t DSF:1;
2965	uint32_t PRTY:1;
2966	uint32_t LIN:1;
2967	uint32_t RXIE:1;
2968	uint32_t TXIE:1;
2969	uint32_t WUIE:1;
2970	uint32_t STIE:1;
2971	uint32_t PBIE:1;
2972	uint32_t CIE:1;
2973	uint32_t CKIE:1;
2974	uint32_t FCIE:1;
2975	uint32_t:7;
2976	uint32_t OFIE:1;
2977	uint32_t:8;
2978	} B;
2979	} LCR; /* LIN Control Register */
2980
2981	union {
2982	uint32_t R;
2983	} LTR; /* LIN Transmit Register */
2984
2985	union {
2986	uint32_t R;
2987	} LRR; /* LIN Recieve Register */
2988
2989	union {
2990	uint32_t R;
2991	} LPR; /* LIN CRC Polynom Register */
2992
2993	};
2994	/****************************************************************************/
2995	/* MODULE : FlexCAN */
2996	/****************************************************************************/
2997	struct FLEXCAN2_tag {
2998	union {
2999	uint32_t R;
3000	struct {
3001	uint32_t MDIS:1;
3002	uint32_t FRZ:1;
3003	uint32_t:1;
3004	uint32_t HALT:1;
3005	uint32_t NOTRDY:1;
3006	uint32_t:1;
3007	uint32_t SOFTRST:1;
3008	uint32_t FRZACK:1;
3009	uint32_t:1;
3010	uint32_t:1;
3011
3012	uint32_t:1;
3013
3014	uint32_t MDISACK:1;
3015	uint32_t:1;
3016	uint32_t:1;
3017
3018	uint32_t:12;
3019
3020	uint32_t MAXMB:6;
3021	} B;
3022	} MCR; /* Module Configuration Register */
3023
3024	union {
3025	uint32_t R;
3026	struct {
3027	uint32_t PRESDIV:8;
3028	uint32_t RJW:2;
3029	uint32_t PSEG1:3;
3030	uint32_t PSEG2:3;
3031	uint32_t BOFFMSK:1;
3032	uint32_t ERRMSK:1;
3033	uint32_t CLKSRC:1;
3034	uint32_t LPB:1;
3035
3036	uint32_t:4;
3037
3038	uint32_t SMP:1;
3039	uint32_t BOFFREC:1;
3040	uint32_t TSYN:1;
3041	uint32_t LBUF:1;
3042	uint32_t LOM:1;
3043	uint32_t PROPSEG:3;
3044	} B;
3045	} CR; /* Control Register */
3046
3047	union {
3048	uint32_t R;
3049	} TIMER; /* Free Running Timer */
3050	int32_t FLEXCAN_reserved00;
3051
3052	union {
3053	uint32_t R;
3054	struct {
3055	uint32_t:3;
3056	uint32_t MI:29;
3057	} B;
3058	} RXGMASK; /* RX Global Mask */
3059
3060	union {
3061	uint32_t R;
3062	struct {
3063	uint32_t:3;
3064	uint32_t MI:29;
3065	} B;
3066	} RX14MASK; /* RX 14 Mask */
3067
3068	union {
3069	uint32_t R;
3070	struct {
3071	uint32_t:3;
3072	uint32_t MI:29;
3073	} B;
3074	} RX15MASK; /* RX 15 Mask */
3075
3076	union {
3077	uint32_t R;
3078	struct {
3079	uint32_t:16;
3080	uint32_t RXECNT:8;
3081	uint32_t TXECNT:8;
3082	} B;
3083	} ECR; /* Error Counter Register */
3084
3085	union {
3086	uint32_t R;
3087	struct {
3088	uint32_t:14;
3089
3090	uint32_t:2;
3091
3092	uint32_t BIT1ERR:1;
3093	uint32_t BIT0ERR:1;
3094	uint32_t ACKERR:1;
3095	uint32_t CRCERR:1;
3096	uint32_t FRMERR:1;
3097	uint32_t STFERR:1;
3098	uint32_t TXWRN:1;
3099	uint32_t RXWRN:1;
3100	uint32_t IDLE:1;
3101	uint32_t TXRX:1;
3102	uint32_t FLTCONF:2;
3103	uint32_t:1;
3104	uint32_t BOFFINT:1;
3105	uint32_t ERRINT:1;
3106	uint32_t:1;
3107	} B;
3108	} ESR; /* Error and Status Register */
3109
3110	union {
3111	uint32_t R;
3112	struct {
3113	uint32_t BUF63M:1;
3114	uint32_t BUF62M:1;
3115	uint32_t BUF61M:1;
3116	uint32_t BUF60M:1;
3117	uint32_t BUF59M:1;
3118	uint32_t BUF58M:1;
3119	uint32_t BUF57M:1;
3120	uint32_t BUF56M:1;
3121	uint32_t BUF55M:1;
3122	uint32_t BUF54M:1;
3123	uint32_t BUF53M:1;
3124	uint32_t BUF52M:1;
3125	uint32_t BUF51M:1;
3126	uint32_t BUF50M:1;
3127	uint32_t BUF49M:1;
3128	uint32_t BUF48M:1;
3129	uint32_t BUF47M:1;
3130	uint32_t BUF46M:1;
3131	uint32_t BUF45M:1;
3132	uint32_t BUF44M:1;
3133	uint32_t BUF43M:1;
3134	uint32_t BUF42M:1;
3135	uint32_t BUF41M:1;
3136	uint32_t BUF40M:1;
3137	uint32_t BUF39M:1;
3138	uint32_t BUF38M:1;
3139	uint32_t BUF37M:1;
3140	uint32_t BUF36M:1;
3141	uint32_t BUF35M:1;
3142	uint32_t BUF34M:1;
3143	uint32_t BUF33M:1;
3144	uint32_t BUF32M:1;
3145	} B;
3146	} IMRH; /* Interruput Masks Register */
3147
3148	union {
3149	uint32_t R;
3150	struct {
3151	uint32_t BUF31M:1;
3152	uint32_t BUF30M:1;
3153	uint32_t BUF29M:1;
3154	uint32_t BUF28M:1;
3155	uint32_t BUF27M:1;
3156	uint32_t BUF26M:1;
3157	uint32_t BUF25M:1;
3158	uint32_t BUF24M:1;
3159	uint32_t BUF23M:1;
3160	uint32_t BUF22M:1;
3161	uint32_t BUF21M:1;
3162	uint32_t BUF20M:1;
3163	uint32_t BUF19M:1;
3164	uint32_t BUF18M:1;
3165	uint32_t BUF17M:1;
3166	uint32_t BUF16M:1;
3167	uint32_t BUF15M:1;
3168	uint32_t BUF14M:1;
3169	uint32_t BUF13M:1;
3170	uint32_t BUF12M:1;
3171	uint32_t BUF11M:1;
3172	uint32_t BUF10M:1;
3173	uint32_t BUF09M:1;
3174	uint32_t BUF08M:1;
3175	uint32_t BUF07M:1;
3176	uint32_t BUF06M:1;
3177	uint32_t BUF05M:1;
3178	uint32_t BUF04M:1;
3179	uint32_t BUF03M:1;
3180	uint32_t BUF02M:1;
3181	uint32_t BUF01M:1;
3182	uint32_t BUF00M:1;
3183	} B;
3184	} IMRL; /* Interruput Masks Register */
3185
3186	union {
3187	uint32_t R;
3188	struct {
3189	uint32_t BUF63I:1;
3190	uint32_t BUF62I:1;
3191	uint32_t BUF61I:1;
3192	uint32_t BUF60I:1;
3193	uint32_t BUF59I:1;
3194	uint32_t BUF58I:1;
3195	uint32_t BUF57I:1;
3196	uint32_t BUF56I:1;
3197	uint32_t BUF55I:1;
3198	uint32_t BUF54I:1;
3199	uint32_t BUF53I:1;
3200	uint32_t BUF52I:1;
3201	uint32_t BUF51I:1;
3202	uint32_t BUF50I:1;
3203	uint32_t BUF49I:1;
3204	uint32_t BUF48I:1;
3205	uint32_t BUF47I:1;
3206	uint32_t BUF46I:1;
3207	uint32_t BUF45I:1;
3208	uint32_t BUF44I:1;
3209	uint32_t BUF43I:1;
3210	uint32_t BUF42I:1;
3211	uint32_t BUF41I:1;
3212	uint32_t BUF40I:1;
3213	uint32_t BUF39I:1;
3214	uint32_t BUF38I:1;
3215	uint32_t BUF37I:1;
3216	uint32_t BUF36I:1;
3217	uint32_t BUF35I:1;
3218	uint32_t BUF34I:1;
3219	uint32_t BUF33I:1;
3220	uint32_t BUF32I:1;
3221	} B;
3222	} IFRH; /* Interruput Flag Register */
3223
3224	union {
3225	uint32_t R;
3226	struct {
3227	uint32_t BUF31I:1;
3228	uint32_t BUF30I:1;
3229	uint32_t BUF29I:1;
3230	uint32_t BUF28I:1;
3231	uint32_t BUF27I:1;
3232	uint32_t BUF26I:1;
3233	uint32_t BUF25I:1;
3234	uint32_t BUF24I:1;
3235	uint32_t BUF23I:1;
3236	uint32_t BUF22I:1;
3237	uint32_t BUF21I:1;
3238	uint32_t BUF20I:1;
3239	uint32_t BUF19I:1;
3240	uint32_t BUF18I:1;
3241	uint32_t BUF17I:1;
3242	uint32_t BUF16I:1;
3243	uint32_t BUF15I:1;
3244	uint32_t BUF14I:1;
3245	uint32_t BUF13I:1;
3246	uint32_t BUF12I:1;
3247	uint32_t BUF11I:1;
3248	uint32_t BUF10I:1;
3249	uint32_t BUF09I:1;
3250	uint32_t BUF08I:1;
3251	uint32_t BUF07I:1;
3252	uint32_t BUF06I:1;
3253	uint32_t BUF05I:1;
3254	uint32_t BUF04I:1;
3255	uint32_t BUF03I:1;
3256	uint32_t BUF02I:1;
3257	uint32_t BUF01I:1;
3258	uint32_t BUF00I:1;
3259	} B;
3260	} IFRL; /* Interruput Flag Register */
3261
3262	uint32_t flexcan2_reserved2[19];
3263
3264	struct canbuf_t {
3265	union {
3266	uint32_t R;
3267	struct {
3268	uint32_t:4;
3269	uint32_t CODE:4;
3270	uint32_t:1;
3271	uint32_t SRR:1;
3272	uint32_t IDE:1;
3273	uint32_t RTR:1;
3274	uint32_t LENGTH:4;
3275	uint32_t TIMESTAMP:16;
3276	} B;
3277	} CS;
3278
3279	union {
3280	uint32_t R;
3281	struct {
3282	uint32_t:3;
3283	uint32_t STD_ID:11;
3284	uint32_t EXT_ID:18;
3285	} B;
3286	} ID;
3287
3288	union {
3289	uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
3290	uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
3291	uint32_t W[2]; /* Data buffer in words (32 bits) */
3292	uint32_t R[2]; /* Data buffer in words (32 bits) */
3293	} DATA;
3294
3295	} BUF[64];
3296	};
3297
3298	/* Define memories */
3299
3300	#define SRAM_START 0x40000000
3301	#define SRAM_SIZE 0x10000
3302	#define SRAM_END 0x4000FFFF
3303
3304	#define FLASH_START 0x0
3305	#define FLASH_SIZE 0x200000
3306	#define FLASH_END 0x1FFFFF
3307
3308	/* Define instances of modules */
3309	#define PBRIDGE_A ((volatile struct PBRIDGE_A_tag ) 0xC3F00000)
3310	#define FMPLL ((volatile struct FMPLL_tag ) 0xC3F80000)
3311	#define EBI ((volatile struct EBI_tag ) 0xC3F84000)
3312	#define FLASH ((volatile struct FLASH_tag ) 0xC3F88000)
3313	#define SIU ((volatile struct SIU_tag ) 0xC3F90000)
3314
3315	#define EMIOS ((volatile struct EMIOS_tag ) 0xC3FA0000)
3316	#define ETPU ((volatile struct ETPU_tag ) 0xC3FC0000)
3317	#define ETPU_DATA_RAM (( uint32_t ) 0xC3FC8000)
3318	#define ETPU_DATA_RAM_EXT (( uint32_t ) 0xC3FCC000)
3319	#define ETPU_DATA_RAM_END 0xC3FC8BFC
3320	#define CODE_RAM (( uint32_t ) 0xC3FD0000)
3321	#define ETPU_CODE_RAM (( uint32_t ) 0xC3FD0000)
3322
3323	#define PBRIDGE_B ((volatile struct PBRIDGE_B_tag ) 0xFFF00000)
3324	#define XBAR ((volatile struct XBAR_tag ) 0xFFF04000)
3325	#define ECSM ((volatile struct ECSM_tag ) 0xFFF40000)
3326	#define EDMA ((volatile struct EDMA_tag ) 0xFFF44000)
3327	#define INTC ((volatile struct INTC_tag ) 0xFFF48000)
3328
3329	#define EQADC ((volatile struct EQADC_tag ) 0xFFF80000)
3330
3331	#define DSPI_A ((volatile struct DSPI_tag ) 0xFFF90000)
3332	#define DSPI_B ((volatile struct DSPI_tag ) 0xFFF94000)
3333	#define DSPI_C ((volatile struct DSPI_tag ) 0xFFF98000)
3334	#define DSPI_D ((volatile struct DSPI_tag ) 0xFFF9C000)
3335
3336	#define ESCI_A ((volatile struct ESCI_tag ) 0xFFFB0000)
3337	#define ESCI_B ((volatile struct ESCI_tag ) 0xFFFB4000)
3338
3339	#define CAN_A ((volatile struct FLEXCAN2_tag ) 0xFFFC0000)
3340	#define CAN_B ((volatile struct FLEXCAN2_tag ) 0xFFFC4000)
3341	#define CAN_C ((volatile struct FLEXCAN2_tag ) 0xFFFC8000)
3342
3343	#ifdef __MWERKS__
3344	#pragma pop
3345	#endif
3346
3347	#ifdef __cplusplus
3348	}
3349	#endif
3350	#endif /* ifdef _MPC5554_H */
3351	/*********************************************************************
3352	*
3353	* Copyright:
3354	* Freescale Semiconductor, INC. All Rights Reserved.
3355	* You are hereby granted a copyright license to use, modify, and
3356	* distribute the SOFTWARE so long as this entire notice is
3357	* retained without alteration in any modified and/or redistributed
3358	* versions, and that such modified versions are clearly identified
3359	* as such. No licenses are granted by implication, estoppel or
3360	* otherwise under any patents or trademarks of Freescale
3361	* Semiconductor, Inc. This software is provided on an "AS IS"
3362	* basis and without warranty.
3363	*
3364	* To the maximum extent permitted by applicable law, Freescale
3365	* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
3366	* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
3367	* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
3368	* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
3369	* AND ANY ACCOMPANYING WRITTEN MATERIALS.
3370	*
3371	* To the maximum extent permitted by applicable law, IN NO EVENT
3372	* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
3373	* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
3374	* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
3375	* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
3376	*
3377	* Freescale Semiconductor assumes no responsibility for the
3378	* maintenance and support of this software
3379	*
3380	********************************************************************/

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source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h @ 97fa2f1b

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