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source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h @ 3ac2bf5e

4.115

Last change on this file since 3ac2bf5e was 3ac2bf5e, checked in by Sebastian Huber <sebastian.huber@…>, on 09/01/11 at 08:15:10

2011-09-01 Sebastian Huber <sebastian.huber@…>

mpc55xx/include/fsl-mpc551x.h: Use legacy register naming.

Property mode set to 100644

File size: 128.3 KB

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1	/*
2	* Modifications of the original file provided by Freescale are:
3	*
4	* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
5	*
6	* embedded brains GmbH
7	* Obere Lagerstr. 30
8	* 82178 Puchheim
9	* Germany
10	* <info@embedded-brains.de>
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	*
21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32	*/
33
34	/**************************************************************************/
35	/* FILE NAME: mpc5510.h COPYRIGHT (c) Freescale 2008 */
36	/* REVISION: 2.2 All Rights Reserved */
37	/* */
38	/* DESCRIPTION: */
39	/* This file contain all of the register and bit field definitions for */
40	/* MPC5510. */
41	/**************************************************************************/
42	/>>>>NOTE! this file is auto-generated please do not edit it!<<<</
43
44	/*************************************************/
45	/* Example register & bit field write: */
46	/* */
47	/* <MODULE>.<REGISTER>.B.<BIT> = 1; */
48	/* <MODULE>.<REGISTER>.R = 0x10000000; */
49	/* */
50	/*************************************************/
51
52	#ifndef _MPC5510_H_
53	#define _MPC5510_H_
54
55	#include <stdint.h>
56
57	#include <mpc55xx/regs-edma.h>
58
59	#ifdef __cplusplus
60	extern "C" {
61	#endif
62
63	#ifdef __MWERKS__
64	#pragma push
65	#pragma ANSI_strict off
66	#endif
67
68	/****************************************************************************/
69	/* MODULE : CRP */
70	/****************************************************************************/
71	struct CRP_tag {
72
73	union {
74	uint32_t R;
75	struct {
76	uint32_t:12;
77	uint32_t IRC32KEN:1;
78	uint32_t XOSCEN:1;
79	uint32_t:1;
80	uint32_t OSC32KEN:1;
81	uint32_t TRIM32IRC:8;
82	uint32_t TRIMIRC:8;
83	} B;
84	} CLKSRC; /* Clock Source Register */
85
86	uint32_t crp_reserved1[3];
87
88	union {
89	uint32_t R;
90	struct {
91	uint32_t CNTEN:1;
92	uint32_t RTCIE:1;
93	uint32_t RTCF:1;
94	uint32_t ROVRF:1;
95	uint32_t RTCVAL:12;
96	uint32_t APIEN:1;
97	uint32_t APIIE:1;
98	uint32_t APIF:1;
99	uint32_t CLKSEL:2;
100	uint32_t ROVREN:1;
101	uint32_t APIVAL:10;
102	} B;
103	} RTCSC; /* RTC Status and Control Register */
104
105	union {
106	uint32_t R;
107	struct {
108	uint32_t RTCCNT:32;
109	} B;
110	} RTCCNT; /* RTC Counter Register */
111
112	uint32_t crp_reserved2[10];
113
114	union {
115	uint32_t R;
116	struct {
117	uint32_t:1;
118	uint32_t WKPSEL7:3;
119	uint32_t:1;
120	uint32_t WKPSEL6:3;
121	uint32_t:1;
122	uint32_t WKPSEL5:3;
123	uint32_t:1;
124	uint32_t WKPSEL4:3;
125	uint32_t:1;
126	uint32_t WKPSEL3:3;
127	uint32_t:1;
128	uint32_t WKPSEL2:3;
129	uint32_t:1;
130	uint32_t WKPSEL1:3;
131	uint32_t:1;
132	uint32_t WKPSEL0:3;
133	} B;
134	} WKPINSEL; /* Wakeup Pin Source Select Register */
135
136	union {
137	uint32_t R;
138	struct {
139	uint32_t WKPDET7:2;
140	uint32_t WKPDET6:2;
141	uint32_t WKPDET5:2;
142	uint32_t WKPDET4:2;
143	uint32_t WKPDET3:2;
144	uint32_t WKPDET2:2;
145	uint32_t WKPDET1:2;
146	uint32_t WKPDET0:2;
147	uint32_t:5;
148	uint32_t RTCOVREN:1;
149	uint32_t RTCWKEN:1;
150	uint32_t APIWKEN:1;
151	uint32_t:7;
152	uint32_t WKCLKSEL:1;
153	} B;
154	} WKSE; /* Wakeup Source Enable Register */
155
156	uint32_t crp_reserved3[2];
157
158	union {
159	uint32_t R;
160	struct {
161	uint32_t Z1VEC:30;
162	uint32_t Z1RST:1;
163	uint32_t VLE:1;
164	} B;
165	} Z1VEC; /* Z1 Reset Vector Register */
166
167	union {
168	uint32_t R;
169	struct {
170	uint32_t Z0VEC:30;
171	uint32_t Z0RST:1;
172	uint32_t:1;
173	} B;
174	} Z0VEC; /* Z0 Reset Vector Register */
175
176	union {
177	uint32_t R;
178	struct {
179	uint32_t RECPTR:30;
180	uint32_t FASTREC:1;
181	uint32_t:1;
182	} B;
183	} RECPTR; /* Reset Recovery Pointer Register */
184
185	uint32_t crp_reserved4;
186
187	union {
188	uint32_t R;
189	struct {
190	uint32_t SLEEPF:1;
191	uint32_t STOPF:1;
192	uint32_t:3;
193	uint32_t WKRLLOVRF:1;
194	uint32_t WKAPIF:1;
195	uint32_t WKRTCF:1;
196	uint32_t PWKSCRF:8;
197	uint32_t SLEEP:1;
198	uint32_t STOP:1;
199	uint32_t:1;
200	uint32_t PKREL:1;
201	uint32_t SLP12EN:1;
202	uint32_t RAMSEL:3;
203	uint32_t PWKSRIE:8;
204	} B;
205	} PSCR; /* Power Status and Control Register */
206
207	uint32_t crp_reserved5[3];
208
209	union {
210	uint32_t R;
211	struct {
212	uint32_t LVI5IE:1;
213	uint32_t LVI5HIE:1;
214	uint32_t LVI5F:1;
215	uint32_t LVI5HF:1;
216	uint32_t LVI5LOCK:1;
217	uint32_t LVI5RE:1;
218	uint32_t:9;
219	uint32_t BYPDIS:1;
220	uint32_t:16;
221	} B;
222	} SOCSC; /* LVI Status and Control Register */
223
224	};
225	/****************************************************************************/
226	/* MODULE : DMAMUX */
227	/****************************************************************************/
228	struct DMAMUX_tag {
229	union {
230	uint8_t R;
231	struct {
232	uint8_t ENBL:1;
233	uint8_t TRIG:1;
234	uint8_t SOURCE:6;
235	} B;
236	} CHCONFIG[16]; /* DMA Channel Configuration Register */
237
238	};
239	/****************************************************************************/
240	/* MODULE : DSPI */
241	/****************************************************************************/
242	struct DSPI_tag {
243	union DSPI_MCR_tag {
244	uint32_t R;
245	struct {
246	uint32_t MSTR:1;
247	uint32_t CONT_SCKE:1;
248	uint32_t DCONF:2;
249	uint32_t FRZ:1;
250	uint32_t MTFE:1;
251	uint32_t PCSSE:1;
252	uint32_t ROOE:1;
253	uint32_t:2;
254	uint32_t PCSIS5:1;
255	uint32_t PCSIS4:1;
256	uint32_t PCSIS3:1;
257	uint32_t PCSIS2:1;
258	uint32_t PCSIS1:1;
259	uint32_t PCSIS0:1;
260	uint32_t:1;
261	uint32_t MDIS:1;
262	uint32_t DIS_TXF:1;
263	uint32_t DIS_RXF:1;
264	uint32_t CLR_TXF:1;
265	uint32_t CLR_RXF:1;
266	uint32_t SMPL_PT:2;
267	uint32_t:7;
268	uint32_t HALT:1;
269	} B;
270	} MCR; /* Module Configuration Register */
271
272	uint32_t dspi_reserved1;
273
274	union {
275	uint32_t R;
276	struct {
277	uint32_t SPI_TCNT:16;
278	uint32_t:16;
279	} B;
280	} TCR;
281
282	union DSPI_CTAR_tag {
283	uint32_t R;
284	struct {
285	uint32_t DBR:1;
286	uint32_t FMSZ:4;
287	uint32_t CPOL:1;
288	uint32_t CPHA:1;
289	uint32_t LSBFE:1;
290	uint32_t PCSSCK:2;
291	uint32_t PASC:2;
292	uint32_t PDT:2;
293	uint32_t PBR:2;
294	uint32_t CSSCK:4;
295	uint32_t ASC:4;
296	uint32_t DT:4;
297	uint32_t BR:4;
298	} B;
299	} CTAR[8]; /* Clock and Transfer Attributes Registers */
300
301	union DSPI_SR_tag {
302	uint32_t R;
303	struct {
304	uint32_t TCF:1;
305	uint32_t TXRXS:1;
306	uint32_t:1;
307	uint32_t EOQF:1;
308	uint32_t TFUF:1;
309	uint32_t:1;
310	uint32_t TFFF:1;
311	uint32_t:5;
312	uint32_t RFOF:1;
313	uint32_t:1;
314	uint32_t RFDF:1;
315	uint32_t:1;
316	uint32_t TXCTR:4;
317	uint32_t TXNXTPTR:4;
318	uint32_t RXCTR:4;
319	uint32_t POPNXTPTR:4;
320	} B;
321	} SR; /* Status Register */
322
323	union DSPI_RSER_tag {
324	uint32_t R;
325	struct {
326	uint32_t TCF_RE:1;
327	uint32_t:2;
328	uint32_t EOQFRE:1;
329	uint32_t TFUFRE:1;
330	uint32_t:1;
331	uint32_t TFFFRE:1;
332	uint32_t TFFFDIRS:1;
333	uint32_t:4;
334	uint32_t RFOFRE:1;
335	uint32_t:1;
336	uint32_t RFDFRE:1;
337	uint32_t RFDFDIRS:1;
338	uint32_t:16;
339	} B;
340	} RSER; /* DMA/Interrupt Request Select and Enable Register */
341
342	union DSPI_PUSHR_tag {
343	uint32_t R;
344	struct {
345	uint32_t CONT:1;
346	uint32_t CTAS:3;
347	uint32_t EOQ:1;
348	uint32_t CTCNT:1;
349	uint32_t:4;
350	uint32_t PCS5:1;
351	uint32_t PCS4:1;
352	uint32_t PCS3:1;
353	uint32_t PCS2:1;
354	uint32_t PCS1:1;
355	uint32_t PCS0:1;
356	uint32_t TXDATA:16;
357	} B;
358	} PUSHR; /* PUSH TX FIFO Register */
359
360	union DSPI_POPR_tag {
361	uint32_t R;
362	struct {
363	uint32_t:16;
364	uint32_t RXDATA:16;
365	} B;
366	} POPR; /* POP RX FIFO Register */
367
368	union {
369	uint32_t R;
370	struct {
371	uint32_t TXCMD:16;
372	uint32_t TXDATA:16;
373	} B;
374	} TXFR[4]; /* Transmit FIFO Registers */
375
376	uint32_t DSPI_reserved_txf[12];
377
378	union {
379	uint32_t R;
380	struct {
381	uint32_t:16;
382	uint32_t RXDATA:16;
383	} B;
384	} RXFR[4]; /* Transmit FIFO Registers */
385
386	uint32_t DSPI_reserved_rxf[12];
387
388	union {
389	uint32_t R;
390	struct {
391	uint32_t:12;
392	uint32_t TXSS:1;
393	uint32_t:2;
394	uint32_t CID:1;
395	uint32_t DCONT:1;
396	uint32_t DSICTAS:3;
397	uint32_t:6;
398	uint32_t DPCS5:1;
399	uint32_t DPCS4:1;
400	uint32_t DPCS3:1;
401	uint32_t DPCS2:1;
402	uint32_t DPCS1:1;
403	uint32_t DPCS0:1;
404	} B;
405	} DSICR; /* DSI Configuration Register */
406
407	union {
408	uint32_t R;
409	struct {
410	uint32_t:16;
411	uint32_t SER_DATA:16;
412	} B;
413	} SDR; /* DSI Serialization Data Register */
414
415	union {
416	uint32_t R;
417	struct {
418	uint32_t:16;
419	uint32_t ASER_DATA:16;
420	} B;
421	} ASDR; /* DSI Alternate Serialization Data Register */
422
423	union {
424	uint32_t R;
425	struct {
426	uint32_t:16;
427	uint32_t COMP_DATA:16;
428	} B;
429	} COMPR; /* DSI Transmit Comparison Register */
430
431	union {
432	uint32_t R;
433	struct {
434	uint32_t:16;
435	uint32_t DESER_DATA:16;
436	} B;
437	} DDR; /* DSI deserialization Data Register */
438
439	};
440	/****************************************************************************/
441	/* MODULE : External Bus Interface (EBI) */
442	/****************************************************************************/
443
444	/* CS_tag instantiated within EBI_tag */
445	struct EBI_CS_tag {
446	union { /* Base Register Bank */
447	uint32_t R;
448	struct {
449	uint32_t BA:17;
450	uint32_t:3;
451	uint32_t PS:1;
452	uint32_t:3;
453	uint32_t AD_MUX:1;
454	uint32_t BL:1;
455	uint32_t WEBS:1;
456	uint32_t TBDIP:1;
457	uint32_t:1;
458	uint32_t SETA:1;
459	uint32_t BI:1;
460	uint32_t V:1;
461	} B;
462	} BR;
463
464	union { /* Option Register Bank */
465	uint32_t R;
466	struct {
467	uint32_t AM:17;
468	uint32_t:7;
469	uint32_t SCY:4;
470	uint32_t:1;
471	uint32_t BSCY:2;
472	uint32_t:1;
473	} B;
474	} OR;
475	};
476
477	struct EBI_CAL_CS_tag {
478	uint32_t ebi_cal_cs_reserved [2];
479	};
480
481	struct EBI_tag {
482	union { /* Module Configuration Register */
483	uint32_t R;
484	struct {
485	uint32_t:16;
486	uint32_t ACGE:1;
487	uint32_t EXTM:1;
488	uint32_t EARB:1;
489	uint32_t:6;
490	uint32_t MDIS:1;
491	uint32_t:3;
492	uint32_t D16_31:1;
493	uint32_t AD_MUX:1;
494	uint32_t DBM:1;
495	} B;
496	} MCR;
497
498	uint32_t EBI_reserved1;
499
500	union { /* Transfer Error Status Register */
501	uint32_t R;
502	struct {
503	uint32_t:30;
504	uint32_t TEAF:1;
505	uint32_t BMTF:1;
506	} B;
507	} TESR;
508
509	union { /* Bus Monitor Control Register */
510	uint32_t R;
511	struct {
512	uint32_t:16;
513	uint32_t BMT:8;
514	uint32_t BME:1;
515	uint32_t:7;
516	} B;
517	} BMCR;
518
519	/* Roll in 3x CS registers */
520	struct EBI_CS_tag CS[4];
521
522	uint32_t EBI_reserved2[4];
523
524	struct EBI_CAL_CS_tag CAL_CS[4];
525	};
526	/****************************************************************************/
527	/* MODULE : EMIOS */
528	/****************************************************************************/
529	struct EMIOS_tag {
530	union EMIOS_MCR_tag {
531	uint32_t R;
532	struct {
533	uint32_t:1;
534	uint32_t MDIS:1;
535	uint32_t FRZ:1;
536	uint32_t GTBE:1;
537	uint32_t:1;
538	uint32_t GPREN:1;
539	uint32_t:10;
540	uint32_t GPRE:8;
541	uint32_t:8;
542	} B;
543	} MCR; /* Module Configuration Register */
544
545	union {
546	uint32_t R;
547	struct {
548	uint32_t:8;
549	uint32_t F23:1;
550	uint32_t F22:1;
551	uint32_t F21:1;
552	uint32_t F20:1;
553	uint32_t F19:1;
554	uint32_t F18:1;
555	uint32_t F17:1;
556	uint32_t F16:1;
557	uint32_t F15:1;
558	uint32_t F14:1;
559	uint32_t F13:1;
560	uint32_t F12:1;
561	uint32_t F11:1;
562	uint32_t F10:1;
563	uint32_t F9:1;
564	uint32_t F8:1;
565	uint32_t F7:1;
566	uint32_t F6:1;
567	uint32_t F5:1;
568	uint32_t F4:1;
569	uint32_t F3:1;
570	uint32_t F2:1;
571	uint32_t F1:1;
572	uint32_t F0:1;
573	} B;
574	} GFG; /* Global FLAG Register */
575
576	union {
577	uint32_t R;
578	struct {
579	uint32_t:8;
580	uint32_t OU23:1;
581	uint32_t OU22:1;
582	uint32_t OU21:1;
583	uint32_t OU20:1;
584	uint32_t OU19:1;
585	uint32_t OU18:1;
586	uint32_t OU17:1;
587	uint32_t OU16:1;
588	uint32_t OU15:1;
589	uint32_t OU14:1;
590	uint32_t OU13:1;
591	uint32_t OU12:1;
592	uint32_t OU11:1;
593	uint32_t OU10:1;
594	uint32_t OU9:1;
595	uint32_t OU8:1;
596	uint32_t OU7:1;
597	uint32_t OU6:1;
598	uint32_t OU5:1;
599	uint32_t OU4:1;
600	uint32_t OU3:1;
601	uint32_t OU2:1;
602	uint32_t OU1:1;
603	uint32_t OU0:1;
604	} B;
605	} OUDR; /* Output Update Disable Register */
606
607	union {
608	uint32_t R;
609	struct {
610	uint32_t:8;
611	uint32_t UC23:1;
612	uint32_t UC22:1;
613	uint32_t UC21:1;
614	uint32_t UC20:1;
615	uint32_t UC19:1;
616	uint32_t UC18:1;
617	uint32_t UC17:1;
618	uint32_t UC16:1;
619	uint32_t UC15:1;
620	uint32_t UC14:1;
621	uint32_t UC13:1;
622	uint32_t UC12:1;
623	uint32_t UC11:1;
624	uint32_t UC10:1;
625	uint32_t UC9:1;
626	uint32_t UC8:1;
627	uint32_t UC7:1;
628	uint32_t UC6:1;
629	uint32_t UC5:1;
630	uint32_t UC4:1;
631	uint32_t UC3:1;
632	uint32_t UC2:1;
633	uint32_t UC1:1;
634	uint32_t UC0:1;
635	} B;
636	} UCDIS; /* Disable Channel Register */
637
638	uint32_t emios_reserved1[4];
639
640	struct EMIOS_CH_tag {
641	union {
642	uint32_t R;
643	struct {
644	uint32_t:16;
645	uint32_t A:16; /* Channel A Data Register */
646	} B;
647	} CADR;
648
649	union {
650	uint32_t R;
651	struct {
652	uint32_t:16;
653	uint32_t B:16; /* Channel B Data Register */
654	} B;
655	} CBDR;
656
657	union {
658	uint32_t R; /* Channel Counter Register */
659	struct {
660	uint32_t:16;
661	uint32_t C:16; /* Channel C Data Register */
662	} B;
663	} CCNTR;
664
665	union EMIOS_CCR_tag {
666	uint32_t R;
667	struct {
668	uint32_t FREN:1;
669	uint32_t ODIS:1;
670	uint32_t ODISSL:2;
671	uint32_t UCPRE:2;
672	uint32_t UCPREN:1;
673	uint32_t DMA:1;
674	uint32_t:1;
675	uint32_t IF:4;
676	uint32_t FCK:1;
677	uint32_t FEN:1;
678	uint32_t:3;
679	uint32_t FORCMA:1;
680	uint32_t FORCMB:1;
681	uint32_t:1;
682	uint32_t BSL:2;
683	uint32_t EDSEL:1;
684	uint32_t EDPOL:1;
685	uint32_t MODE:7;
686	} B;
687	} CCR; /* Channel Control Register */
688
689	union EMIOS_CSR_tag {
690	uint32_t R;
691	struct {
692	uint32_t OVR:1;
693	uint32_t:15;
694	uint32_t OVFL:1;
695	uint32_t:12;
696	uint32_t UCIN:1;
697	uint32_t UCOUT:1;
698	uint32_t FLAG:1;
699	} B;
700	} CSR; /* Channel Status Register */
701
702	union {
703	uint32_t R; /* Alternate Channel A Data Register */
704	} ALTA;
705
706	uint32_t emios_channel_reserved[2];
707
708	} CH[24];
709
710	};
711	/****************************************************************************/
712	/* MODULE : EQADC */
713	/****************************************************************************/
714	struct EQADC_tag {
715	union {
716	uint32_t R;
717	struct {
718	uint32_t:30;
719	uint32_t DBG:2;
720	} B;
721	} MCR; /* Module Configuration Register */
722
723	uint32_t eqadc_reserved0;
724
725	union {
726	uint32_t R;
727	struct {
728	uint32_t:6;
729	uint32_t NMF:26;
730	} B;
731	} NMSFR; /* Null Message Send Format Register */
732
733	union {
734	uint32_t R;
735	struct {
736	uint32_t:28;
737	uint32_t DFL:4;
738	} B;
739	} ETDFR; /* External Trigger Digital Filter Register */
740
741	union {
742	uint32_t R;
743	struct {
744	uint32_t CF_PUSH:32;
745	} B;
746	} CFPR[6]; /* CFIFO Push Registers */
747
748	uint32_t eqadc_reserved1;
749
750	uint32_t eqadc_reserved2;
751
752	union {
753	uint32_t R;
754	struct {
755	uint32_t:16;
756	uint32_t RF_POP:16;
757	} B;
758	} RFPR[6]; /* Result FIFO Pop Registers */
759
760	uint32_t eqadc_reserved3;
761
762	uint32_t eqadc_reserved4;
763
764	union {
765	uint16_t R;
766	struct {
767	uint16_t:5;
768	uint16_t SSE:1;
769	uint16_t CFINV:1;
770	uint16_t:1;
771	uint16_t MODE:4;
772	uint16_t:4;
773	} B;
774	} CFCR[6]; /* CFIFO Control Registers */
775
776	uint32_t eqadc_reserved5;
777
778	union {
779	uint16_t R;
780	struct {
781	uint16_t NCIE:1;
782	uint16_t TORIE:1;
783	uint16_t PIE:1;
784	uint16_t EOQIE:1;
785	uint16_t CFUIE:1;
786	uint16_t:1;
787	uint16_t CFFE:1;
788	uint16_t CFFS:1;
789	uint16_t:4;
790	uint16_t RFOIE:1;
791	uint16_t:1;
792	uint16_t RFDE:1;
793	uint16_t RFDS:1;
794	} B;
795	} IDCR[6]; /* Interrupt and DMA Control Registers */
796
797	uint32_t eqadc_reserved6;
798
799	union {
800	uint32_t R;
801	struct {
802	uint32_t NCF:1;
803	uint32_t TORF:1;
804	uint32_t PF:1;
805	uint32_t EOQF:1;
806	uint32_t CFUF:1;
807	uint32_t SSS:1;
808	uint32_t CFFF:1;
809	uint32_t:5;
810	uint32_t RFOF:1;
811	uint32_t:1;
812	uint32_t RFDF:1;
813	uint32_t:1;
814	uint32_t CFCTR:4;
815	uint32_t TNXTPTR:4;
816	uint32_t RFCTR:4;
817	uint32_t POPNXTPTR:4;
818	} B;
819	} FISR[6]; /* FIFO and Interrupt Status Registers */
820
821	uint32_t eqadc_reserved7;
822
823	uint32_t eqadc_reserved8;
824
825	union {
826	uint16_t R;
827	struct {
828	uint16_t:5;
829	uint16_t TC_CF:11;
830	} B;
831	} CFTCR[6]; /* CFIFO Transfer Counter Registers */
832
833	uint32_t eqadc_reserved9;
834
835	union {
836	uint32_t R;
837	struct {
838	uint32_t CFS0_T0:2;
839	uint32_t CFS1_T0:2;
840	uint32_t CFS2_T0:2;
841	uint32_t CFS3_T0:2;
842	uint32_t CFS4_T0:2;
843	uint32_t CFS5_T0:2;
844	uint32_t:5;
845	uint32_t LCFT0:4;
846	uint32_t TC_LCFT0:11;
847	} B;
848	} CFSSR0; /* CFIFO Status Register 0 */
849
850	uint32_t eqadc_reserved10[2];
851
852	union {
853	uint32_t R;
854	struct {
855	uint32_t CFS0:2;
856	uint32_t CFS1:2;
857	uint32_t CFS2:2;
858	uint32_t CFS3:2;
859	uint32_t CFS4:2;
860	uint32_t CFS5:2;
861	uint32_t:20;
862	} B;
863	} CFSR;
864
865	uint32_t eqadc_reserved11[20];
866
867	struct {
868	union {
869	uint32_t R;
870	struct {
871	uint32_t:32;
872	} B;
873	} R[4];
874
875	uint32_t eqadc_reserved12[12];
876
877	} CF[6];
878
879	uint32_t eqadc_reserved13[32];
880
881	struct {
882	union {
883	uint32_t R;
884	struct {
885	uint32_t:32;
886	} B;
887	} R[4];
888
889	uint32_t eqadc_reserved14[12];
890
891	} RF[6];
892
893	};
894	/****************************************************************************/
895	/* MODULE : eSCI */
896	/****************************************************************************/
897	struct ESCI_tag {
898	union ESCI_CR1_tag {
899	uint32_t R;
900	struct {
901	uint32_t:3;
902	uint32_t SBR:13;
903	uint32_t LOOPS:1;
904	uint32_t:1;
905	uint32_t RSRC:1;
906	uint32_t M:1;
907	uint32_t WAKE:1;
908	uint32_t ILT:1;
909	uint32_t PE:1;
910	uint32_t PT:1;
911	uint32_t TIE:1;
912	uint32_t TCIE:1;
913	uint32_t RIE:1;
914	uint32_t ILIE:1;
915	uint32_t TE:1;
916	uint32_t RE:1;
917	uint32_t RWU:1;
918	uint32_t SBK:1;
919	} B;
920	} CR1; /* Control Register 1 */
921
922	union ESCI_CR2_tag {
923	uint16_t R;
924	struct {
925	uint16_t MDIS:1;
926	uint16_t FBR:1;
927	uint16_t BSTP:1;
928	uint16_t IEBERR:1;
929	uint16_t RXDMA:1;
930	uint16_t TXDMA:1;
931	uint16_t BRK13:1;
932	uint16_t TXDIR:1;
933	uint16_t BESM13:1;
934	uint16_t SBSTP:1;
935	uint16_t:1;
936	uint16_t PMSK:1;
937	uint16_t ORIE:1;
938	uint16_t NFIE:1;
939	uint16_t FEIE:1;
940	uint16_t PFIE:1;
941	} B;
942	} CR2; /* Control Register 2 */
943
944	union ESCI_DR_tag {
945	uint16_t R;
946	struct {
947	uint16_t R8:1;
948	uint16_t T8:1;
949	uint16_t:6;
950	uint8_t D;
951	} B;
952	} DR; /* Data Register */
953
954	union ESCI_SR_tag {
955	uint32_t R;
956	struct {
957	uint32_t TDRE:1;
958	uint32_t TC:1;
959	uint32_t RDRF:1;
960	uint32_t IDLE:1;
961	uint32_t OR:1;
962	uint32_t NF:1;
963	uint32_t FE:1;
964	uint32_t PF:1;
965	uint32_t:3;
966	uint32_t BERR:1;
967	uint32_t:3;
968	uint32_t RAF:1;
969	uint32_t RXRDY:1;
970	uint32_t TXRDY:1;
971	uint32_t LWAKE:1;
972	uint32_t STO:1;
973	uint32_t PBERR:1;
974	uint32_t CERR:1;
975	uint32_t CKERR:1;
976	uint32_t FRC:1;
977	uint32_t:6;
978	uint32_t UREQ:1;
979	uint32_t OVFL:1;
980	} B;
981	} SR; /* Status Register */
982
983	union {
984	uint32_t R;
985	struct {
986	uint32_t LRES:1;
987	uint32_t WU:1;
988	uint32_t WUD0:1;
989	uint32_t WUD1:1;
990	uint32_t LDBG:1;
991	uint32_t DSF:1;
992	uint32_t PRTY:1;
993	uint32_t LIN:1;
994	uint32_t RXIE:1;
995	uint32_t TXIE:1;
996	uint32_t WUIE:1;
997	uint32_t STIE:1;
998	uint32_t PBIE:1;
999	uint32_t CIE:1;
1000	uint32_t CKIE:1;
1001	uint32_t FCIE:1;
1002	uint32_t:6;
1003	uint32_t UQIE:1;
1004	uint32_t OFIE:1;
1005	uint32_t:8;
1006	} B;
1007	} LCR; /* LIN Control Register */
1008
1009	union {
1010	uint32_t R;
1011	} LTR; /* LIN Transmit Register */
1012
1013	union {
1014	uint32_t R;
1015	} LRR; /* LIN Recieve Register */
1016
1017	union {
1018	uint32_t R;
1019	} LPR; /* LIN CRC Polynom Register */
1020
1021	};
1022	/****************************************************************************/
1023	/* MODULE : FLASH */
1024	/****************************************************************************/
1025	struct FLASH_tag {
1026	union { /* Module Configuration Register */
1027	uint32_t R;
1028	struct {
1029	uint32_t:3;
1030	uint32_t SFS:1;
1031	uint32_t SIZE:4;
1032	uint32_t:1;
1033	uint32_t LAS:3;
1034	uint32_t:3;
1035	uint32_t MAS:1;
1036	uint32_t EER:1;
1037	uint32_t RWE:1;
1038	uint32_t BBEPE:1;
1039	uint32_t EPE:1;
1040	uint32_t PEAS:1;
1041	uint32_t DONE:1;
1042	uint32_t PEG:1;
1043	uint32_t:1;
1044	uint32_t PRD:1;
1045	uint32_t STOP:1;
1046	uint32_t:1;
1047	uint32_t PGM:1;
1048	uint32_t PSUS:1;
1049	uint32_t ERS:1;
1050	uint32_t ESUS:1;
1051	uint32_t EHV:1;
1052	} B;
1053	} MCR;
1054
1055	union LMLR_tag { /* Low/Mid Address Space Block Locking Register */
1056	uint32_t R;
1057	struct {
1058	uint32_t LME:1;
1059	uint32_t:10;
1060	uint32_t SLOCK:1;
1061	uint32_t:2;
1062	uint32_t MLOCK:2;
1063	uint32_t:6;
1064	uint32_t LLOCK:10;
1065	} B;
1066	} LMLR; /* Legacy naming - refer to LML in Reference Manual */
1067
1068	union HLR_tag { /* High Address Space Block Locking Register */
1069	uint32_t R;
1070	struct {
1071	uint32_t HBE:1;
1072	uint32_t:23;
1073	uint32_t HBLOCK:8;
1074	} B;
1075	} HLR; /* Legacy naming - refer to HBL in Reference Manual */
1076
1077	union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */
1078	uint32_t R;
1079	struct {
1080	uint32_t SLE:1;
1081	uint32_t:10;
1082	uint32_t SSLOCK:1;
1083	uint32_t:2;
1084	uint32_t SMLOCK:2;
1085	uint32_t:6;
1086	uint32_t SLLOCK:10;
1087	} B;
1088	} SLMLR; /* Legacy naming - refer to SLL in Reference Manual */
1089
1090	union { /* Low/Mid Address Space Block Select Register */
1091	uint32_t R;
1092	struct {
1093	uint32_t:14;
1094	uint32_t MSEL:2;
1095	uint32_t:6;
1096	uint32_t LSEL:10;
1097	} B;
1098	} LMSR; /* Legacy naming - refer to LMS in Reference Manual */
1099
1100	union { /* High Address Space Block Select Register */
1101	uint32_t R;
1102	struct {
1103	uint32_t:28;
1104	uint32_t HBSEL:4;
1105	} B;
1106	} HSR; /* Legacy naming - refer to HBS in Reference Manual */
1107
1108	union { /* Address Register */
1109	uint32_t R;
1110	struct {
1111	uint32_t:10;
1112	uint32_t ADDR:19;
1113	uint32_t:3;
1114	} B;
1115	} AR; /* Legacy naming - refer to ADR in Reference Manual */
1116
1117	union { /* Platform Flash Configuration Register for Port 0 */
1118	uint32_t R;
1119	struct {
1120	uint32_t LBCFG:4;
1121	uint32_t ARB:1;
1122	uint32_t PRI:1;
1123	uint32_t:5;
1124	uint32_t M4PFE:1;
1125	uint32_t M3PFE:1;
1126	uint32_t M2PFE:1;
1127	uint32_t M1PFE:1;
1128	uint32_t M0PFE:1;
1129	uint32_t APC:3;
1130	uint32_t WWSC:2;
1131	uint32_t RWSC:3;
1132	uint32_t:1;
1133	uint32_t DPFEN:1;
1134	uint32_t:1;
1135	uint32_t IPFEN:1;
1136	uint32_t:1;
1137	uint32_t PFLIM:2;
1138	uint32_t BFEN:1;
1139	} B;
1140	} PFCRP0;
1141
1142	union { /* Platform Flash Configuration Register for Port 1 */
1143	uint32_t R;
1144	struct {
1145	uint32_t LBCFG:4;
1146	uint32_t:7;
1147	uint32_t M4PFE:1;
1148	uint32_t M3PFE:1;
1149	uint32_t M2PFE:1;
1150	uint32_t M1PFE:1;
1151	uint32_t M0PFE:1;
1152	uint32_t APC:3;
1153	uint32_t WWSC:2;
1154	uint32_t RWSC:3;
1155	uint32_t:1;
1156	uint32_t DPFEN:1;
1157	uint32_t:1;
1158	uint32_t IPFEN:1;
1159	uint32_t:1;
1160	uint32_t PFLIM:2;
1161	uint32_t BFEN:1;
1162	} B;
1163	} PFCRP1;
1164
1165	};
1166	/****************************************************************************/
1167	/* MODULE : FlexCAN */
1168	/****************************************************************************/
1169	struct FLEXCAN_tag {
1170	union {
1171	uint32_t R;
1172	struct {
1173	uint32_t MDIS:1;
1174	uint32_t FRZ:1;
1175	uint32_t FEN:1;
1176	uint32_t HALT:1;
1177	uint32_t NOTRDY:1;
1178	uint32_t WAKMSK:1;
1179	uint32_t SOFTRST:1;
1180	uint32_t FRZACK:1;
1181	uint32_t SUPV:1;
1182	uint32_t SLFWAK:1;
1183	uint32_t WRNEN:1;
1184	uint32_t LPMACK:1;
1185	uint32_t WAKSRC:1;
1186	uint32_t DOZE:1;
1187	uint32_t SRXDIS:1;
1188	uint32_t BCC:1;
1189	uint32_t:2;
1190	uint32_t LPRIO_EN:1;
1191	uint32_t AEN:1;
1192	uint32_t:2;
1193	uint32_t IDAM:2;
1194	uint32_t:2;
1195	uint32_t MAXMB:6;
1196	} B;
1197	} MCR; /* Module Configuration Register */
1198
1199	union {
1200	uint32_t R;
1201	struct {
1202	uint32_t PRESDIV:8;
1203	uint32_t RJW:2;
1204	uint32_t PSEG1:3;
1205	uint32_t PSEG2:3;
1206	uint32_t BOFFMSK:1;
1207	uint32_t ERRMSK:1;
1208	uint32_t CLKSRC:1;
1209	uint32_t LPB:1;
1210	uint32_t TWRNMSK:1;
1211	uint32_t RWRNMSK:1;
1212	uint32_t:2;
1213	uint32_t SMP:1;
1214	uint32_t BOFFREC:1;
1215	uint32_t TSYN:1;
1216	uint32_t LBUF:1;
1217	uint32_t LOM:1;
1218	uint32_t PROPSEG:3;
1219	} B;
1220	} CTRL; /* Control Register */
1221
1222	union {
1223	uint32_t R;
1224	} TIMER; /* Free Running Timer */
1225
1226	uint32_t FLEXCAN_reserved1;
1227
1228	union {
1229	uint32_t R;
1230	struct {
1231	uint32_t MI:32;
1232	} B;
1233	} RXGMASK; /* RX Global Mask */
1234
1235	union {
1236	uint32_t R;
1237	struct {
1238	uint32_t MI:32;
1239	} B;
1240	} RX14MASK; /* RX 14 Mask */
1241
1242	union {
1243	uint32_t R;
1244	struct {
1245	uint32_t MI:32;
1246	} B;
1247	} RX15MASK; /* RX 15 Mask */
1248
1249	union {
1250	uint32_t R;
1251	struct {
1252	uint32_t:16;
1253	uint32_t RXECNT:8;
1254	uint32_t TXECNT:8;
1255	} B;
1256	} ECR; /* Error Counter Register */
1257
1258	union {
1259	uint32_t R;
1260	struct {
1261	uint32_t:14;
1262	uint32_t TWRNINT:1;
1263	uint32_t RWRNINT:1;
1264	uint32_t BIT1ERR:1;
1265	uint32_t BIT0ERR:1;
1266	uint32_t ACKERR:1;
1267	uint32_t CRCERR:1;
1268	uint32_t FRMERR:1;
1269	uint32_t STFERR:1;
1270	uint32_t TXWRN:1;
1271	uint32_t RXWRN:1;
1272	uint32_t IDLE:1;
1273	uint32_t TXRX:1;
1274	uint32_t FLTCONF:2;
1275	uint32_t:1;
1276	uint32_t BOFFINT:1;
1277	uint32_t ERRINT:1;
1278	uint32_t WAKINT:1;
1279	} B;
1280	} ESR; /* Error and Status Register */
1281
1282	union {
1283	uint32_t R;
1284	struct {
1285	uint32_t BUF63M:1;
1286	uint32_t BUF62M:1;
1287	uint32_t BUF61M:1;
1288	uint32_t BUF60M:1;
1289	uint32_t BUF59M:1;
1290	uint32_t BUF58M:1;
1291	uint32_t BUF57M:1;
1292	uint32_t BUF56M:1;
1293	uint32_t BUF55M:1;
1294	uint32_t BUF54M:1;
1295	uint32_t BUF53M:1;
1296	uint32_t BUF52M:1;
1297	uint32_t BUF51M:1;
1298	uint32_t BUF50M:1;
1299	uint32_t BUF49M:1;
1300	uint32_t BUF48M:1;
1301	uint32_t BUF47M:1;
1302	uint32_t BUF46M:1;
1303	uint32_t BUF45M:1;
1304	uint32_t BUF44M:1;
1305	uint32_t BUF43M:1;
1306	uint32_t BUF42M:1;
1307	uint32_t BUF41M:1;
1308	uint32_t BUF40M:1;
1309	uint32_t BUF39M:1;
1310	uint32_t BUF38M:1;
1311	uint32_t BUF37M:1;
1312	uint32_t BUF36M:1;
1313	uint32_t BUF35M:1;
1314	uint32_t BUF34M:1;
1315	uint32_t BUF33M:1;
1316	uint32_t BUF32M:1;
1317	} B;
1318	} IMASK2; /* Interruput Masks Register */
1319
1320	union {
1321	uint32_t R;
1322	struct {
1323	uint32_t BUF31M:1;
1324	uint32_t BUF30M:1;
1325	uint32_t BUF29M:1;
1326	uint32_t BUF28M:1;
1327	uint32_t BUF27M:1;
1328	uint32_t BUF26M:1;
1329	uint32_t BUF25M:1;
1330	uint32_t BUF24M:1;
1331	uint32_t BUF23M:1;
1332	uint32_t BUF22M:1;
1333	uint32_t BUF21M:1;
1334	uint32_t BUF20M:1;
1335	uint32_t BUF19M:1;
1336	uint32_t BUF18M:1;
1337	uint32_t BUF17M:1;
1338	uint32_t BUF16M:1;
1339	uint32_t BUF15M:1;
1340	uint32_t BUF14M:1;
1341	uint32_t BUF13M:1;
1342	uint32_t BUF12M:1;
1343	uint32_t BUF11M:1;
1344	uint32_t BUF10M:1;
1345	uint32_t BUF09M:1;
1346	uint32_t BUF08M:1;
1347	uint32_t BUF07M:1;
1348	uint32_t BUF06M:1;
1349	uint32_t BUF05M:1;
1350	uint32_t BUF04M:1;
1351	uint32_t BUF03M:1;
1352	uint32_t BUF02M:1;
1353	uint32_t BUF01M:1;
1354	uint32_t BUF00M:1;
1355	} B;
1356	} IMASK1; /* Interruput Masks Register */
1357
1358	union {
1359	uint32_t R;
1360	struct {
1361	uint32_t BUF63I:1;
1362	uint32_t BUF62I:1;
1363	uint32_t BUF61I:1;
1364	uint32_t BUF60I:1;
1365	uint32_t BUF59I:1;
1366	uint32_t BUF58I:1;
1367	uint32_t BUF57I:1;
1368	uint32_t BUF56I:1;
1369	uint32_t BUF55I:1;
1370	uint32_t BUF54I:1;
1371	uint32_t BUF53I:1;
1372	uint32_t BUF52I:1;
1373	uint32_t BUF51I:1;
1374	uint32_t BUF50I:1;
1375	uint32_t BUF49I:1;
1376	uint32_t BUF48I:1;
1377	uint32_t BUF47I:1;
1378	uint32_t BUF46I:1;
1379	uint32_t BUF45I:1;
1380	uint32_t BUF44I:1;
1381	uint32_t BUF43I:1;
1382	uint32_t BUF42I:1;
1383	uint32_t BUF41I:1;
1384	uint32_t BUF40I:1;
1385	uint32_t BUF39I:1;
1386	uint32_t BUF38I:1;
1387	uint32_t BUF37I:1;
1388	uint32_t BUF36I:1;
1389	uint32_t BUF35I:1;
1390	uint32_t BUF34I:1;
1391	uint32_t BUF33I:1;
1392	uint32_t BUF32I:1;
1393	} B;
1394	} IFLAG2; /* Interruput Flag Register */
1395
1396	union {
1397	uint32_t R;
1398	struct {
1399	uint32_t BUF31I:1;
1400	uint32_t BUF30I:1;
1401	uint32_t BUF29I:1;
1402	uint32_t BUF28I:1;
1403	uint32_t BUF27I:1;
1404	uint32_t BUF26I:1;
1405	uint32_t BUF25I:1;
1406	uint32_t BUF24I:1;
1407	uint32_t BUF23I:1;
1408	uint32_t BUF22I:1;
1409	uint32_t BUF21I:1;
1410	uint32_t BUF20I:1;
1411	uint32_t BUF19I:1;
1412	uint32_t BUF18I:1;
1413	uint32_t BUF17I:1;
1414	uint32_t BUF16I:1;
1415	uint32_t BUF15I:1;
1416	uint32_t BUF14I:1;
1417	uint32_t BUF13I:1;
1418	uint32_t BUF12I:1;
1419	uint32_t BUF11I:1;
1420	uint32_t BUF10I:1;
1421	uint32_t BUF09I:1;
1422	uint32_t BUF08I:1;
1423	uint32_t BUF07I:1;
1424	uint32_t BUF06I:1;
1425	uint32_t BUF05I:1;
1426	uint32_t BUF04I:1;
1427	uint32_t BUF03I:1;
1428	uint32_t BUF02I:1;
1429	uint32_t BUF01I:1;
1430	uint32_t BUF00I:1;
1431	} B;
1432	} IFLAG1; /* Interruput Flag Register */
1433
1434	uint32_t FLEXCAN_reserved2[19];
1435
1436	struct canbuf_t {
1437	union {
1438	uint32_t R;
1439	struct {
1440	uint32_t:4;
1441	uint32_t CODE:4;
1442	uint32_t:1;
1443	uint32_t SRR:1;
1444	uint32_t IDE:1;
1445	uint32_t RTR:1;
1446	uint32_t LENGTH:4;
1447	uint32_t TIMESTAMP:16;
1448	} B;
1449	} CS;
1450
1451	union {
1452	uint32_t R;
1453	struct {
1454	uint32_t PRIO:3;
1455	uint32_t STD_ID:11;
1456	uint32_t EXT_ID:18;
1457	} B;
1458	} ID;
1459
1460	union {
1461	uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
1462	uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
1463	uint32_t W[2]; /* Data buffer in words (32 bits) */
1464	uint32_t R[2]; /* Data buffer in words (32 bits) */
1465	} DATA;
1466
1467	} BUF[64];
1468
1469	uint32_t FLEXCAN_reserved3[256];
1470
1471	union {
1472	uint32_t R;
1473	struct {
1474	uint32_t MI:32;
1475	} B;
1476	} RXIMR[64]; /* RX Individual Mask Registers */
1477
1478	};
1479	/****************************************************************************/
1480	/* MODULE : FMPLL */
1481	/****************************************************************************/
1482	struct FMPLL_tag {
1483
1484	uint32_t FMPLL_reserved0;
1485
1486	union FMPLL_SYNSR_tag { /* Synthesiser Status Register */
1487	uint32_t R;
1488	struct {
1489	uint32_t:22;
1490	uint32_t LOLF:1;
1491	uint32_t LOC:1;
1492	uint32_t MODE:1;
1493	uint32_t PLLSEL:1;
1494	uint32_t PLLREF:1;
1495	uint32_t LOCKS:1;
1496	uint32_t LOCK:1;
1497	uint32_t LOCF:1;
1498	uint32_t CALDONE:1;
1499	uint32_t CALPASS:1;
1500	} B;
1501	} SYNSR;
1502
1503	union FMPLL_ESYNCR1_tag {
1504	uint32_t R;
1505	struct {
1506	uint32_t:1;
1507	uint32_t CLKCFG:3;
1508	uint32_t:8;
1509	uint32_t EPREDIV:4;
1510	uint32_t:8;
1511	uint32_t EMFD:8;
1512	} B;
1513	} ESYNCR1;
1514
1515	union FMPLL_ESYNCR2_tag {
1516	uint32_t R;
1517	struct {
1518	uint32_t:8;
1519	uint32_t LOCEN:1;
1520	uint32_t LOLRE:1;
1521	uint32_t LOCRE:1;
1522	uint32_t LOLIRQ:1;
1523	uint32_t LOCIRQ:1;
1524	uint32_t:1;
1525	uint32_t ERATE:2;
1526	uint32_t:5;
1527	uint32_t EDEPTH:3;
1528	uint32_t:2;
1529	uint32_t ERFD:6;
1530	} B;
1531	} ESYNCR2;
1532
1533	};
1534	/****************************************************************************/
1535	/* MODULE : i2c */
1536	/****************************************************************************/
1537	struct I2C_tag {
1538	union {
1539	uint8_t R;
1540	struct {
1541	uint8_t AD:7;
1542	uint8_t:1;
1543	} B;
1544	} IBAD; /* Module Bus Address Register */
1545
1546	union {
1547	uint8_t R;
1548	struct {
1549	uint8_t MULT:2;
1550	uint8_t ICR:6;
1551	} B;
1552	} IBFD; /* Module Bus Frequency Register */
1553
1554	union {
1555	uint8_t R;
1556	struct {
1557	uint8_t MDIS:1;
1558	uint8_t IBIE:1;
1559	uint8_t MS:1;
1560	uint8_t TX:1;
1561	uint8_t NOACK:1;
1562	uint8_t RSTA:1;
1563	uint8_t DMAEN:1;
1564	uint8_t:1;
1565	} B;
1566	} IBCR; /* Module Bus Control Register */
1567
1568	union {
1569	uint8_t R;
1570	struct {
1571	uint8_t TCF:1;
1572	uint8_t IAAS:1;
1573	uint8_t IBB:1;
1574	uint8_t IBAL:1;
1575	uint8_t:1;
1576	uint8_t SRW:1;
1577	uint8_t IBIF:1;
1578	uint8_t RXAK:1;
1579	} B;
1580	} IBSR; /* Module Status Register */
1581
1582	union {
1583	uint8_t R;
1584	struct {
1585	uint8_t DATA:8;
1586	} B;
1587	} IBDR; /* Module Data Register */
1588
1589	union {
1590	uint8_t R;
1591	struct {
1592	uint8_t BIIE:1;
1593	uint8_t:7;
1594	} B;
1595	} IBIC; /* Module Interrupt Configuration Register */
1596
1597	};
1598	/****************************************************************************/
1599	/* MODULE : INTC */
1600	/****************************************************************************/
1601	struct INTC_tag {
1602	union {
1603	uint32_t R;
1604	struct {
1605	uint32_t:18;
1606	uint32_t VTES_PRC1:1;
1607	uint32_t:4;
1608	uint32_t HVEN_PRC1:1;
1609	uint32_t:2;
1610	uint32_t VTES:1;
1611	uint32_t:4;
1612	uint32_t HVEN:1;
1613	} B;
1614	} MCR; /* Module Configuration Register */
1615
1616	int32_t INTC_reserved1;
1617
1618	union {
1619	uint32_t R;
1620	struct {
1621	uint32_t:28;
1622	uint32_t PRI:4;
1623	} B;
1624	} CPR; /* Processor 0 Current Priority Register */
1625
1626	union {
1627	uint32_t R;
1628	struct {
1629	uint32_t:28;
1630	uint32_t PRI:4;
1631	} B;
1632	} CPR_PRC1; /* Processor 1 Current Priority Register */
1633
1634	union {
1635	uint32_t R;
1636	struct {
1637	uint32_t VTBA:21;
1638	uint32_t INTVEC:9;
1639	uint32_t:2;
1640	} B;
1641	} IACKR; /* Processor 0 Interrupt Acknowledge Register */
1642
1643	union {
1644	uint32_t R;
1645	struct {
1646	uint32_t VTBA_PRC1:21;
1647	uint32_t INTVEC_PRC1:9;
1648	uint32_t:2;
1649	} B;
1650	} IACKR_PRC1; /* Processor 1 Interrupt Acknowledge Register */
1651
1652	union {
1653	uint32_t R;
1654	struct {
1655	uint32_t:32;
1656	} B;
1657	} EOIR; /* Processor 0 End of Interrupt Register */
1658
1659	union {
1660	uint32_t R;
1661	struct {
1662	uint32_t:32;
1663	} B;
1664	} EOIR_PRC1; /* Processor 1 End of Interrupt Register */
1665
1666	union {
1667	uint8_t R;
1668	struct {
1669	uint8_t:6;
1670	uint8_t SET:1;
1671	uint8_t CLR:1;
1672	} B;
1673	} SSCIR[8]; /* Software Set/Clear Interruput Register */
1674
1675	uint32_t intc_reserved2[6];
1676
1677	union {
1678	uint8_t R;
1679	struct {
1680	uint8_t PRC_SEL:2;
1681	uint8_t:2;
1682	uint8_t PRI:4;
1683	} B;
1684	} PSR[294]; /* Software Set/Clear Interrupt Register */
1685
1686	};
1687	/****************************************************************************/
1688	/* MODULE : MCM */
1689	/****************************************************************************/
1690	struct MCM_tag {
1691
1692	uint32_t mcm_reserved1[5];
1693
1694	uint16_t mcm_reserved2;
1695
1696	union {
1697	uint16_t R;
1698	struct {
1699	uint16_t RO:1;
1700	uint16_t:6;
1701	uint16_t SWRWH:1;
1702	uint16_t SWE:1;
1703	uint16_t SWRI:2;
1704	uint16_t SWT:5;
1705	} B;
1706	} SWTCR; /* Software Watchdog Timer Control */
1707
1708	uint8_t mcm_reserved3[3];
1709
1710	union {
1711	uint8_t R;
1712	} SWTSR; /* SWT Service Register */
1713
1714	uint8_t mcm_reserved4[3];
1715
1716	union {
1717	uint8_t R;
1718	struct {
1719	uint8_t:7;
1720	uint8_t SWTIC:1;
1721	} B;
1722	} SWTIR; /* SWT Interrupt Register */
1723
1724	uint32_t mcm_reserved5[1];
1725
1726	union {
1727	uint32_t R;
1728	struct {
1729	uint32_t PRI:1;
1730	uint32_t:31;
1731	} B;
1732	} MUDCR; /* Misc. User Defined Control Register */
1733
1734	uint32_t mcm_reserved6[6];
1735	uint8_t mcm_reserved7[3];
1736
1737	union {
1738	uint8_t R;
1739	struct {
1740	uint8_t:6;
1741	uint8_t ERNCR:1;
1742	uint8_t EFNCR:1;
1743	} B;
1744	} ECR; /* ECC Configuration Register */
1745
1746	uint8_t mcm_reserved8[3];
1747
1748	union {
1749	uint8_t R;
1750	struct {
1751	uint8_t:6;
1752	uint8_t RNCE:1;
1753	uint8_t FNCE:1;
1754	} B;
1755	} ESR; /* ECC Status Register */
1756
1757	uint16_t mcm_reserved9;
1758
1759	union {
1760	uint16_t R;
1761	struct {
1762	uint16_t:6;
1763	uint16_t FRCNCI:1;
1764	uint16_t FR1NCI:1;
1765	uint16_t:1;
1766	uint16_t ERRBIT:7;
1767	} B;
1768	} EEGR; /* ECC Error Generation Register */
1769
1770	uint32_t mcm_reserved10;
1771
1772	union {
1773	uint32_t R;
1774	} FEAR; /* Flash ECC Address Register */
1775
1776	uint16_t mcm_reserved11;
1777
1778	union {
1779	uint8_t R;
1780	struct {
1781	uint8_t:4;
1782	uint8_t FEMR:4;
1783	} B;
1784	} FEMR; /* Flash ECC Master Register */
1785
1786	union {
1787	uint8_t R;
1788	struct {
1789	uint8_t WRITE:1;
1790	uint8_t SIZE:3;
1791	uint8_t PROTECTION:4;
1792	} B;
1793	} FEAT; /* Flash ECC Attributes Register */
1794
1795	union {
1796	uint32_t R;
1797	} FEDRH; /* Flash ECC Data High Register */
1798
1799	union {
1800	uint32_t R;
1801	} FEDRL; /* Flash ECC Data Low Register */
1802
1803	union {
1804	uint32_t R;
1805	struct {
1806	uint32_t REAR:32;
1807	} B;
1808	} REAR; /* RAM ECC Address */
1809
1810	uint16_t mcm_reserved12;
1811
1812	union {
1813	uint8_t R;
1814	struct {
1815	uint8_t:4;
1816	uint8_t REMR:4;
1817	} B;
1818	} REMR; /* RAM ECC Master */
1819
1820	union {
1821	uint8_t R;
1822	struct {
1823	uint8_t WRITE:1;
1824	uint8_t SIZE:3;
1825	uint8_t PROTECTION:4;
1826	} B;
1827	} REAT; /* RAM ECC Attributes Register */
1828
1829	union {
1830	uint32_t R;
1831	} REDRH; /* RAM ECC Data High Register */
1832
1833	union {
1834	uint32_t R;
1835	} REDRL; /* RAMECC Data Low Register */
1836
1837	};
1838	/****************************************************************************/
1839	/* MODULE : MPU */
1840	/****************************************************************************/
1841	struct MPU_tag {
1842	union {
1843	uint32_t R;
1844	struct {
1845	uint32_t SPERR:8;
1846	uint32_t:4;
1847	uint32_t HRL:4;
1848	uint32_t NSP:4;
1849	uint32_t NGRD:4;
1850	uint32_t:7;
1851	uint32_t VLD:1;
1852	} B;
1853	} CESR; /* Module Control/Error Status Register */
1854
1855	uint32_t mpu_reserved1[3];
1856
1857	union {
1858	uint32_t R;
1859	struct {
1860	uint32_t EADDR:32;
1861	} B;
1862	} EAR0;
1863
1864	union {
1865	uint32_t R;
1866	struct {
1867	uint32_t EACD:16;
1868	uint32_t EPID:8;
1869	uint32_t EMN:4;
1870	uint32_t EATTR:3;
1871	uint32_t ERW:1;
1872	} B;
1873	} EDR0;
1874
1875	union {
1876	uint32_t R;
1877	struct {
1878	uint32_t EADDR:32;
1879	} B;
1880	} EAR1;
1881
1882	union {
1883	uint32_t R;
1884	struct {
1885	uint32_t EACD:16;
1886	uint32_t EPID:8;
1887	uint32_t EMN:4;
1888	uint32_t EATTR:3;
1889	uint32_t ERW:1;
1890	} B;
1891	} EDR1;
1892
1893	union {
1894	uint32_t R;
1895	struct {
1896	uint32_t EADDR:32;
1897	} B;
1898	} EAR2;
1899
1900	union {
1901	uint32_t R;
1902	struct {
1903	uint32_t EACD:16;
1904	uint32_t EPID:8;
1905	uint32_t EMN:4;
1906	uint32_t EATTR:3;
1907	uint32_t ERW:1;
1908	} B;
1909	} EDR2;
1910
1911	uint32_t mpu_reserved2[246];
1912
1913	struct {
1914	union {
1915	uint32_t R;
1916	struct {
1917	uint32_t SRTADDR:27;
1918	uint32_t:5;
1919	} B;
1920	} WORD0; /* Region Descriptor n Word 0 */
1921
1922	union {
1923	uint32_t R;
1924	struct {
1925	uint32_t ENDADDR:27;
1926	uint32_t:5;
1927	} B;
1928	} WORD1; /* Region Descriptor n Word 1 */
1929
1930	union {
1931	uint32_t R;
1932	struct {
1933	uint32_t:6;
1934	uint32_t M4RE0:1;
1935	uint32_t M4WE:1;
1936	uint32_t M3PE:1;
1937	uint32_t M3SM:2;
1938	uint32_t M3UM:3;
1939	uint32_t M2PE:1;
1940	uint32_t M2SM:2;
1941	uint32_t M2UM:3;
1942	uint32_t M1PE:1;
1943	uint32_t M1SM:2;
1944	uint32_t M1UM:3;
1945	uint32_t M0PE:1;
1946	uint32_t M0SM:2;
1947	uint32_t M0UM:3;
1948	} B;
1949	} WORD2; /* Region Descriptor n Word 2 */
1950
1951	union {
1952	uint32_t R;
1953	struct {
1954	uint32_t PID:8;
1955	uint32_t PIDMASK:8;
1956	uint32_t:15;
1957	uint32_t VLD:1;
1958	} B;
1959	} WORD3; /* Region Descriptor n Word 3 */
1960
1961	} RGD[16];
1962
1963	uint32_t mpu_reserved3[192];
1964
1965	union {
1966	uint32_t R;
1967	struct {
1968	uint32_t:6;
1969	uint32_t M4RE:1;
1970	uint32_t M4WE:1;
1971	uint32_t M3PE:1;
1972	uint32_t M3SM:2;
1973	uint32_t M3UM:3;
1974	uint32_t M2PE:1;
1975	uint32_t M2SM:2;
1976	uint32_t M2UM:3;
1977	uint32_t M1PE:1;
1978	uint32_t M1SM:2;
1979	uint32_t M1UM:3;
1980	uint32_t M0PE:1;
1981	uint32_t M0SM:2;
1982	uint32_t M0UM:3;
1983	} B;
1984	} RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
1985	};
1986	/****************************************************************************/
1987	/* MODULE : pit */
1988	/****************************************************************************/
1989	struct PIT_tag {
1990	union {
1991	uint32_t R;
1992	struct {
1993	uint32_t TSV:32;
1994	} B;
1995	} TLVAL[9];
1996
1997	uint32_t pit_reserved1[23];
1998
1999	union {
2000	uint32_t R;
2001	struct {
2002	uint32_t TVL:32;
2003	} B;
2004	} TVAL[9];
2005
2006	uint32_t pit_reserved2[23];
2007
2008	union {
2009	uint32_t R;
2010	struct {
2011	uint32_t:23;
2012	uint32_t TIF8:1;
2013	uint32_t TIF7:1;
2014	uint32_t TIF6:1;
2015	uint32_t TIF5:1;
2016	uint32_t TIF4:1;
2017	uint32_t TIF3:1;
2018	uint32_t TIF2:1;
2019	uint32_t TIF1:1;
2020	uint32_t RTIF:1;
2021	} B;
2022	} PITFLG;
2023
2024	union {
2025	uint32_t R;
2026	struct {
2027	uint32_t:23;
2028	uint32_t TIE8:1;
2029	uint32_t TIE7:1;
2030	uint32_t TIE6:1;
2031	uint32_t TIE5:1;
2032	uint32_t TIE4:1;
2033	uint32_t TIE3:1;
2034	uint32_t TIE2:1;
2035	uint32_t TIE1:1;
2036	uint32_t RTIE:1;
2037	} B;
2038	} PITINTEN;
2039
2040	union {
2041	uint32_t R;
2042	struct {
2043	uint32_t:23;
2044	uint32_t ISEL8:1;
2045	uint32_t ISEL7:1;
2046	uint32_t ISEL6:1;
2047	uint32_t ISEL5:1;
2048	uint32_t ISEL4:1;
2049	uint32_t ISEL3:1;
2050	uint32_t ISEL2:1;
2051	uint32_t ISEL1:1;
2052	uint32_t:1;
2053	} B;
2054	} PITINTSEL;
2055
2056	union {
2057	uint32_t R;
2058	struct {
2059	uint32_t:23;
2060	uint32_t PEN8:1;
2061	uint32_t PEN7:1;
2062	uint32_t PEN6:1;
2063	uint32_t PEN5:1;
2064	uint32_t PEN4:1;
2065	uint32_t PEN3:1;
2066	uint32_t PEN2:1;
2067	uint32_t PEN1:1;
2068	uint32_t PEN0:1;
2069	} B;
2070	} PITEN;
2071
2072	union {
2073	uint32_t R;
2074	struct {
2075	uint32_t:7;
2076	uint32_t MDIS:1;
2077	uint32_t:24;
2078	} B;
2079	} PITCTRL;
2080
2081	};
2082	/****************************************************************************/
2083	/* MODULE : sem4 */
2084	/****************************************************************************/
2085	struct SEMA4_tag {
2086	union {
2087	uint8_t R;
2088	struct {
2089	uint8_t:6;
2090	uint8_t GTFSM:2;
2091	} B;
2092	} GATE[16]; /* Gate n Register */
2093
2094	uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */
2095
2096	union {
2097	uint16_t R;
2098	struct {
2099	uint16_t INE0:1;
2100	uint16_t INE1:1;
2101	uint16_t INE2:1;
2102	uint16_t INE3:1;
2103	uint16_t INE4:1;
2104	uint16_t INE5:1;
2105	uint16_t INE6:1;
2106	uint16_t INE7:1;
2107	uint16_t INE8:1;
2108	uint16_t INE9:1;
2109	uint16_t INE10:1;
2110	uint16_t INE11:1;
2111	uint16_t INE12:1;
2112	uint16_t INE13:1;
2113	uint16_t INE14:1;
2114	uint16_t INE15:1;
2115	} B;
2116	} CP0INE;
2117
2118	uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */
2119
2120	union {
2121	uint16_t R;
2122	struct {
2123	uint16_t INE0:1;
2124	uint16_t INE1:1;
2125	uint16_t INE2:1;
2126	uint16_t INE3:1;
2127	uint16_t INE4:1;
2128	uint16_t INE5:1;
2129	uint16_t INE6:1;
2130	uint16_t INE7:1;
2131	uint16_t INE8:1;
2132	uint16_t INE9:1;
2133	uint16_t INE10:1;
2134	uint16_t INE11:1;
2135	uint16_t INE12:1;
2136	uint16_t INE13:1;
2137	uint16_t INE14:1;
2138	uint16_t INE15:1;
2139	} B;
2140	} CP1INE;
2141
2142	uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */
2143
2144	union {
2145	uint16_t R;
2146	struct {
2147	uint16_t GN0:1;
2148	uint16_t GN1:1;
2149	uint16_t GN2:1;
2150	uint16_t GN3:1;
2151	uint16_t GN4:1;
2152	uint16_t GN5:1;
2153	uint16_t GN6:1;
2154	uint16_t GN7:1;
2155	uint16_t GN8:1;
2156	uint16_t GN9:1;
2157	uint16_t GN10:1;
2158	uint16_t GN11:1;
2159	uint16_t GN12:1;
2160	uint16_t GN13:1;
2161	uint16_t GN14:1;
2162	uint16_t GN15:1;
2163	} B;
2164	} CP0NTF;
2165
2166	uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */
2167
2168	union {
2169	uint16_t R;
2170	struct {
2171	uint16_t GN0:1;
2172	uint16_t GN1:1;
2173	uint16_t GN2:1;
2174	uint16_t GN3:1;
2175	uint16_t GN4:1;
2176	uint16_t GN5:1;
2177	uint16_t GN6:1;
2178	uint16_t GN7:1;
2179	uint16_t GN8:1;
2180	uint16_t GN9:1;
2181	uint16_t GN10:1;
2182	uint16_t GN11:1;
2183	uint16_t GN12:1;
2184	uint16_t GN13:1;
2185	uint16_t GN14:1;
2186	uint16_t GN15:1;
2187	} B;
2188	} CP1NTF;
2189
2190	uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */
2191
2192	union {
2193	uint16_t R;
2194	struct {
2195	uint16_t:2;
2196	uint16_t RSTGSM:2;
2197	uint16_t:1;
2198	uint16_t RSTGMS:3;
2199	uint16_t RSTGTN:8;
2200	} B;
2201	} RSTGT;
2202
2203	uint16_t sema4_reserved6;
2204
2205	union {
2206	uint16_t R;
2207	struct {
2208	uint16_t:2;
2209	uint16_t RSTNSM:2;
2210	uint16_t:1;
2211	uint16_t RSTNMS:3;
2212	uint16_t RSTNTN:8;
2213	} B;
2214	} RSTNTF;
2215	};
2216	/****************************************************************************/
2217	/* MODULE : SIU */
2218	/****************************************************************************/
2219	struct SIU_tag {
2220
2221	int32_t SIU_reserved0;
2222
2223	union { /* MCU ID Register */
2224	uint32_t R;
2225	struct {
2226	uint32_t PARTNUM:16;
2227	uint32_t CSP:1;
2228	uint32_t PKG:5;
2229	uint32_t:2;
2230	uint32_t MASKNUM_MAJOR:4;
2231	uint32_t MASKNUM_MINOR:4;
2232	} B;
2233	} MIDR;
2234
2235	int32_t SIU_reserved1;
2236
2237	union { /* Reset Status Register */
2238	uint32_t R;
2239	struct {
2240	uint32_t PORS:1;
2241	uint32_t ERS:1;
2242	uint32_t LLRS:1;
2243	uint32_t LCRS:1;
2244	uint32_t WDRS:1;
2245	uint32_t CRS:1;
2246	uint32_t:8;
2247	uint32_t SSRS:1;
2248	uint32_t:15;
2249	uint32_t BOOTCFG:1;
2250	uint32_t:1;
2251	} B;
2252	} RSR;
2253
2254	union { /* System Reset Control Register */
2255	uint32_t R;
2256	struct {
2257	uint32_t SSR:1;
2258	uint32_t:15;
2259	uint32_t CRE0:1;
2260	uint32_t CRE1:1;
2261	uint32_t:6;
2262	uint32_t SSRL:1;
2263	uint32_t:7;
2264	} B;
2265	} SRCR;
2266
2267	union SIU_EISR_tag { /* External Interrupt Status Register */
2268	uint32_t R;
2269	struct {
2270	uint32_t NMI0:1;
2271	uint32_t NMI1:1;
2272	uint32_t:14;
2273	uint32_t EIF15:1;
2274	uint32_t EIF14:1;
2275	uint32_t EIF13:1;
2276	uint32_t EIF12:1;
2277	uint32_t EIF11:1;
2278	uint32_t EIF10:1;
2279	uint32_t EIF9:1;
2280	uint32_t EIF8:1;
2281	uint32_t EIF7:1;
2282	uint32_t EIF6:1;
2283	uint32_t EIF5:1;
2284	uint32_t EIF4:1;
2285	uint32_t EIF3:1;
2286	uint32_t EIF2:1;
2287	uint32_t EIF1:1;
2288	uint32_t EIF0:1;
2289	} B;
2290	} EISR;
2291
2292	union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
2293	uint32_t R;
2294	struct {
2295	uint32_t:16;
2296	uint32_t EIRE15:1;
2297	uint32_t EIRE14:1;
2298	uint32_t EIRE13:1;
2299	uint32_t EIRE12:1;
2300	uint32_t EIRE11:1;
2301	uint32_t EIRE10:1;
2302	uint32_t EIRE9:1;
2303	uint32_t EIRE8:1;
2304	uint32_t EIRE7:1;
2305	uint32_t EIRE6:1;
2306	uint32_t EIRE5:1;
2307	uint32_t EIRE4:1;
2308	uint32_t EIRE3:1;
2309	uint32_t EIRE2:1;
2310	uint32_t EIRE1:1;
2311	uint32_t EIRE0:1;
2312	} B;
2313	} DIRER;
2314
2315	union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */
2316	uint32_t R;
2317	struct {
2318	uint32_t:27;
2319	uint32_t DIRS4:1;
2320	uint32_t DIRS3:1;
2321	uint32_t DIRS2:1;
2322	uint32_t DIRS1:1;
2323	uint32_t:1;
2324	} B;
2325	} DIRSR;
2326
2327	union { /* Overrun Status Register */
2328	uint32_t R;
2329	struct {
2330	uint32_t:16;
2331	uint32_t OVF15:1;
2332	uint32_t OVF14:1;
2333	uint32_t OVF13:1;
2334	uint32_t OVF12:1;
2335	uint32_t OVF11:1;
2336	uint32_t OVF10:1;
2337	uint32_t OVF9:1;
2338	uint32_t OVF8:1;
2339	uint32_t OVF7:1;
2340	uint32_t OVF6:1;
2341	uint32_t OVF5:1;
2342	uint32_t OVF4:1;
2343	uint32_t OVF3:1;
2344	uint32_t OVF2:1;
2345	uint32_t OVF1:1;
2346	uint32_t OVF0:1;
2347	} B;
2348	} OSR;
2349
2350	union SIU_ORER_tag { /* Overrun Request Enable Register */
2351	uint32_t R;
2352	struct {
2353	uint32_t:16;
2354	uint32_t ORE15:1;
2355	uint32_t ORE14:1;
2356	uint32_t ORE13:1;
2357	uint32_t ORE12:1;
2358	uint32_t ORE11:1;
2359	uint32_t ORE10:1;
2360	uint32_t ORE9:1;
2361	uint32_t ORE8:1;
2362	uint32_t ORE7:1;
2363	uint32_t ORE6:1;
2364	uint32_t ORE5:1;
2365	uint32_t ORE4:1;
2366	uint32_t ORE3:1;
2367	uint32_t ORE2:1;
2368	uint32_t ORE1:1;
2369	uint32_t ORE0:1;
2370	} B;
2371	} ORER;
2372
2373	union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
2374	uint32_t R;
2375	struct {
2376	uint32_t NREE0:1;
2377	uint32_t NREE1:1;
2378	uint32_t:14;
2379	uint32_t IREE15:1;
2380	uint32_t IREE14:1;
2381	uint32_t IREE13:1;
2382	uint32_t IREE12:1;
2383	uint32_t IREE11:1;
2384	uint32_t IREE10:1;
2385	uint32_t IREE9:1;
2386	uint32_t IREE8:1;
2387	uint32_t IREE7:1;
2388	uint32_t IREE6:1;
2389	uint32_t IREE5:1;
2390	uint32_t IREE4:1;
2391	uint32_t IREE3:1;
2392	uint32_t IREE2:1;
2393	uint32_t IREE1:1;
2394	uint32_t IREE0:1;
2395	} B;
2396	} IREER;
2397
2398	union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
2399	uint32_t R;
2400	struct {
2401	uint32_t NFEE0:1;
2402	uint32_t NFEE1:1;
2403	uint32_t:14;
2404	uint32_t IFEE15:1;
2405	uint32_t IFEE14:1;
2406	uint32_t IFEE13:1;
2407	uint32_t IFEE12:1;
2408	uint32_t IFEE11:1;
2409	uint32_t IFEE10:1;
2410	uint32_t IFEE9:1;
2411	uint32_t IFEE8:1;
2412	uint32_t IFEE7:1;
2413	uint32_t IFEE6:1;
2414	uint32_t IFEE5:1;
2415	uint32_t IFEE4:1;
2416	uint32_t IFEE3:1;
2417	uint32_t IFEE2:1;
2418	uint32_t IFEE1:1;
2419	uint32_t IFEE0:1;
2420	} B;
2421	} IFEER;
2422
2423	union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
2424	uint32_t R;
2425	struct {
2426	uint32_t:28;
2427	uint32_t DFL:4;
2428	} B;
2429	} IDFR;
2430
2431	union { /* External IRQ Filtered Input Register */
2432	uint32_t R;
2433	struct {
2434	uint32_t FNMI0:1;
2435	uint32_t FNMI1:1;
2436	uint32_t:14;
2437	uint32_t FI15:1;
2438	uint32_t FI14:1;
2439	uint32_t FI13:1;
2440	uint32_t FI12:1;
2441	uint32_t FI11:1;
2442	uint32_t FI10:1;
2443	uint32_t FI9:1;
2444	uint32_t FI8:1;
2445	uint32_t FI7:1;
2446	uint32_t FI6:1;
2447	uint32_t FI5:1;
2448	uint32_t FI4:1;
2449	uint32_t FI3:1;
2450	uint32_t FI2:1;
2451	uint32_t FI1:1;
2452	uint32_t FI0:1;
2453	} B;
2454	} IFIR;
2455
2456	int32_t SIU_reserved2[2];
2457
2458	union SIU_PCR_tag { /* Pad Configuration Registers */
2459	uint16_t R;
2460	struct {
2461	uint16_t:4;
2462	uint16_t PA:2;
2463	uint16_t OBE:1;
2464	uint16_t IBE:1;
2465	uint16_t:2;
2466	uint16_t ODE:1;
2467	uint16_t HYS:1;
2468	uint16_t SRC:2;
2469	uint16_t WPE:1;
2470	uint16_t WPS:1;
2471	} B;
2472	} PCR[146];
2473
2474	int32_t SIU_reserved3[295];
2475
2476	union { /* GPIO Pin Data Output Registers */
2477	uint8_t R;
2478	struct {
2479	uint8_t:7;
2480	uint8_t PDO:1;
2481	} B;
2482	} GPDO[146];
2483
2484	int32_t SIU_reserved4[91];
2485
2486	union { /* GPIO Pin Data Input Registers */
2487	uint8_t R;
2488	struct {
2489	uint8_t:7;
2490	uint8_t PDI:1;
2491	} B;
2492	} GPDI[146];
2493
2494	int32_t SIU_reserved5[27];
2495
2496	union { /* IMUX Register */
2497	uint32_t R;
2498	struct {
2499	uint32_t TSEL3:2;
2500	uint32_t TSEL2:2;
2501	uint32_t TSEL1:2;
2502	uint32_t TSEL0:2;
2503	uint32_t:24;
2504	} B;
2505	} ISEL0;
2506
2507	union { /* IMUX Register */
2508	uint32_t R;
2509	struct {
2510	uint32_t ESEL15:2;
2511	uint32_t ESEL14:2;
2512	uint32_t ESEL13:2;
2513	uint32_t ESEL12:2;
2514	uint32_t ESEL11:2;
2515	uint32_t ESEL10:2;
2516	uint32_t ESEL9:2;
2517	uint32_t ESEL8:2;
2518	uint32_t ESEL7:2;
2519	uint32_t ESEL6:2;
2520	uint32_t ESEL5:2;
2521	uint32_t ESEL4:2;
2522	uint32_t ESEL3:2;
2523	uint32_t ESEL2:2;
2524	uint32_t ESEL1:2;
2525	uint32_t ESEL0:2;
2526	} B;
2527	} ISEL1;
2528
2529	union { /* IMUX Register */
2530	uint32_t R;
2531	struct {
2532	uint32_t SELEMIOS15:2;
2533	uint32_t SELEMIOS14:2;
2534	uint32_t SELEMIOS13:2;
2535	uint32_t SELEMIOS12:2;
2536	uint32_t SELEMIOS11:2;
2537	uint32_t SELEMIOS10:2;
2538	uint32_t SELEMIOS9:2;
2539	uint32_t SELEMIOS8:2;
2540	uint32_t SELEMIOS7:2;
2541	uint32_t SELEMIOS6:2;
2542	uint32_t SELEMIOS5:2;
2543	uint32_t SELEMIOS4:2;
2544	uint32_t SELEMIOS3:2;
2545	uint32_t SELEMIOS2:2;
2546	uint32_t SELEMIOS1:2;
2547	uint32_t SELEMIOS0:2;
2548	} B;
2549	} ISEL2;
2550
2551	int32_t SIU_reserved6[29];
2552
2553	union { /* Chip Configuration Register Register */
2554	uint32_t R;
2555	struct {
2556	uint32_t:14;
2557	uint32_t MATCH:1;
2558	uint32_t DISNEX:1;
2559	uint32_t:16;
2560	} B;
2561	} CCR;
2562
2563	union { /* External Clock Configuration Register Register */
2564	uint32_t R;
2565	struct {
2566	uint32_t:30;
2567	uint32_t EBDF:2;
2568	} B;
2569	} ECCR;
2570
2571	union { /* Compare A High Register */
2572	uint32_t R;
2573	} CMPAH;
2574
2575	union { /* Compare A Low Register */
2576	uint32_t R;
2577	} CMPAL;
2578
2579	union { /* Compare B High Register */
2580	uint32_t R;
2581	} CMPBH;
2582
2583	union { /* Compare B Low Register */
2584	uint32_t R;
2585	} CMPBL;
2586
2587	int32_t SIU_reserved7[2];
2588
2589	union { /* System CLock Register */
2590	uint32_t R;
2591	struct {
2592	uint32_t SYSCLKSEL:2;
2593	uint32_t SYSCLKDIV:2;
2594	uint32_t SWTCLKSEL:1;
2595	uint32_t:11;
2596	uint32_t LPCLKDIV7:2;
2597	uint32_t LPCLKDIV6:2;
2598	uint32_t LPCLKDIV5:2;
2599	uint32_t LPCLKDIV4:2;
2600	uint32_t LPCLKDIV3:2;
2601	uint32_t LPCLKDIV2:2;
2602	uint32_t LPCLKDIV1:2;
2603	uint32_t LPCLKDIV0:2;
2604	} B;
2605	} SYSCLK;
2606
2607	union { /* Halt Register */
2608	uint32_t R;
2609	} HLT;
2610
2611	union { /* Halt Acknowledge Register */
2612	uint32_t R;
2613	} HLTACK;
2614
2615	int32_t SIU_reserved8[149];
2616
2617	union { /* Parallel GPIO Pin Data Output Register */
2618	uint32_t R;
2619	struct {
2620	uint32_t:16;
2621	uint32_t PB:16;
2622	} B;
2623	} PGPDO0;
2624
2625	union { /* Parallel GPIO Pin Data Output Register */
2626	uint32_t R;
2627	struct {
2628	uint32_t PC:16;
2629	uint32_t PD:16;
2630	} B;
2631	} PGPDO1;
2632
2633	union { /* Parallel GPIO Pin Data Output Register */
2634	uint32_t R;
2635	struct {
2636	uint32_t PE:16;
2637	uint32_t PF:16;
2638	} B;
2639	} PGPDO2;
2640
2641	union { /* Parallel GPIO Pin Data Output Register */
2642	uint32_t R;
2643	struct {
2644	uint32_t PG:16;
2645	uint32_t PH:16;
2646	} B;
2647	} PGPDO3;
2648
2649	union { /* Parallel GPIO Pin Data Output Register */
2650	uint32_t R;
2651	struct {
2652	uint32_t PJ:16;
2653	uint32_t:16;
2654	} B;
2655	} PGPDO4;
2656
2657	int32_t SIU_reserved9[11];
2658
2659	union { /* Parallel GPIO Pin Data Input Register */
2660	uint32_t R;
2661	struct {
2662	uint32_t PA:16;
2663	uint32_t PB:16;
2664	} B;
2665	} PGPDI0;
2666
2667	union { /* Parallel GPIO Pin Data Input Register */
2668	uint32_t R;
2669	struct {
2670	uint32_t PC:16;
2671	uint32_t PD:16;
2672	} B;
2673	} PGPDI1;
2674
2675	union { /* Parallel GPIO Pin Data Input Register */
2676	uint32_t R;
2677	struct {
2678	uint32_t PE:16;
2679	uint32_t PF:16;
2680	} B;
2681	} PGPDI2;
2682
2683	union { /* Parallel GPIO Pin Data Input Register */
2684	uint32_t R;
2685	struct {
2686	uint32_t PG:16;
2687	uint32_t PH:16;
2688	} B;
2689	} PGPDI3;
2690
2691	union { /* Parallel GPIO Pin Data Input Register */
2692	uint32_t R;
2693	struct {
2694	uint32_t PJ:16;
2695	uint32_t PK:2;
2696	uint32_t:14;
2697	} B;
2698	} PGPDI4;
2699
2700	int32_t SIU_reserved10[12];
2701
2702	union { /* Masked Parallel GPIO Pin Data Input Register */
2703	uint32_t R;
2704	struct {
2705	uint32_t PB_MASK:16;
2706	uint32_t PB:16;
2707	} B;
2708	} MPGPDO1;
2709
2710	union { /* Masked Parallel GPIO Pin Data Input Register */
2711	uint32_t R;
2712	struct {
2713	uint32_t PC_MASK:16;
2714	uint32_t PC:16;
2715	} B;
2716	} MPGPDO2;
2717
2718	union { /* Masked Parallel GPIO Pin Data Input Register */
2719	uint32_t R;
2720	struct {
2721	uint32_t PD_MASK:16;
2722	uint32_t PD:16;
2723	} B;
2724	} MPGPDO3;
2725
2726	union { /* Masked Parallel GPIO Pin Data Input Register */
2727	uint32_t R;
2728	struct {
2729	uint32_t PE_MASK:16;
2730	uint32_t PE:16;
2731	} B;
2732	} MPGPDO4;
2733
2734	union { /* Masked Parallel GPIO Pin Data Input Register */
2735	uint32_t R;
2736	struct {
2737	uint32_t PF_MASK:16;
2738	uint32_t PF:16;
2739	} B;
2740	} MPGPDO5;
2741
2742	union { /* Masked Parallel GPIO Pin Data Input Register */
2743	uint32_t R;
2744	struct {
2745	uint32_t PG_MASK:16;
2746	uint32_t PG:16;
2747	} B;
2748	} MPGPDO6;
2749
2750	union { /* Masked Parallel GPIO Pin Data Input Register */
2751	uint32_t R;
2752	struct {
2753	uint32_t PH_MASK:16;
2754	uint32_t PH:16;
2755	} B;
2756	} MPGPDO7;
2757
2758	union { /* Masked Parallel GPIO Pin Data Input Register */
2759	uint32_t R;
2760	struct {
2761	uint32_t PJ_MASK:16;
2762	uint32_t PJ:16;
2763	} B;
2764	} MPGPDO8;
2765
2766	};
2767	/****************************************************************************/
2768	/* MODULE : FlexRay */
2769	/****************************************************************************/
2770
2771	typedef union uMVR {
2772	uint16_t R;
2773	struct {
2774	uint16_t CHIVER:8; /* CHI Version Number */
2775	uint16_t PEVER:8; /* PE Version Number */
2776	} B;
2777	} MVR_t;
2778
2779	typedef union uMCR {
2780	uint16_t R;
2781	struct {
2782	uint16_t MEN:1; /* module enable */
2783	uint16_t:1;
2784	uint16_t SCMD:1; /* single channel mode */
2785	uint16_t CHB:1; /* channel B enable */
2786	uint16_t CHA:1; /* channel A enable */
2787	uint16_t SFFE:1; /* synchronization frame filter enable */
2788	uint16_t:5;
2789	uint16_t CLKSEL:1; /* protocol engine clock source select */
2790	uint16_t PRESCALE:3; /* protocol engine clock prescaler */
2791	uint16_t:1;
2792	} B;
2793	} MCR_t;
2794	typedef union uSTBSCR {
2795	uint16_t R;
2796	struct {
2797	uint16_t WMD:1; /* write mode */
2798	uint16_t STBSSEL:7; /* strobe signal select */
2799	uint16_t:3;
2800	uint16_t ENB:1; /* strobe signal enable */
2801	uint16_t:2;
2802	uint16_t STBPSEL:2; /* strobe port select */
2803	} B;
2804	} STBSCR_t;
2805	typedef union uMBDSR {
2806	uint16_t R;
2807	struct {
2808	uint16_t:1;
2809	uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
2810	uint16_t:1;
2811	uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
2812	} B;
2813	} MBDSR_t;
2814
2815	typedef union uMBSSUTR {
2816	uint16_t R;
2817	struct {
2818
2819	uint16_t:2;
2820	uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */
2821	uint16_t:2;
2822	uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */
2823	} B;
2824	} MBSSUTR_t;
2825
2826	typedef union uPOCR {
2827	uint16_t R;
2828	uint8_t byte[2];
2829	struct {
2830	uint16_t WME:1; /* write mode external correction command */
2831	uint16_t:3;
2832	uint16_t EOC_AP:2; /* external offset correction application */
2833	uint16_t ERC_AP:2; /* external rate correction application */
2834	uint16_t BSY:1; /* command write busy / write mode command */
2835	uint16_t:3;
2836	uint16_t POCCMD:4; /* protocol command */
2837	} B;
2838	} POCR_t;
2839	/* protocol commands */
2840	typedef union uGIFER {
2841	uint16_t R;
2842	struct {
2843	uint16_t MIF:1; /* module interrupt flag */
2844	uint16_t PRIF:1; /* protocol interrupt flag */
2845	uint16_t CHIF:1; /* CHI interrupt flag */
2846	uint16_t WKUPIF:1; /* wakeup interrupt flag */
2847	uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
2848	uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
2849	uint16_t RBIF:1; /* receive message buffer interrupt flag */
2850	uint16_t TBIF:1; /* transmit buffer interrupt flag */
2851	uint16_t MIE:1; /* module interrupt enable */
2852	uint16_t PRIE:1; /* protocol interrupt enable */
2853	uint16_t CHIE:1; /* CHI interrupt enable */
2854	uint16_t WKUPIE:1; /* wakeup interrupt enable */
2855	uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
2856	uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
2857	uint16_t RBIE:1; /* receive message buffer interrupt enable */
2858	uint16_t TBIE:1; /* transmit buffer interrupt enable */
2859	} B;
2860	} GIFER_t;
2861	typedef union uPIFR0 {
2862	uint16_t R;
2863	struct {
2864	uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
2865	uint16_t INTLIF:1; /* internal protocol error interrupt flag */
2866	uint16_t ILCFIF:1; /* illegal protocol configuration flag */
2867	uint16_t CSAIF:1; /* cold start abort interrupt flag */
2868	uint16_t MRCIF:1; /* missing rate correctio interrupt flag */
2869	uint16_t MOCIF:1; /* missing offset correctio interrupt flag */
2870	uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
2871	uint16_t MXSIF:1; /* max sync frames detected interrupt flag */
2872	uint16_t MTXIF:1; /* media access test symbol received flag */
2873	uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
2874	uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
2875	uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
2876	uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
2877	uint16_t TI2IF:1; /* timer 2 expired interrupt flag */
2878	uint16_t TI1IF:1; /* timer 1 expired interrupt flag */
2879	uint16_t CYSIF:1; /* cycle start interrupt flag */
2880	} B;
2881	} PIFR0_t;
2882	typedef union uPIFR1 {
2883	uint16_t R;
2884	struct {
2885	uint16_t EMCIF:1; /* error mode changed interrupt flag */
2886	uint16_t IPCIF:1; /* illegal protocol command interrupt flag */
2887	uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
2888	uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
2889	uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
2890	uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
2891	uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
2892	uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
2893	uint16_t:2;
2894	uint16_t EVTIF:1; /* even cycle table written interrupt flag */
2895	uint16_t ODTIF:1; /* odd cycle table written interrupt flag */
2896	uint16_t:4;
2897	} B;
2898	} PIFR1_t;
2899	typedef union uPIER0 {
2900	uint16_t R;
2901	struct {
2902	uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
2903	uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
2904	uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
2905	uint16_t CSAIE:1; /* cold start abort interrupt enable */
2906	uint16_t MRCIE:1; /* missing rate correctio interrupt enable */
2907	uint16_t MOCIE:1; /* missing offset correctio interrupt enable */
2908	uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
2909	uint16_t MXSIE:1; /* max sync frames detected interrupt enable */
2910	uint16_t MTXIE:1; /* media access test symbol received interrupt enable */
2911	uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
2912	uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
2913	uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
2914	uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
2915	uint16_t TI2IE:1; /* timer 2 expired interrupt enable */
2916	uint16_t TI1IE:1; /* timer 1 expired interrupt enable */
2917	uint16_t CYSIE:1; /* cycle start interrupt enable */
2918	} B;
2919	} PIER0_t;
2920	typedef union uPIER1 {
2921	uint16_t R;
2922	struct {
2923	uint16_t EMCIE:1; /* error mode changed interrupt enable */
2924	uint16_t IPCIE:1; /* illegal protocol command interrupt enable */
2925	uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
2926	uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
2927	uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
2928	uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
2929	uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
2930	uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
2931	uint16_t:2;
2932	uint16_t EVTIE:1; /* even cycle table written interrupt enable */
2933	uint16_t ODTIE:1; /* odd cycle table written interrupt enable */
2934	uint16_t:4;
2935	} B;
2936	} PIER1_t;
2937	typedef union uCHIERFR {
2938	uint16_t R;
2939	struct {
2940	uint16_t FRLBEF:1; /* flame lost channel B error flag */
2941	uint16_t FRLAEF:1; /* frame lost channel A error flag */
2942	uint16_t PCMIEF:1; /* command ignored error flag */
2943	uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
2944	uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
2945	uint16_t MSBEF:1; /* message buffer search error flag */
2946	uint16_t MBUEF:1; /* message buffer utilization error flag */
2947	uint16_t LCKEF:1; /* lock error flag */
2948	uint16_t DBLEF:1; /* double transmit message buffer lock error flag */
2949	uint16_t SBCFEF:1; /* system bus communication failure error flag */
2950	uint16_t FIDEF:1; /* frame ID error flag */
2951	uint16_t DPLEF:1; /* dynamic payload length error flag */
2952	uint16_t SPLEF:1; /* static payload length error flag */
2953	uint16_t NMLEF:1; /* network management length error flag */
2954	uint16_t NMFEF:1; /* network management frame error flag */
2955	uint16_t ILSAEF:1; /* illegal access error flag */
2956	} B;
2957	} CHIERFR_t;
2958	typedef union uMBIVEC {
2959	uint16_t R;
2960	struct {
2961
2962	uint16_t:2;
2963	uint16_t TBIVEC:6; /* transmit buffer interrupt vector */
2964	uint16_t:2;
2965	uint16_t RBIVEC:6; /* receive buffer interrupt vector */
2966	} B;
2967	} MBIVEC_t;
2968
2969	typedef union uPSR0 {
2970	uint16_t R;
2971	struct {
2972	uint16_t ERRMODE:2; /* error mode */
2973	uint16_t SLOTMODE:2; /* slot mode */
2974	uint16_t:1;
2975	uint16_t PROTSTATE:3; /* protocol state */
2976	uint16_t SUBSTATE:4; /* protocol sub state */
2977	uint16_t:1;
2978	uint16_t WAKEUPSTATUS:3; /* wakeup status */
2979	} B;
2980	} PSR0_t;
2981
2982	/* protocol states */
2983	/* protocol sub-states */
2984	/* wakeup status */
2985	typedef union uPSR1 {
2986	uint16_t R;
2987	struct {
2988	uint16_t CSAA:1; /* cold start attempt abort flag */
2989	uint16_t SCP:1; /* cold start path */
2990	uint16_t:1;
2991	uint16_t REMCSAT:5; /* remanining coldstart attempts */
2992	uint16_t CPN:1; /* cold start noise path */
2993	uint16_t HHR:1; /* host halt request pending */
2994	uint16_t FRZ:1; /* freeze occured */
2995	uint16_t APTAC:5; /* allow passive to active counter */
2996	} B;
2997	} PSR1_t;
2998	typedef union uPSR2 {
2999	uint16_t R;
3000	struct {
3001	uint16_t NBVB:1; /* NIT boundary violation on channel B */
3002	uint16_t NSEB:1; /* NIT syntax error on channel B */
3003	uint16_t STCB:1; /* symbol window transmit conflict on channel B */
3004	uint16_t SBVB:1; /* symbol window boundary violation on channel B */
3005	uint16_t SSEB:1; /* symbol window syntax error on channel B */
3006	uint16_t MTB:1; /* media access test symbol MTS received on channel B */
3007	uint16_t NBVA:1; /* NIT boundary violation on channel A */
3008	uint16_t NSEA:1; /* NIT syntax error on channel A */
3009	uint16_t STCA:1; /* symbol window transmit conflict on channel A */
3010	uint16_t SBVA:1; /* symbol window boundary violation on channel A */
3011	uint16_t SSEA:1; /* symbol window syntax error on channel A */
3012	uint16_t MTA:1; /* media access test symbol MTS received on channel A */
3013	uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
3014	} B;
3015	} PSR2_t;
3016	typedef union uPSR3 {
3017	uint16_t R;
3018	struct {
3019	uint16_t:2;
3020	uint16_t WUB:1; /* wakeup symbol received on channel B */
3021	uint16_t ABVB:1; /* aggregated boundary violation on channel B */
3022	uint16_t AACB:1; /* aggregated additional communication on channel B */
3023	uint16_t ACEB:1; /* aggregated content error on channel B */
3024	uint16_t ASEB:1; /* aggregated syntax error on channel B */
3025	uint16_t AVFB:1; /* aggregated valid frame on channel B */
3026	uint16_t:2;
3027	uint16_t WUA:1; /* wakeup symbol received on channel A */
3028	uint16_t ABVA:1; /* aggregated boundary violation on channel A */
3029	uint16_t AACA:1; /* aggregated additional communication on channel A */
3030	uint16_t ACEA:1; /* aggregated content error on channel A */
3031	uint16_t ASEA:1; /* aggregated syntax error on channel A */
3032	uint16_t AVFA:1; /* aggregated valid frame on channel A */
3033	} B;
3034	} PSR3_t;
3035	typedef union uCIFRR {
3036	uint16_t R;
3037	struct {
3038	uint16_t:8;
3039	uint16_t MIFR:1; /* module interrupt flag */
3040	uint16_t PRIFR:1; /* protocol interrupt flag */
3041	uint16_t CHIFR:1; /* CHI interrupt flag */
3042	uint16_t WUPIFR:1; /* wakeup interrupt flag */
3043	uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
3044	uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
3045	uint16_t RBIFR:1; /* receive message buffer interrupt flag */
3046	uint16_t TBIFR:1; /* transmit buffer interrupt flag */
3047	} B;
3048	} CIFRR_t;
3049	typedef union uSYMATOR {
3050	uint16_t R;
3051	struct {
3052	uint16_t:11;
3053	uint16_t TIMEOUT:5; /* system memory time out value */
3054	} B;
3055	} SYMATOR_t;
3056
3057	typedef union uSFCNTR {
3058	uint16_t R;
3059	struct {
3060	uint16_t SFEVB:4; /* sync frames channel B, even cycle */
3061	uint16_t SFEVA:4; /* sync frames channel A, even cycle */
3062	uint16_t SFODB:4; /* sync frames channel B, odd cycle */
3063	uint16_t SFODA:4; /* sync frames channel A, odd cycle */
3064	} B;
3065	} SFCNTR_t;
3066
3067	typedef union uSFTCCSR {
3068	uint16_t R;
3069	struct {
3070	uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
3071	uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
3072	uint16_t CYCNUM:6; /* cycle number */
3073	uint16_t ELKS:1; /* even cycle tables lock status */
3074	uint16_t OLKS:1; /* odd cycle tables lock status */
3075	uint16_t EVAL:1; /* even cycle tables valid */
3076	uint16_t OVAL:1; /* odd cycle tables valid */
3077	uint16_t:1;
3078	uint16_t OPT:1; /one pair trigger /
3079	uint16_t SDVEN:1; /* sync frame deviation table enable */
3080	uint16_t SIDEN:1; /* sync frame ID table enable */
3081	} B;
3082	} SFTCCSR_t;
3083	typedef union uSFIDRFR {
3084	uint16_t R;
3085	struct {
3086	uint16_t:6;
3087	uint16_t SYNFRID:10; /* sync frame rejection ID */
3088	} B;
3089	} SFIDRFR_t;
3090
3091	typedef union uTICCR {
3092	uint16_t R;
3093	struct {
3094	uint16_t:2;
3095	uint16_t T2CFG:1; /* timer 2 configuration */
3096	uint16_t T2REP:1; /* timer 2 repetitive mode */
3097	uint16_t:1;
3098	uint16_t T2SP:1; /* timer 2 stop */
3099	uint16_t T2TR:1; /* timer 2 trigger */
3100	uint16_t T2ST:1; /* timer 2 state */
3101	uint16_t:3;
3102	uint16_t T1REP:1; /* timer 1 repetitive mode */
3103	uint16_t:1;
3104	uint16_t T1SP:1; /* timer 1 stop */
3105	uint16_t T1TR:1; /* timer 1 trigger */
3106	uint16_t T1ST:1; /* timer 1 state */
3107
3108	} B;
3109	} TICCR_t;
3110	typedef union uTI1CYSR {
3111	uint16_t R;
3112	struct {
3113	uint16_t:2;
3114	uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
3115	uint16_t:2;
3116	uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
3117
3118	} B;
3119	} TI1CYSR_t;
3120
3121	typedef union uSSSR {
3122	uint16_t R;
3123	struct {
3124	uint16_t WMD:1; /* write mode */
3125	uint16_t:1;
3126	uint16_t SEL:2; /* static slot number */
3127	uint16_t:1;
3128	uint16_t SLOTNUMBER:11; /* selector */
3129	} B;
3130	} SSSR_t;
3131
3132	typedef union uSSCCR {
3133	uint16_t R;
3134	struct {
3135	uint16_t WMD:1; /* write mode */
3136	uint16_t:1;
3137	uint16_t SEL:2; /* selector */
3138	uint16_t:1;
3139	uint16_t CNTCFG:2; /* counter configuration */
3140	uint16_t MCY:1; /* multi cycle selection */
3141	uint16_t VFR:1; /* valid frame selection */
3142	uint16_t SYF:1; /* sync frame selection */
3143	uint16_t NUF:1; /* null frame selection */
3144	uint16_t SUF:1; /* startup frame selection */
3145	uint16_t STATUSMASK:4; /* slot status mask */
3146	} B;
3147	} SSCCR_t;
3148	typedef union uSSR {
3149	uint16_t R;
3150	struct {
3151	uint16_t VFB:1; /* valid frame on channel B */
3152	uint16_t SYB:1; /* valid sync frame on channel B */
3153	uint16_t NFB:1; /* valid null frame on channel B */
3154	uint16_t SUB:1; /* valid startup frame on channel B */
3155	uint16_t SEB:1; /* syntax error on channel B */
3156	uint16_t CEB:1; /* content error on channel B */
3157	uint16_t BVB:1; /* boundary violation on channel B */
3158	uint16_t TCB:1; /* tx conflict on channel B */
3159	uint16_t VFA:1; /* valid frame on channel A */
3160	uint16_t SYA:1; /* valid sync frame on channel A */
3161	uint16_t NFA:1; /* valid null frame on channel A */
3162	uint16_t SUA:1; /* valid startup frame on channel A */
3163	uint16_t SEA:1; /* syntax error on channel A */
3164	uint16_t CEA:1; /* content error on channel A */
3165	uint16_t BVA:1; /* boundary violation on channel A */
3166	uint16_t TCA:1; /* tx conflict on channel A */
3167	} B;
3168	} SSR_t;
3169	typedef union uMTSCFR {
3170	uint16_t R;
3171	struct {
3172	uint16_t MTE:1; /* media access test symbol transmission enable */
3173	uint16_t:1;
3174	uint16_t CYCCNTMSK:6; /* cycle counter mask */
3175	uint16_t:2;
3176	uint16_t CYCCNTVAL:6; /* cycle counter value */
3177	} B;
3178	} MTSCFR_t;
3179
3180	typedef union uRSBIR {
3181	uint16_t R;
3182	struct {
3183	uint16_t WMD:1; /* write mode */
3184	uint16_t:1;
3185	uint16_t SEL:2; /* selector */
3186	uint16_t:5;
3187	uint16_t RSBIDX:7; /* receive shadow buffer index */
3188	} B;
3189	} RSBIR_t;
3190
3191	typedef union uRFDSR {
3192	uint16_t R;
3193	struct {
3194	uint16_t FIFODEPTH:8; /* fifo depth */
3195	uint16_t:1;
3196	uint16_t ENTRYSIZE:7; /* entry size */
3197	} B;
3198	} RFDSR_t;
3199
3200	typedef union uRFRFCFR {
3201	uint16_t R;
3202	struct {
3203	uint16_t WMD:1; /* write mode */
3204	uint16_t IBD:1; /* interval boundary */
3205	uint16_t SEL:2; /* filter number */
3206	uint16_t:1;
3207	uint16_t SID:11; /* slot ID */
3208	} B;
3209	} RFRFCFR_t;
3210
3211	typedef union uRFRFCTR {
3212	uint16_t R;
3213	struct {
3214	uint16_t:4;
3215	uint16_t F3MD:1; /* filter mode */
3216	uint16_t F2MD:1; /* filter mode */
3217	uint16_t F1MD:1; /* filter mode */
3218	uint16_t F0MD:1; /* filter mode */
3219	uint16_t:4;
3220	uint16_t F3EN:1; /* filter enable */
3221	uint16_t F2EN:1; /* filter enable */
3222	uint16_t F1EN:1; /* filter enable */
3223	uint16_t F0EN:1; /* filter enable */
3224	} B;
3225	} RFRFCTR_t;
3226	typedef union uPCR0 {
3227	uint16_t R;
3228	struct {
3229	uint16_t ACTION_POINT_OFFSET:6;
3230	uint16_t STATIC_SLOT_LENGTH:10;
3231	} B;
3232	} PCR0_t;
3233
3234	typedef union uPCR1 {
3235	uint16_t R;
3236	struct {
3237	uint16_t:2;
3238	uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3239	} B;
3240	} PCR1_t;
3241
3242	typedef union uPCR2 {
3243	uint16_t R;
3244	struct {
3245	uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3246	uint16_t NUMBER_OF_STATIC_SLOTS:10;
3247	} B;
3248	} PCR2_t;
3249
3250	typedef union uPCR3 {
3251	uint16_t R;
3252	struct {
3253	uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3254	uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3255	uint16_t COLDSTART_ATTEMPTS:5;
3256	} B;
3257	} PCR3_t;
3258
3259	typedef union uPCR4 {
3260	uint16_t R;
3261	struct {
3262	uint16_t CAS_RX_LOW_MAX:7;
3263	uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3264	} B;
3265	} PCR4_t;
3266
3267	typedef union uPCR5 {
3268	uint16_t R;
3269	struct {
3270	uint16_t TSS_TRANSMITTER:4;
3271	uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3272	uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3273	} B;
3274	} PCR5_t;
3275
3276	typedef union uPCR6 {
3277	uint16_t R;
3278	struct {
3279	uint16_t:1;
3280	uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3281	uint16_t MACRO_INITIAL_OFFSET_A:7;
3282	} B;
3283	} PCR6_t;
3284
3285	typedef union uPCR7 {
3286	uint16_t R;
3287	struct {
3288	uint16_t DECODING_CORRECTION_B:9;
3289	uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3290	} B;
3291	} PCR7_t;
3292
3293	typedef union uPCR8 {
3294	uint16_t R;
3295	struct {
3296	uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3297	uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3298	uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3299	} B;
3300	} PCR8_t;
3301
3302	typedef union uPCR9 {
3303	uint16_t R;
3304	struct {
3305	uint16_t MINISLOT_EXISTS:1;
3306	uint16_t SYMBOL_WINDOW_EXISTS:1;
3307	uint16_t OFFSET_CORRECTION_OUT:14;
3308	} B;
3309	} PCR9_t;
3310
3311	typedef union uPCR10 {
3312	uint16_t R;
3313	struct {
3314	uint16_t SINGLE_SLOT_ENABLED:1;
3315	uint16_t WAKEUP_CHANNEL:1;
3316	uint16_t MACRO_PER_CYCLE:14;
3317	} B;
3318	} PCR10_t;
3319
3320	typedef union uPCR11 {
3321	uint16_t R;
3322	struct {
3323	uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
3324	uint16_t KEY_SLOT_USED_FOR_SYNC:1;
3325	uint16_t OFFSET_CORRECTION_START:14;
3326	} B;
3327	} PCR11_t;
3328
3329	typedef union uPCR12 {
3330	uint16_t R;
3331	struct {
3332	uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
3333	uint16_t KEY_SLOT_HEADER_CRC:11;
3334	} B;
3335	} PCR12_t;
3336
3337	typedef union uPCR13 {
3338	uint16_t R;
3339	struct {
3340	uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
3341	uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
3342	} B;
3343	} PCR13_t;
3344
3345	typedef union uPCR14 {
3346	uint16_t R;
3347	struct {
3348	uint16_t RATE_CORRECTION_OUT:11;
3349	uint16_t LISTEN_TIMEOUT_H:5;
3350	} B;
3351	} PCR14_t;
3352
3353	typedef union uPCR15 {
3354	uint16_t R;
3355	struct {
3356	uint16_t LISTEN_TIMEOUT_L:16;
3357	} B;
3358	} PCR15_t;
3359
3360	typedef union uPCR16 {
3361	uint16_t R;
3362	struct {
3363	uint16_t MACRO_INITIAL_OFFSET_B:7;
3364	uint16_t NOISE_LISTEN_TIMEOUT_H:9;
3365	} B;
3366	} PCR16_t;
3367
3368	typedef union uPCR17 {
3369	uint16_t R;
3370	struct {
3371	uint16_t NOISE_LISTEN_TIMEOUT_L:16;
3372	} B;
3373	} PCR17_t;
3374
3375	typedef union uPCR18 {
3376	uint16_t R;
3377	struct {
3378	uint16_t WAKEUP_PATTERN:6;
3379	uint16_t KEY_SLOT_ID:10;
3380	} B;
3381	} PCR18_t;
3382
3383	typedef union uPCR19 {
3384	uint16_t R;
3385	struct {
3386	uint16_t DECODING_CORRECTION_A:9;
3387	uint16_t PAYLOAD_LENGTH_STATIC:7;
3388	} B;
3389	} PCR19_t;
3390
3391	typedef union uPCR20 {
3392	uint16_t R;
3393	struct {
3394	uint16_t MICRO_INITIAL_OFFSET_B:8;
3395	uint16_t MICRO_INITIAL_OFFSET_A:8;
3396	} B;
3397	} PCR20_t;
3398
3399	typedef union uPCR21 {
3400	uint16_t R;
3401	struct {
3402	uint16_t EXTERN_RATE_CORRECTION:3;
3403	uint16_t LATEST_TX:13;
3404	} B;
3405	} PCR21_t;
3406
3407	typedef union uPCR22 {
3408	uint16_t R;
3409	struct {
3410	uint16_t:1;
3411	uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
3412	uint16_t MICRO_PER_CYCLE_H:4;
3413	} B;
3414	} PCR22_t;
3415
3416	typedef union uPCR23 {
3417	uint16_t R;
3418	struct {
3419	uint16_t micro_per_cycle_l:16;
3420	} B;
3421	} PCR23_t;
3422
3423	typedef union uPCR24 {
3424	uint16_t R;
3425	struct {
3426	uint16_t CLUSTER_DRIFT_DAMPING:5;
3427	uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
3428	uint16_t MICRO_PER_CYCLE_MIN_H:4;
3429	} B;
3430	} PCR24_t;
3431
3432	typedef union uPCR25 {
3433	uint16_t R;
3434	struct {
3435	uint16_t MICRO_PER_CYCLE_MIN_L:16;
3436	} B;
3437	} PCR25_t;
3438
3439	typedef union uPCR26 {
3440	uint16_t R;
3441	struct {
3442	uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
3443	uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
3444	uint16_t MICRO_PER_CYCLE_MAX_H:4;
3445	} B;
3446	} PCR26_t;
3447
3448	typedef union uPCR27 {
3449	uint16_t R;
3450	struct {
3451	uint16_t MICRO_PER_CYCLE_MAX_L:16;
3452	} B;
3453	} PCR27_t;
3454
3455	typedef union uPCR28 {
3456	uint16_t R;
3457	struct {
3458	uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
3459	uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
3460	} B;
3461	} PCR28_t;
3462
3463	typedef union uPCR29 {
3464	uint16_t R;
3465	struct {
3466	uint16_t EXTERN_OFFSET_CORRECTION:3;
3467	uint16_t MINISLOTS_MAX:13;
3468	} B;
3469	} PCR29_t;
3470
3471	typedef union uPCR30 {
3472	uint16_t R;
3473	struct {
3474	uint16_t:12;
3475	uint16_t SYNC_NODE_MAX:4;
3476	} B;
3477	} PCR30_t;
3478
3479	typedef struct uMSG_BUFF_CCS {
3480	union {
3481	uint16_t R;
3482	struct {
3483	uint16_t:1;
3484	uint16_t MCM:1; /* message buffer commit mode */
3485	uint16_t MBT:1; /* message buffer type */
3486	uint16_t MTD:1; /* message buffer direction */
3487	uint16_t CMT:1; /* commit for transmission */
3488	uint16_t EDT:1; /* enable / disable trigger */
3489	uint16_t LCKT:1; /* lock request trigger */
3490	uint16_t MBIE:1; /* message buffer interrupt enable */
3491	uint16_t:3;
3492	uint16_t DUP:1; /* data updated */
3493	uint16_t DVAL:1; /* data valid */
3494	uint16_t EDS:1; /* lock status */
3495	uint16_t LCKS:1; /* enable / disable status */
3496	uint16_t MBIF:1; /* message buffer interrupt flag */
3497	} B;
3498	} MBCCSR;
3499	union {
3500	uint16_t R;
3501	struct {
3502	uint16_t MTM:1; /* message buffer transmission mode */
3503	uint16_t CHNLA:1; /* channel assignement */
3504	uint16_t CHNLB:1; /* channel assignement */
3505	uint16_t CCFE:1; /* cycle counter filter enable */
3506	uint16_t CCFMSK:6; /* cycle counter filter mask */
3507	uint16_t CCFVAL:6; /* cycle counter filter value */
3508	} B;
3509	} MBCCFR;
3510	union {
3511	uint16_t R;
3512	struct {
3513	uint16_t:5;
3514	uint16_t FID:11; /* frame ID */
3515	} B;
3516	} MBFIDR;
3517
3518	union {
3519	uint16_t R;
3520	struct {
3521	uint16_t:9;
3522	uint16_t MBIDX:7; /* message buffer index */
3523	} B;
3524	} MBIDXR;
3525	} MSG_BUFF_CCS_t;
3526	typedef union uSYSBADHR {
3527	uint16_t R;
3528	} SYSBADHR_t;
3529	typedef union uSYSBADLR {
3530	uint16_t R;
3531	} SYSBADLR_t;
3532	typedef union uPADR {
3533	uint16_t R;
3534	} PADR_t;
3535	typedef union uPDAR {
3536	uint16_t R;
3537	} PDAR_t;
3538	typedef union uCASERCR {
3539	uint16_t R;
3540	} CASERCR_t;
3541	typedef union uCBSERCR {
3542	uint16_t R;
3543	} CBSERCR_t;
3544	typedef union uCYCTR {
3545	uint16_t R;
3546	} CYCTR_t;
3547	typedef union uMTCTR {
3548	uint16_t R;
3549	} MTCTR_t;
3550	typedef union uSLTCTAR {
3551	uint16_t R;
3552	} SLTCTAR_t;
3553	typedef union uSLTCTBR {
3554	uint16_t R;
3555	} SLTCTBR_t;
3556	typedef union uRTCORVR {
3557	uint16_t R;
3558	} RTCORVR_t;
3559	typedef union uOFCORVR {
3560	uint16_t R;
3561	} OFCORVR_t;
3562	typedef union uSFTOR {
3563	uint16_t R;
3564	} SFTOR_t;
3565	typedef union uSFIDAFVR {
3566	uint16_t R;
3567	} SFIDAFVR_t;
3568	typedef union uSFIDAFMR {
3569	uint16_t R;
3570	} SFIDAFMR_t;
3571	typedef union uNMVR {
3572	uint16_t R;
3573	} NMVR_t;
3574	typedef union uNMVLR {
3575	uint16_t R;
3576	} NMVLR_t;
3577	typedef union uT1MTOR {
3578	uint16_t R;
3579	} T1MTOR_t;
3580	typedef union uTI2CR0 {
3581	uint16_t R;
3582	} TI2CR0_t;
3583	typedef union uTI2CR1 {
3584	uint16_t R;
3585	} TI2CR1_t;
3586	typedef union uSSCR {
3587	uint16_t R;
3588	} SSCR_t;
3589	typedef union uRFSR {
3590	uint16_t R;
3591	} RFSR_t;
3592	typedef union uRFSIR {
3593	uint16_t R;
3594	} RFSIR_t;
3595	typedef union uRFARIR {
3596	uint16_t R;
3597	} RFARIR_t;
3598	typedef union uRFBRIR {
3599	uint16_t R;
3600	} RFBRIR_t;
3601	typedef union uRFMIDAFVR {
3602	uint16_t R;
3603	} RFMIDAFVR_t;
3604	typedef union uRFMIAFMR {
3605	uint16_t R;
3606	} RFMIAFMR_t;
3607	typedef union uRFFIDRFVR {
3608	uint16_t R;
3609	} RFFIDRFVR_t;
3610	typedef union uRFFIDRFMR {
3611	uint16_t R;
3612	} RFFIDRFMR_t;
3613	typedef union uLDTXSLAR {
3614	uint16_t R;
3615	} LDTXSLAR_t;
3616	typedef union uLDTXSLBR {
3617	uint16_t R;
3618	} LDTXSLBR_t;
3619
3620	typedef struct FR_tag {
3621	volatile MVR_t MVR; /module version register //0 /
3622	volatile MCR_t MCR; /module configuration register //2 /
3623	volatile SYSBADHR_t SYSBADHR; /system memory base address high register //4 /
3624	volatile SYSBADLR_t SYSBADLR; /system memory base address low register //6 /
3625	volatile STBSCR_t STBSCR; /strobe signal control register //8 /
3626	uint16_t reserved0[1]; /A /
3627	volatile MBDSR_t MBDSR; /message buffer data size register //C /
3628	volatile MBSSUTR_t MBSSUTR; /message buffer segment size and utilization register //E /
3629	uint16_t reserved1[1]; /10 /
3630	uint16_t reserved2[1]; /12 /
3631	volatile POCR_t POCR; /Protocol operation control register //14 /
3632	volatile GIFER_t GIFER; /global interrupt flag and enable register //16 /
3633	volatile PIFR0_t PIFR0; /protocol interrupt flag register 0 //18 /
3634	volatile PIFR1_t PIFR1; /protocol interrupt flag register 1 //1A /
3635	volatile PIER0_t PIER0; /protocol interrupt enable register 0 //1C /
3636	volatile PIER1_t PIER1; /protocol interrupt enable register 1 //1E /
3637	volatile CHIERFR_t CHIERFR; /CHI error flag register //20 /
3638	volatile MBIVEC_t MBIVEC; /message buffer interrupt vector register //22 /
3639	volatile CASERCR_t CASERCR; /channel A status error counter register //24 /
3640	volatile CBSERCR_t CBSERCR; /channel B status error counter register //26 /
3641	volatile PSR0_t PSR0; /protocol status register 0 //28 /
3642	volatile PSR1_t PSR1; /protocol status register 1 //2A /
3643	volatile PSR2_t PSR2; /protocol status register 2 //2C /
3644	volatile PSR3_t PSR3; /protocol status register 3 //2E /
3645	volatile MTCTR_t MTCTR; /macrotick counter register //30 /
3646	volatile CYCTR_t CYCTR; /cycle counter register //32 /
3647	volatile SLTCTAR_t SLTCTAR; /slot counter channel A register //34 /
3648	volatile SLTCTBR_t SLTCTBR; /slot counter channel B register //36 /
3649	volatile RTCORVR_t RTCORVR; /rate correction value register //38 /
3650	volatile OFCORVR_t OFCORVR; /offset correction value register //3A /
3651	volatile CIFRR_t CIFRR; /combined interrupt flag register //3C /
3652	volatile SYMATOR_t SYMATOR; /system memory acess time-out register //3E /
3653	volatile SFCNTR_t SFCNTR; /sync frame counter register //40 /
3654	volatile SFTOR_t SFTOR; /sync frame table offset register //42 /
3655	volatile SFTCCSR_t SFTCCSR; /sync frame table configuration, control, status register //44 /
3656	volatile SFIDRFR_t SFIDRFR; /sync frame ID rejection filter register //46 /
3657	volatile SFIDAFVR_t SFIDAFVR; /sync frame ID acceptance filter value regiater //48 /
3658	volatile SFIDAFMR_t SFIDAFMR; /sync frame ID acceptance filter mask register //4A /
3659	volatile NMVR_t NMVR[6]; /network management vector registers (12 bytes) //4C /
3660	volatile NMVLR_t NMVLR; /network management vector length register //58 /
3661	volatile TICCR_t TICCR; /timer configuration and control register //5A /
3662	volatile TI1CYSR_t TI1CYSR; /timer 1 cycle set register //5C /
3663	volatile T1MTOR_t T1MTOR; /timer 1 macrotick offset register //5E /
3664	volatile TI2CR0_t TI2CR0; /timer 2 configuration register 0 //60 /
3665	volatile TI2CR1_t TI2CR1; /timer 2 configuration register 1 //62 /
3666	volatile SSSR_t SSSR; /slot status selection register //64 /
3667	volatile SSCCR_t SSCCR; /slot status counter condition register //66 /
3668	volatile SSR_t SSR[8]; /slot status registers 0-7 //68 /
3669	volatile SSCR_t SSCR[4]; /slot status counter registers 0-3 //78 /
3670	volatile MTSCFR_t MTSACFR; /mts a config register //80 /
3671	volatile MTSCFR_t MTSBCFR; /mts b config register //82 /
3672	volatile RSBIR_t RSBIR; /receive shadow buffer index register //84 /
3673	volatile RFSR_t RFSR; /receive fifo selection register //86 /
3674	volatile RFSIR_t RFSIR; /receive fifo start index register //88 /
3675	volatile RFDSR_t RFDSR; /receive fifo depth and size register //8A /
3676	volatile RFARIR_t RFARIR; /receive fifo a read index register //8C /
3677	volatile RFBRIR_t RFBRIR; /receive fifo b read index register //8E /
3678	volatile RFMIDAFVR_t RFMIDAFVR; /receive fifo message ID acceptance filter value register //90 /
3679	volatile RFMIAFMR_t RFMIAFMR; /receive fifo message ID acceptance filter mask register //92 /
3680	volatile RFFIDRFVR_t RFFIDRFVR; /receive fifo frame ID rejection filter value register //94 /
3681	volatile RFFIDRFMR_t RFFIDRFMR; /receive fifo frame ID rejection filter mask register //96 /
3682	volatile RFRFCFR_t RFRFCFR; /receive fifo range filter configuration register //98 /
3683	volatile RFRFCTR_t RFRFCTR; /receive fifo range filter control register //9A /
3684	volatile LDTXSLAR_t LDTXSLAR; /last dynamic transmit slot channel A register //9C /
3685	volatile LDTXSLBR_t LDTXSLBR; /last dynamic transmit slot channel B register //9E /
3686	volatile PCR0_t PCR0; /protocol configuration register 0 //A0 /
3687	volatile PCR1_t PCR1; /protocol configuration register 1 //A2 /
3688	volatile PCR2_t PCR2; /protocol configuration register 2 //A4 /
3689	volatile PCR3_t PCR3; /protocol configuration register 3 //A6 /
3690	volatile PCR4_t PCR4; /protocol configuration register 4 //A8 /
3691	volatile PCR5_t PCR5; /protocol configuration register 5 //AA /
3692	volatile PCR6_t PCR6; /protocol configuration register 6 //AC /
3693	volatile PCR7_t PCR7; /protocol configuration register 7 //AE /
3694	volatile PCR8_t PCR8; /protocol configuration register 8 //B0 /
3695	volatile PCR9_t PCR9; /protocol configuration register 9 //B2 /
3696	volatile PCR10_t PCR10; /protocol configuration register 10 //B4 /
3697	volatile PCR11_t PCR11; /protocol configuration register 11 //B6 /
3698	volatile PCR12_t PCR12; /protocol configuration register 12 //B8 /
3699	volatile PCR13_t PCR13; /protocol configuration register 13 //BA /
3700	volatile PCR14_t PCR14; /protocol configuration register 14 //BC /
3701	volatile PCR15_t PCR15; /protocol configuration register 15 //BE /
3702	volatile PCR16_t PCR16; /protocol configuration register 16 //C0 /
3703	volatile PCR17_t PCR17; /protocol configuration register 17 //C2 /
3704	volatile PCR18_t PCR18; /protocol configuration register 18 //C4 /
3705	volatile PCR19_t PCR19; /protocol configuration register 19 //C6 /
3706	volatile PCR20_t PCR20; /protocol configuration register 20 //C8 /
3707	volatile PCR21_t PCR21; /protocol configuration register 21 //CA /
3708	volatile PCR22_t PCR22; /protocol configuration register 22 //CC /
3709	volatile PCR23_t PCR23; /protocol configuration register 23 //CE /
3710	volatile PCR24_t PCR24; /protocol configuration register 24 //D0 /
3711	volatile PCR25_t PCR25; /protocol configuration register 25 //D2 /
3712	volatile PCR26_t PCR26; /protocol configuration register 26 //D4 /
3713	volatile PCR27_t PCR27; /protocol configuration register 27 //D6 /
3714	volatile PCR28_t PCR28; /protocol configuration register 28 //D8 /
3715	volatile PCR29_t PCR29; /protocol configuration register 29 //DA /
3716	volatile PCR30_t PCR30; /protocol configuration register 30 //DC /
3717	uint16_t reserved3[17];
3718	volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 //100 */
3719	} FR_tag_t;
3720
3721	typedef union uF_HEADER /* frame header */
3722	{
3723	struct {
3724	uint16_t:5;
3725	uint16_t HDCRC:11; /* Header CRC */
3726	uint16_t:2;
3727	uint16_t CYCCNT:6; /* Cycle Count */
3728	uint16_t:1;
3729	uint16_t PLDLEN:7; /* Payload Length */
3730	uint16_t:1;
3731	uint16_t PPI:1; /* Payload Preamble Indicator */
3732	uint16_t NUF:1; /* Null Frame Indicator */
3733	uint16_t SYF:1; /* Sync Frame Indicator */
3734	uint16_t SUF:1; /* Startup Frame Indicator */
3735	uint16_t FID:11; /* Frame ID */
3736	} B;
3737	uint16_t WORDS[3];
3738	} F_HEADER_t;
3739	typedef union uS_STSTUS /* slot status */
3740	{
3741	struct {
3742	uint16_t VFB:1; /* Valid Frame on channel B */
3743	uint16_t SYB:1; /* Sync Frame Indicator channel B */
3744	uint16_t NFB:1; /* Null Frame Indicator channel B */
3745	uint16_t SUB:1; /* Startup Frame Indicator channel B */
3746	uint16_t SEB:1; /* Syntax Error on channel B */
3747	uint16_t CEB:1; /* Content Error on channel B */
3748	uint16_t BVB:1; /* Boundary Violation on channel B */
3749	uint16_t CH:1; /* Channel */
3750	uint16_t VFA:1; /* Valid Frame on channel A */
3751	uint16_t SYA:1; /* Sync Frame Indicator channel A */
3752	uint16_t NFA:1; /* Null Frame Indicator channel A */
3753	uint16_t SUA:1; /* Startup Frame Indicator channel A */
3754	uint16_t SEA:1; /* Syntax Error on channel A */
3755	uint16_t CEA:1; /* Content Error on channel A */
3756	uint16_t BVA:1; /* Boundary Violation on channel A */
3757	uint16_t:1;
3758	} RX;
3759	struct {
3760	uint16_t VFB:1; /* Valid Frame on channel B */
3761	uint16_t SYB:1; /* Sync Frame Indicator channel B */
3762	uint16_t NFB:1; /* Null Frame Indicator channel B */
3763	uint16_t SUB:1; /* Startup Frame Indicator channel B */
3764	uint16_t SEB:1; /* Syntax Error on channel B */
3765	uint16_t CEB:1; /* Content Error on channel B */
3766	uint16_t BVB:1; /* Boundary Violation on channel B */
3767	uint16_t TCB:1; /* Tx Conflict on channel B */
3768	uint16_t VFA:1; /* Valid Frame on channel A */
3769	uint16_t SYA:1; /* Sync Frame Indicator channel A */
3770	uint16_t NFA:1; /* Null Frame Indicator channel A */
3771	uint16_t SUA:1; /* Startup Frame Indicator channel A */
3772	uint16_t SEA:1; /* Syntax Error on channel A */
3773	uint16_t CEA:1; /* Content Error on channel A */
3774	uint16_t BVA:1; /* Boundary Violation on channel A */
3775	uint16_t TCA:1; /* Tx Conflict on channel A */
3776	} TX;
3777	uint16_t R;
3778	} S_STATUS_t;
3779
3780	typedef struct uMB_HEADER /* message buffer header */
3781	{
3782	F_HEADER_t FRAME_HEADER;
3783	uint16_t DATA_OFFSET;
3784	S_STATUS_t SLOT_STATUS;
3785	} MB_HEADER_t;
3786	/****************************************************************************/
3787	/* MODULE : MLB */
3788	/****************************************************************************/
3789	struct MLB_tag {
3790
3791	union { /* MLB Module Configuration Register */
3792	uint32_t R;
3793	struct {
3794	uint32_t MDIS:1;
3795	uint32_t:15;
3796	uint32_t MDATOBSE:1;
3797	uint32_t MSIGOBS:1;
3798	uint32_t MSLOTE:1;
3799	uint32_t:2;
3800	uint32_t MSVRQIE:1;
3801	uint32_t MDATRQE:1;
3802	uint32_t:2;
3803	uint32_t MSVRQDL:3;
3804	uint32_t MSVRQCIE:1;
3805	uint32_t MIFSEL:1;
3806	uint32_t MSBFEPOL:1;
3807	uint32_t MDBFEPOL:1;
3808	} B;
3809	} MCR;
3810
3811	union { /* MLB Blank Register */
3812	uint32_t R;
3813	struct {
3814	uint32_t:31;
3815	uint32_t BLANK:1;
3816	} B;
3817	} MBR;
3818
3819	union { /* MLB Status Register */
3820	uint32_t R;
3821	struct {
3822	uint32_t:29;
3823	uint32_t MDATRQS:1;
3824	uint32_t MSYSS:1;
3825	uint32_t MSVRQS:1;
3826	} B;
3827	} MSR;
3828
3829	union { /* RX Control Channel Address Register */
3830	uint32_t R;
3831	struct {
3832	uint32_t RXCCHA_ACEN:1;
3833	uint32_t:25;
3834	uint32_t RXCCHA:5;
3835	uint32_t:1;
3836	} B;
3837	} RXCCHAR;
3838
3839	union { /* RX Async Channel Address Register */
3840	uint32_t R;
3841	struct {
3842	uint32_t RXACHA_ACEN:1;
3843	uint32_t:25;
3844	uint32_t RXACHA:5;
3845	uint32_t:1;
3846	} B;
3847	} RXACHAR;
3848
3849	union { /* TX Control Channel Address Register */
3850	uint32_t R;
3851	struct {
3852	uint32_t TXCCHA_ACEN:1;
3853	uint32_t:25;
3854	uint32_t TXCCHA:5;
3855	uint32_t:1;
3856	} B;
3857	} TXCCHAR;
3858
3859	union { /* TX Async Channel Address Register */
3860	uint32_t R;
3861	struct {
3862	uint32_t TXACHA_ACEN:1;
3863	uint32_t:25;
3864	uint32_t TXACHA:5;
3865	uint32_t:1;
3866	} B;
3867	} TXACHAR;
3868
3869	union { /* TX Sync Channel Address Register */
3870	uint32_t R;
3871	struct {
3872	uint32_t TXSCHA_ACEN:1;
3873	uint32_t:25;
3874	uint32_t TXSCHA:5;
3875	uint32_t:1;
3876	} B;
3877	} TXSCHAR;
3878
3879	union { /* TX Sync Channel Address Mask Register */
3880	uint32_t R;
3881	struct {
3882	uint32_t:26;
3883	uint32_t TXSCHAM:5;
3884	uint32_t:1;
3885	} B;
3886	} TXSCHAMR;
3887
3888	union { /* Clock Adjust Control Register */
3889	uint32_t R;
3890	struct {
3891	uint32_t:16;
3892	uint32_t PDLY:16;
3893	} B;
3894	} CLKACR;
3895
3896	union { /* RX Isochronous Channel Address Register */
3897	uint32_t R;
3898	struct {
3899	uint32_t RXICHA_ACEN:1;
3900	uint32_t:25;
3901	uint32_t RXICHA:5;
3902	uint32_t:1;
3903	} B;
3904	} RXICHAR;
3905
3906	union { /* TX Isochronous Channel Address Register */
3907	uint32_t R;
3908	struct {
3909	uint32_t TXICHA_ACEN:1;
3910	uint32_t:25;
3911	uint32_t TXICHA:5;
3912	uint32_t:1;
3913	} B;
3914	} TXICHAR;
3915
3916	};
3917
3918	/* Define memories */
3919
3920	#define SRAM_START 0x40000000UL
3921	#define SRAM_SIZE 0x14000UL
3922	#define SRAM_END 0x40013FFFUL
3923
3924	#define FLASH_START 0x0UL
3925	#define FLASH_SIZE 0x180000UL
3926	#define FLASH_END 0x17FFFFUL
3927
3928	/* Define instances of modules */
3929	#define SEMA4 ((volatile struct SEMA4_tag ) 0xFFF10000UL)
3930	#define MPU ((volatile struct MPU_tag ) 0xFFF14000UL)
3931	#define MCM ((volatile struct MCM_tag ) 0xFFF40000UL)
3932	#define EDMA ((volatile struct EDMA_tag ) 0xFFF44000UL)
3933	#define INTC ((volatile struct INTC_tag ) 0xFFF48000UL)
3934	#define EQADC ((volatile struct EQADC_tag ) 0xFFF80000UL)
3935	#define MLB ((volatile struct MLB_tag ) 0xFFF84000UL)
3936	#define I2C ((volatile struct I2C_tag ) 0xFFF88000UL)
3937	#define DSPI_A ((volatile struct DSPI_tag ) 0xFFF90000UL)
3938	#define DSPI_B ((volatile struct DSPI_tag ) 0xFFF94000UL)
3939	#define DSPI_C ((volatile struct DSPI_tag ) 0xFFF98000UL)
3940	#define DSPI_D ((volatile struct DSPI_tag ) 0xFFF9C000UL)
3941	#define ESCI_A ((volatile struct ESCI_tag ) 0xFFFA0000UL)
3942	#define ESCI_B ((volatile struct ESCI_tag ) 0xFFFA4000UL)
3943	#define ESCI_C ((volatile struct ESCI_tag ) 0xFFFA8000UL)
3944	#define ESCI_D ((volatile struct ESCI_tag ) 0xFFFAC000UL)
3945	#define ESCI_E ((volatile struct ESCI_tag ) 0xFFFB0000UL)
3946	#define ESCI_F ((volatile struct ESCI_tag ) 0xFFFB4000UL)
3947	#define ESCI_G ((volatile struct ESCI_tag ) 0xFFFB8000UL)
3948	#define ESCI_H ((volatile struct ESCI_tag ) 0xFFFBC000UL)
3949	#define CAN_A ((volatile struct FLEXCAN_tag ) 0xFFFC0000UL)
3950	#define CAN_B ((volatile struct FLEXCAN_tag ) 0xFFFC4000UL)
3951	#define CAN_C ((volatile struct FLEXCAN_tag ) 0xFFFC8000UL)
3952	#define CAN_D ((volatile struct FLEXCAN_tag ) 0xFFFCC000UL)
3953	#define CAN_E ((volatile struct FLEXCAN_tag ) 0xFFFD0000UL)
3954	#define CAN_F ((volatile struct FLEXCAN_tag ) 0xFFFD4000UL)
3955	#define FR ((volatile struct FR_tag ) 0xFFFD8000UL)
3956	#define DMAMUX ((volatile struct DMAMUX_tag ) 0xFFFDC000UL)
3957	#define PIT ((volatile struct PIT_tag ) 0xFFFE0000UL)
3958	#define EMIOS ((volatile struct EMIOS_tag ) 0xFFFE4000UL)
3959	#define SIU ((volatile struct SIU_tag ) 0xFFFE8000UL)
3960	#define CRP ((volatile struct CRP_tag ) 0xFFFEC000UL)
3961	#define FMPLL ((volatile struct FMPLL_tag ) 0xFFFF0000UL)
3962	#define EBI ((volatile struct EBI_tag ) 0xFFFF4000UL)
3963	#define FLASH ((volatile struct FLASH_tag ) 0xFFFF8000UL)
3964
3965	#ifdef __MWERKS__
3966	#pragma pop
3967	#endif
3968
3969	#ifdef __cplusplus
3970	}
3971	#endif
3972	#endif /* ifdef _MPC5510_H */
3973	/*********************************************************************
3974	*
3975	* Copyright:
3976	* Freescale Semiconductor, INC. All Rights Reserved.
3977	* You are hereby granted a copyright license to use, modify, and
3978	* distribute the SOFTWARE so long as this entire notice is
3979	* retained without alteration in any modified and/or redistributed
3980	* versions, and that such modified versions are clearly identified
3981	* as such. No licenses are granted by implication, estoppel or
3982	* otherwise under any patents or trademarks of Freescale
3983	* Semiconductor, Inc. This software is provided on an "AS IS"
3984	* basis and without warranty.
3985	*
3986	* To the maximum extent permitted by applicable law, Freescale
3987	* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
3988	* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
3989	* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
3990	* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
3991	* AND ANY ACCOMPANYING WRITTEN MATERIALS.
3992	*
3993	* To the maximum extent permitted by applicable law, IN NO EVENT
3994	* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
3995	* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
3996	* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
3997	* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
3998	*
3999	* Freescale Semiconductor assumes no responsibility for the
4000	* maintenance and support of this software
4001	*
4002	********************************************************************/

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