1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief Enhanced Direct Memory Access (eDMA). |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008 |
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11 | * Embedded Brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * rtems@embedded-brains.de |
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16 | * |
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17 | * The license and distribution terms for this file may be found in the file |
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18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #include <mpc55xx/regs.h> |
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22 | #include <mpc55xx/edma.h> |
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23 | #include <mpc55xx/mpc55xx.h> |
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24 | |
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25 | #include <bsp/irq.h> |
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26 | |
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27 | #include <string.h> |
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28 | |
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29 | #define RTEMS_STATUS_CHECKS_USE_PRINTK |
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30 | |
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31 | #include <rtems/status-checks.h> |
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32 | |
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33 | #define MPC55XX_EDMA_CHANNEL_NUMBER 64 |
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34 | #define MPC55XX_EDMA_INVALID_CHANNEL UINT8_MAX |
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35 | #define MPC55XX_EDMA_IS_CHANNEL_INVALID( i) ((i) < 0 || (i) >= MPC55XX_EDMA_CHANNEL_NUMBER) |
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36 | |
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37 | #define MPC55XX_EDMA_IRQ_PRIORITY MPC55XX_INTC_MIN_PRIORITY |
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38 | |
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39 | typedef struct { |
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40 | uint8_t channel; |
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41 | rtems_id transfer_update; |
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42 | uint32_t *error_status; |
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43 | } mpc55xx_edma_channel_entry; |
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44 | |
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45 | static mpc55xx_edma_channel_entry mpc55xx_edma_channel_table [MPC55XX_EDMA_CHANNEL_NUMBER]; |
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46 | |
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47 | static uint32_t mpc55xx_edma_channel_occupation_low = 0; |
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48 | |
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49 | static uint32_t mpc55xx_edma_channel_occupation_high = 0; |
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50 | |
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51 | static rtems_id mpc55xx_edma_channel_occupation_mutex = RTEMS_ID_NONE; |
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52 | |
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53 | static uint8_t mpc55xx_edma_irq_error_low_channel = 0; |
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54 | |
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55 | static uint8_t mpc55xx_edma_irq_error_high_channel = 32; |
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56 | |
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57 | static void mpc55xx_edma_irq_handler( rtems_vector_number vector, void *data) |
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58 | { |
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59 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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60 | mpc55xx_edma_channel_entry *e = (mpc55xx_edma_channel_entry *) data; |
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61 | #ifdef DEBUG |
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62 | uint32_t citer = EDMA.TCD [e->channel].CITERE_LINK ? EDMA.TCD [e->channel].CITER & EDMA_TCD_BITER_LINKED_MASK : EDMA.TCD [e->channel].CITER; |
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63 | RTEMS_DEBUG_PRINT( "Channel %i (CITER = %i)\n", e->channel, citer); |
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64 | #endif /* DEBUG */ |
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65 | EDMA.CIRQR.R = e->channel; |
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66 | sc = rtems_semaphore_release( e->transfer_update); |
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67 | RTEMS_SYSLOG_WARNING_SC( sc, "Transfer update semaphore release"); |
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68 | } |
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69 | |
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70 | static void mpc55xx_edma_irq_update_error_table( uint8_t *link_table, uint8_t *error_table, int channel) |
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71 | { |
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72 | int i = 0; |
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73 | error_table [channel] = 1; |
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74 | for (i = 0; i < MPC55XX_EDMA_CHANNEL_NUMBER; ++i) { |
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75 | if (channel == link_table [i] && error_table [i] == 0) { |
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76 | mpc55xx_edma_irq_update_error_table( link_table, error_table, i); |
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77 | } |
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78 | } |
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79 | } |
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80 | |
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81 | static void mpc55xx_edma_irq_error_handler( rtems_vector_number vector, void *data) |
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82 | { |
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83 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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84 | uint8_t channel_start = *((uint8_t *) data); |
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85 | uint8_t channel_end = (uint8_t) (channel_start + 32); |
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86 | int i = 0; |
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87 | uint32_t mask = 0x1; |
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88 | uint32_t error_register = 0; |
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89 | uint8_t channel_link_table [MPC55XX_EDMA_CHANNEL_NUMBER]; |
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90 | uint8_t channel_error_table [MPC55XX_EDMA_CHANNEL_NUMBER]; |
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91 | |
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92 | /* Error register */ |
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93 | if (channel_start < 32) { |
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94 | error_register = EDMA.ERL.R; |
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95 | } else if (channel_start < 64) { |
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96 | error_register = EDMA.ERH.R; |
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97 | } |
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98 | RTEMS_DEBUG_PRINT( "Error register %s: 0x%08x\n", channel_start < 32 ? "low" : "high", error_register); |
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99 | |
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100 | /* Fill channel link table */ |
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101 | for (i = 0; i < MPC55XX_EDMA_CHANNEL_NUMBER; ++i) { |
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102 | if (EDMA.TCD [i].BITERE_LINK && EDMA.TCD [i].CITER != EDMA.TCD [i].BITER) { |
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103 | channel_link_table [i] = (uint8_t) EDMA_TCD_BITER_LINK( i); |
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104 | } else if (EDMA.TCD [i].MAJORE_LINK && EDMA.TCD [i].CITER == EDMA.TCD [i].BITER) { |
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105 | channel_link_table [i] = EDMA.TCD [i].MAJORLINKCH; |
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106 | } else { |
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107 | channel_link_table [i] = MPC55XX_EDMA_INVALID_CHANNEL; |
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108 | } |
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109 | channel_error_table [i] = 0; |
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110 | } |
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111 | |
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112 | /* Search for channels with errors */ |
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113 | for (i = channel_start; i < channel_end; ++i) { |
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114 | if ((error_register & mask) != 0) { |
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115 | mpc55xx_edma_irq_update_error_table( channel_link_table, channel_error_table, i); |
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116 | } |
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117 | mask <<= 1; |
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118 | } |
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119 | |
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120 | /* Process the channels related to errors */ |
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121 | error_register = EDMA.ESR.R; |
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122 | for (i = 0; i < MPC55XX_EDMA_CHANNEL_NUMBER; ++i) { |
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123 | if (channel_error_table [i]) { |
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124 | mpc55xx_edma_channel_entry *e = &mpc55xx_edma_channel_table [i]; |
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125 | if (e->error_status != NULL) { |
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126 | *e->error_status = error_register; |
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127 | } |
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128 | sc = mpc55xx_edma_enable_hardware_requests( i, false); |
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129 | RTEMS_SYSLOG_ERROR_SC( sc, "Disable hardware requests"); |
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130 | sc = rtems_semaphore_release( e->transfer_update); |
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131 | RTEMS_SYSLOG_WARNING_SC( sc, "Transfer update semaphore release"); |
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132 | } |
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133 | } |
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134 | |
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135 | /* Clear the error interrupt requests */ |
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136 | for (i = 0; i < MPC55XX_EDMA_CHANNEL_NUMBER; ++i) { |
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137 | if (channel_error_table [i]) { |
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138 | EDMA.CER.R = (uint8_t) i; |
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139 | } |
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140 | } |
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141 | } |
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142 | |
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143 | rtems_status_code mpc55xx_edma_enable_hardware_requests( int channel, bool enable) |
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144 | { |
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145 | if (MPC55XX_EDMA_IS_CHANNEL_INVALID( channel)) { |
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146 | return RTEMS_INVALID_NUMBER; |
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147 | } |
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148 | if (enable) { |
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149 | EDMA.SERQR.R = (uint8_t) channel; |
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150 | } else { |
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151 | EDMA.CERQR.R = (uint8_t) channel; |
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152 | } |
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153 | return RTEMS_SUCCESSFUL; |
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154 | } |
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155 | |
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156 | rtems_status_code mpc55xx_edma_enable_error_interrupts( int channel, bool enable) |
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157 | { |
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158 | if (MPC55XX_EDMA_IS_CHANNEL_INVALID( channel)) { |
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159 | return RTEMS_INVALID_NUMBER; |
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160 | } |
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161 | if (enable) { |
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162 | EDMA.SEEIR.R = channel; |
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163 | } else { |
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164 | EDMA.CEEIR.R = channel; |
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165 | } |
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166 | return RTEMS_SUCCESSFUL; |
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167 | } |
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168 | |
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169 | rtems_status_code mpc55xx_edma_init() |
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170 | { |
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171 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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172 | int i = 0; |
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173 | |
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174 | /* Channel occupation mutex */ |
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175 | sc = rtems_semaphore_create ( |
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176 | rtems_build_name ( 'D', 'M', 'A', 'O'), |
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177 | 1, |
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178 | RTEMS_SIMPLE_BINARY_SEMAPHORE | RTEMS_INHERIT_PRIORITY | RTEMS_PRIORITY, |
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179 | RTEMS_NO_PRIORITY, |
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180 | &mpc55xx_edma_channel_occupation_mutex |
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181 | ); |
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182 | RTEMS_CHECK_SC( sc, "Create channel occupation mutex"); |
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183 | |
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184 | /* Arbitration mode: round robin */ |
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185 | EDMA.CR.B.ERCA = 1; |
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186 | EDMA.CR.B.ERGA = 1; |
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187 | |
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188 | /* Clear TCDs */ |
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189 | memset( &EDMA.TCD [0], 0, sizeof( EDMA.TCD)); |
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190 | |
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191 | /* Channel table */ |
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192 | for (i = 0; i < MPC55XX_EDMA_CHANNEL_NUMBER; ++i) { |
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193 | mpc55xx_edma_channel_table [i].channel = i; |
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194 | mpc55xx_edma_channel_table [i].transfer_update = RTEMS_ID_NONE; |
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195 | mpc55xx_edma_channel_table [i].error_status = NULL; |
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196 | } |
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197 | |
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198 | /* Error interrupt handler */ |
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199 | sc = mpc55xx_interrupt_handler_install( |
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200 | MPC55XX_IRQ_EDMA_ERROR_LOW, |
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201 | MPC55XX_EDMA_IRQ_PRIORITY, |
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202 | "eDMA Error (Low)", |
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203 | RTEMS_INTERRUPT_UNIQUE, |
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204 | mpc55xx_edma_irq_error_handler, |
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205 | &mpc55xx_edma_irq_error_low_channel |
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206 | ); |
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207 | RTEMS_CHECK_SC( sc, "Install low error interrupt handler"); |
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208 | sc = mpc55xx_interrupt_handler_install( |
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209 | MPC55XX_IRQ_EDMA_ERROR_HIGH, |
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210 | MPC55XX_EDMA_IRQ_PRIORITY, |
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211 | "eDMA Error (High)", |
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212 | RTEMS_INTERRUPT_UNIQUE, |
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213 | mpc55xx_edma_irq_error_handler, |
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214 | &mpc55xx_edma_irq_error_high_channel |
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215 | ); |
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216 | RTEMS_CHECK_SC( sc, "Install high error interrupt handler"); |
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217 | |
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218 | return RTEMS_SUCCESSFUL; |
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219 | } |
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220 | |
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221 | rtems_status_code mpc55xx_edma_obtain_channel( int channel, uint32_t *error_status, rtems_id transfer_update) |
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222 | { |
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223 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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224 | int channel_occupied = 1; |
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225 | |
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226 | if (MPC55XX_EDMA_IS_CHANNEL_INVALID( channel)) { |
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227 | return RTEMS_INVALID_NUMBER; |
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228 | } |
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229 | |
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230 | /* Check occupation */ |
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231 | sc = rtems_semaphore_obtain( mpc55xx_edma_channel_occupation_mutex, RTEMS_WAIT, 0); |
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232 | RTEMS_CHECK_SC( sc, "Obtain channel occupation mutex"); |
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233 | if (channel < 32) { |
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234 | channel_occupied = mpc55xx_edma_channel_occupation_low & (0x1 << channel); |
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235 | if (!channel_occupied) { |
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236 | mpc55xx_edma_channel_occupation_low |= 0x1 << channel; |
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237 | } |
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238 | } else if (channel < 64) { |
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239 | channel_occupied = mpc55xx_edma_channel_occupation_high & (0x1 << (channel - 32)); |
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240 | if (!channel_occupied) { |
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241 | mpc55xx_edma_channel_occupation_high |= 0x1 << (channel - 32); |
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242 | } |
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243 | } |
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244 | if (channel_occupied) { |
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245 | sc = rtems_semaphore_release( mpc55xx_edma_channel_occupation_mutex); |
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246 | RTEMS_SYSLOG_WARNING_SC( sc, "Release occupation mutex"); |
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247 | return RTEMS_RESOURCE_IN_USE; |
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248 | } else { |
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249 | sc = rtems_semaphore_release( mpc55xx_edma_channel_occupation_mutex); |
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250 | RTEMS_CHECK_SC( sc, "Release channel occupation mutex"); |
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251 | } |
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252 | |
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253 | /* Channel data */ |
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254 | mpc55xx_edma_channel_table [channel].transfer_update = transfer_update; |
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255 | mpc55xx_edma_channel_table [channel].error_status = error_status; |
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256 | |
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257 | /* Interrupt handler */ |
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258 | sc = mpc55xx_interrupt_handler_install( |
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259 | MPC55XX_IRQ_EDMA_GET_REQUEST( channel), |
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260 | MPC55XX_EDMA_IRQ_PRIORITY, |
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261 | "eDMA Channel", |
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262 | RTEMS_INTERRUPT_SHARED, |
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263 | mpc55xx_edma_irq_handler, |
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264 | &mpc55xx_edma_channel_table [channel] |
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265 | ); |
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266 | RTEMS_CHECK_SC( sc, "Install channel interrupt handler"); |
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267 | |
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268 | /* Enable error interrupts */ |
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269 | sc = mpc55xx_edma_enable_error_interrupts( channel, true); |
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270 | RTEMS_CHECK_SC( sc, "Enable error interrupts"); |
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271 | |
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272 | return RTEMS_SUCCESSFUL; |
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273 | } |
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274 | |
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275 | rtems_status_code mpc55xx_edma_release_channel( int channel) |
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276 | { |
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277 | // TODO |
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278 | return RTEMS_NOT_IMPLEMENTED; |
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279 | } |
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