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source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c @ d374492

4.104.115

Last change on this file since d374492 was d374492, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 07/21/09 at 08:38:04
Update for MPC55XX changes
Property mode set to `100644`
File size: 18.8 KB

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1	/**
2	* @file
3	*
4	* @ingroup mpc55xx_dspi
5	*
6	* @brief Source file for the LibI2C bus driver for the Deserial Serial Peripheral Interface (DSPI).
7	*/
8
9	/*
10	* Copyright (c) 2008
11	* Embedded Brains GmbH
12	* Obere Lagerstr. 30
13	* D-82178 Puchheim
14	* Germany
15	* rtems@embedded-brains.de
16	*
17	* The license and distribution terms for this file may be found in the file
18	* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19	*/
20
21	#include <mpc55xx/regs.h>
22	#include <mpc55xx/dspi.h>
23	#include <mpc55xx/mpc55xx.h>
24
25	#include <libcpu/powerpc-utility.h>
26
27	#define RTEMS_STATUS_CHECKS_USE_PRINTK
28
29	#include <rtems/status-checks.h>
30
31	#define MPC55XX_DSPI_FIFO_SIZE 4
32
33	#define MPC55XX_DSPI_CTAR_NUMBER 8
34
35	#define MPC55XX_DSPI_CTAR_DEFAULT 0
36
37	#define MPC55XX_DSPI_EDMA_MAGIC_SIZE 128
38
39	#define MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE 63
40
41	typedef struct {
42	uint32_t scaler : 26;
43	uint32_t pbr : 2;
44	uint32_t br : 4;
45	} mpc55xx_dspi_baudrate_scaler_entry;
46
47	static const mpc55xx_dspi_baudrate_scaler_entry mpc55xx_dspi_baudrate_scaler_table [MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE] = {
48	{ 4, 0, 0 },
49	{ 6, 1, 0 },
50	{ 8, 0, 1 },
51	{ 10, 2, 0 },
52	{ 12, 1, 1 },
53	{ 14, 3, 0 },
54	{ 16, 0, 3 },
55	{ 18, 1, 2 },
56	{ 20, 2, 1 },
57	{ 24, 1, 3 },
58	{ 28, 3, 1 },
59	{ 30, 2, 2 },
60	{ 32, 0, 4 },
61	{ 40, 2, 3 },
62	{ 42, 3, 2 },
63	{ 48, 1, 4 },
64	{ 56, 3, 3 },
65	{ 64, 0, 5 },
66	{ 80, 2, 4 },
67	{ 96, 1, 5 },
68	{ 112, 3, 4 },
69	{ 128, 0, 6 },
70	{ 160, 2, 5 },
71	{ 192, 1, 6 },
72	{ 224, 3, 5 },
73	{ 256, 0, 7 },
74	{ 320, 2, 6 },
75	{ 384, 1, 7 },
76	{ 448, 3, 6 },
77	{ 512, 0, 8 },
78	{ 640, 2, 7 },
79	{ 768, 1, 8 },
80	{ 896, 3, 7 },
81	{ 1024, 0, 9 },
82	{ 1280, 2, 8 },
83	{ 1536, 1, 9 },
84	{ 1792, 3, 8 },
85	{ 2048, 0, 10 },
86	{ 2560, 2, 9 },
87	{ 3072, 1, 10 },
88	{ 3584, 3, 9 },
89	{ 4096, 0, 11 },
90	{ 5120, 2, 10 },
91	{ 6144, 1, 11 },
92	{ 7168, 3, 10 },
93	{ 8192, 0, 12 },
94	{ 10240, 2, 11 },
95	{ 12288, 1, 12 },
96	{ 14336, 3, 11 },
97	{ 16384, 0, 13 },
98	{ 20480, 2, 12 },
99	{ 24576, 1, 13 },
100	{ 28672, 3, 12 },
101	{ 32768, 0, 14 },
102	{ 40960, 2, 13 },
103	{ 49152, 1, 14 },
104	{ 57344, 3, 13 },
105	{ 65536, 0, 15 },
106	{ 81920, 2, 14 },
107	{ 98304, 1, 15 },
108	{ 114688, 3, 14 },
109	{ 163840, 2, 15 },
110	{ 229376, 3, 15 },
111	};
112
113	static void mpc55xx_dspi_edma_done( mpc55xx_edma_channel_entry *e, uint32_t error_status)
114	{
115	rtems_semaphore_release( e->id);
116
117	if (error_status != 0) {
118	RTEMS_SYSLOG_ERROR( "eDMA error: 0x%08x\n", error_status);
119	}
120	}
121
122	static mpc55xx_dspi_baudrate_scaler_entry mpc55xx_dspi_search_baudrate_scaler( uint32_t scaler, int min, int mid, int max)
123	{
124	if (scaler <= mpc55xx_dspi_baudrate_scaler_table [mid].scaler) {
125	max = mid;
126	} else {
127	min = mid;
128	}
129	mid = (min + max) / 2;
130	if (mid == min) {
131	return mpc55xx_dspi_baudrate_scaler_table [max];
132	} else {
133	return mpc55xx_dspi_search_baudrate_scaler( scaler, min, mid, max);
134	}
135	}
136
137	static uint32_t mpc55xx_dspi_push_data [8 * MPC55XX_DSPI_NUMBER] __attribute__ ((aligned (32)));
138
139	static inline void mpc55xx_dspi_store_push_data( mpc55xx_dspi_bus_entry *e)
140	{
141	mpc55xx_dspi_push_data [e->table_index * 8] = e->push_data.R;
142	rtems_cache_flush_multiple_data_lines( &mpc55xx_dspi_push_data [e->table_index * 8], 4);
143	}
144
145	static inline uint32_t mpc55xx_dspi_push_data_address( mpc55xx_dspi_bus_entry *e)
146	{
147	return (uint32_t) &mpc55xx_dspi_push_data [e->table_index * 8];
148	}
149
150	static inline uint32_t mpc55xx_dspi_nirvana_address( mpc55xx_dspi_bus_entry *e)
151	{
152	return (uint32_t) &mpc55xx_dspi_push_data [e->table_index * 8 + 1];
153	}
154
155	static rtems_status_code mpc55xx_dspi_init( rtems_libi2c_bus_t *bus)
156	{
157	rtems_status_code sc = RTEMS_SUCCESSFUL;
158	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
159	union DSPI_MCR_tag mcr = MPC55XX_ZERO_FLAGS;
160	union DSPI_CTAR_tag ctar = MPC55XX_ZERO_FLAGS;
161	union DSPI_RSER_tag rser = MPC55XX_ZERO_FLAGS;
162	struct tcd_t tcd_push = EDMA_TCD_DEFAULT;
163	int i = 0;
164
165	/* eDMA receive */
166	sc = rtems_semaphore_create (
167	rtems_build_name ( 'S', 'P', 'I', 'R'),
168	0,
169	RTEMS_SIMPLE_BINARY_SEMAPHORE,
170	0,
171	&e->edma_receive.id
172	);
173	RTEMS_CHECK_SC( sc, "create receive update semaphore");
174
175	sc = mpc55xx_edma_obtain_channel( &e->edma_receive);
176	RTEMS_CHECK_SC( sc, "obtain receive eDMA channel");
177
178	/* eDMA transmit */
179	sc = rtems_semaphore_create (
180	rtems_build_name ( 'S', 'P', 'I', 'T'),
181	0,
182	RTEMS_SIMPLE_BINARY_SEMAPHORE,
183	0,
184	&e->edma_transmit.id
185	);
186	RTEMS_CHECK_SC( sc, "create transmit update semaphore");
187
188	sc = mpc55xx_edma_obtain_channel( &e->edma_transmit);
189	RTEMS_CHECK_SC( sc, "obtain transmit eDMA channel");
190
191	sc = mpc55xx_edma_obtain_channel( &e->edma_push);
192	RTEMS_CHECK_SC( sc, "obtain push eDMA channel");
193
194	tcd_push.SADDR = mpc55xx_dspi_push_data_address( e);
195	tcd_push.SDF.B.SSIZE = 2;
196	tcd_push.SDF.B.SOFF = 0;
197	tcd_push.DADDR = (uint32_t) &e->regs->PUSHR.R;
198	tcd_push.SDF.B.DSIZE = 2;
199	tcd_push.CDF.B.DOFF = 0;
200	tcd_push.NBYTES = 4;
201	tcd_push.CDF.B.CITER = 1;
202	tcd_push.BMF.B.BITER = 1;
203
204	EDMA.TCD [e->edma_push.channel] = tcd_push;
205
206	/* Module Control Register */
207	mcr.B.MSTR = e->master ? 1 : 0;
208	mcr.B.CONT_SCKE = 0;
209	mcr.B.DCONF = 0;
210	mcr.B.FRZ = 0;
211	mcr.B.MTFE = 0;
212	mcr.B.PCSSE = 0;
213	mcr.B.ROOE = 0;
214	mcr.B.PCSIS0 = 1;
215	mcr.B.PCSIS1 = 1;
216	mcr.B.PCSIS2 = 1;
217	mcr.B.PCSIS3 = 1;
218	mcr.B.PCSIS5 = 1;
219	mcr.B.MDIS = 0;
220	mcr.B.DIS_TXF = 0;
221	mcr.B.DIS_RXF = 0;
222	mcr.B.CLR_TXF = 0;
223	mcr.B.CLR_RXF = 0;
224	mcr.B.SMPL_PT = 0;
225	mcr.B.HALT = 0;
226
227	e->regs->MCR.R = mcr.R;
228
229	/* Clock and Transfer Attributes Register */
230	ctar.B.DBR = 0;
231	ctar.B.FMSZ = 0x7;
232	ctar.B.CPOL = 0;
233	ctar.B.CPHA = 0;
234	ctar.B.LSBFE = 0;
235	ctar.B.PCSSCK = 0;
236	ctar.B.PASC = 0;
237	ctar.B.PDT = 0;
238	ctar.B.PBR = 0;
239	ctar.B.CSSCK = 0;
240	ctar.B.ASC = 0;
241	ctar.B.DT = 0;
242	ctar.B.BR = 0;
243
244	for (i = 0; i < MPC55XX_DSPI_CTAR_NUMBER; ++i) {
245	e->regs->CTAR [i].R = ctar.R;
246	}
247
248	/* DMA/Interrupt Request Select and Enable Register */
249	rser.B.TFFFRE = 1;
250	rser.B.TFFFDIRS = 1;
251	rser.B.RFDFRE = 1;
252	rser.B.RFDFDIRS = 1;
253
254	e->regs->RSER.R = rser.R;
255
256	return RTEMS_SUCCESSFUL;
257	}
258
259	static rtems_status_code mpc55xx_dspi_send_start( rtems_libi2c_bus_t *bus)
260	{
261	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
262
263	/* Reset chip selects */
264	e->push_data.B.PCS0 = 0;
265	e->push_data.B.PCS1 = 0;
266	e->push_data.B.PCS2 = 0;
267	e->push_data.B.PCS3 = 0;
268	e->push_data.B.PCS4 = 0;
269	e->push_data.B.PCS5 = 0;
270	mpc55xx_dspi_store_push_data( e);
271
272	return RTEMS_SUCCESSFUL;
273	}
274
275	static rtems_status_code mpc55xx_dspi_send_stop( rtems_libi2c_bus_t *bus)
276	{
277	return RTEMS_SUCCESSFUL;
278	}
279
280	static rtems_status_code mpc55xx_dspi_send_addr( rtems_libi2c_bus_t *bus, uint32_t addr, int rw)
281	{
282	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
283	union DSPI_SR_tag sr = MPC55XX_ZERO_FLAGS;
284
285	/* Flush transmit and receive FIFO */
286	e->regs->MCR.B.CLR_TXF = 1;
287	e->regs->MCR.B.CLR_RXF = 1;
288
289	/* Clear status flags */
290	sr.B.EOQF = 1;
291	sr.B.TFFF = 1;
292	sr.B.RFDF = 1;
293	e->regs->SR.R = sr.R;
294
295	/* Frame command */
296	e->push_data.R = 0;
297	e->push_data.B.CONT = 0;
298	e->push_data.B.CTAS = MPC55XX_DSPI_CTAR_DEFAULT;
299	e->push_data.B.EOQ = 0;
300	e->push_data.B.CTCNT = 0;
301	switch (addr) {
302	case 0:
303	e->push_data.B.PCS0 = 1;
304	break;
305	case 1:
306	e->push_data.B.PCS1 = 1;
307	break;
308	case 2:
309	e->push_data.B.PCS2 = 1;
310	break;
311	case 3:
312	e->push_data.B.PCS3 = 1;
313	break;
314	case 4:
315	e->push_data.B.PCS4 = 1;
316	break;
317	case 5:
318	e->push_data.B.PCS5 = 1;
319	break;
320	default:
321	return -RTEMS_INVALID_ADDRESS;
322	}
323	mpc55xx_dspi_store_push_data( e);
324
325	return RTEMS_SUCCESSFUL;
326	}
327
328	/* FIXME, TODO */
329	extern uint32_t bsp_clock_speed;
330
331	static int mpc55xx_dspi_set_transfer_mode( rtems_libi2c_bus_t bus, const rtems_libi2c_tfr_mode_t mode)
332	{
333	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
334	union DSPI_CTAR_tag ctar = MPC55XX_ZERO_FLAGS;
335
336	if (mode->bits_per_char != 8) {
337	return -RTEMS_INVALID_NUMBER;
338	}
339
340	e->idle_char = mode->idle_char;
341
342	ctar.R = e->regs->CTAR [MPC55XX_DSPI_CTAR_DEFAULT].R;
343
344	ctar.B.PCSSCK = 0;
345	ctar.B.CSSCK = 0;
346	ctar.B.PASC = 0;
347	ctar.B.ASC = 0;
348
349	ctar.B.LSBFE = mode->lsb_first ? 1 : 0;
350	ctar.B.CPOL = mode->clock_inv ? 1 : 0;
351	ctar.B.CPHA = mode->clock_phs ? 1 : 0;
352
353	if (mode->baudrate != e->baud) {
354	uint32_t scaler = bsp_clock_speed / mode->baudrate;
355	mpc55xx_dspi_baudrate_scaler_entry bse = mpc55xx_dspi_search_baudrate_scaler( scaler, 0, MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE / 2, MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE);
356
357	ctar.B.PBR = bse.pbr;
358	ctar.B.BR = bse.br;
359
360	e->baud = mode->baudrate;
361	}
362
363	e->regs->CTAR [MPC55XX_DSPI_CTAR_DEFAULT].R = ctar.R;
364
365	return 0;
366	}
367
368	/**
369	* @brief Writes @a n characters from @a out to bus @a bus and synchronously stores the received data in @a in.
370	*
371	* eDMA channel usage for transmission:
372	* @dot
373	* digraph push {
374	* push [label="Push Register"];
375	* push_data [label="Push Data"];
376	* idle_push_data [label="Idle Push Data"];
377	* out [shape=box,label="Output Buffer"];
378	* edge [color=red,fontcolor=red];
379	* push -> idle_push_data [label="Transmit Request",URL="\ref mpc55xx_dspi_bus_entry::edma_transmit"];
380	* push -> out [label="Transmit Request",URL="\ref mpc55xx_dspi_bus_entry::edma_transmit"];
381	* out -> push_data [label="Channel Link",URL="\ref mpc55xx_dspi_bus_entry::edma_push"];
382	* edge [color=blue,fontcolor=blue];
383	* out -> push_data [label="Data"];
384	* push_data -> push [label="Data"];
385	* idle_push_data -> push [label="Data"];
386	* }
387	* @enddot
388	*
389	* eDMA channel usage for receiving:
390	* @dot
391	* digraph pop {
392	* pop [label="Pop Register"];
393	* nirvana [label="Nirvana"];
394	* in [shape=box,label="Input Buffer"];
395	* edge [color=red,fontcolor=red];
396	* pop -> nirvana [label="Receive Request",URL="\ref mpc55xx_dspi_bus_entry::edma_receive"];
397	* pop -> in [label="Receive Request",URL="\ref mpc55xx_dspi_bus_entry::edma_receive"];
398	* edge [color=blue,fontcolor=blue];
399	* pop -> nirvana [label="Data"];
400	* pop -> in [label="Data"];
401	* }
402	* @enddot
403	*/
404	static int mpc55xx_dspi_read_write( rtems_libi2c_bus_t bus, unsigned char in, const unsigned char *out, int n)
405	{
406	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
407
408	/* Non cache aligned characters */
409	int n_nc = n;
410
411	/* Cache aligned characters */
412	int n_c = 0;
413
414	/* Register addresses */
415	volatile void *push = &e->regs->PUSHR.R;
416	volatile void *pop = &e->regs->POPR.R;
417	volatile union DSPI_SR_tag *status = &e->regs->SR;
418
419	/* Push and pop data */
420	union DSPI_PUSHR_tag push_data = e->push_data;
421	union DSPI_POPR_tag pop_data;
422
423	/* Status register */
424	union DSPI_SR_tag sr;
425
426	/* Read and write indices */
427	int r = 0;
428	int w = 0;
429
430	if (n == 0) {
431	return 0;
432	} else if (in == NULL && out == NULL) {
433	return -RTEMS_INVALID_ADDRESS;
434	}
435
436	if (n > MPC55XX_DSPI_EDMA_MAGIC_SIZE) {
437	n_nc = (int) mpc55xx_non_cache_aligned_size( in);
438	n_c = (int) mpc55xx_cache_aligned_size( in, (size_t) n);
439	if (n_c > EDMA_TCD_BITER_LINKED_SIZE) {
440	RTEMS_SYSLOG_WARNING( "buffer size out of range, cannot use eDMA\n");
441	n_nc = n;
442	n_c = 0;
443	} else if (n_nc + n_c != n) {
444	RTEMS_SYSLOG_WARNING( "input buffer not proper cache aligned, cannot use eDMA\n");
445	n_nc = n;
446	n_c = 0;
447	}
448	}
449
450	#ifdef DEBUG
451	if (e->regs->SR.B.TXCTR != e->regs->SR.B.RXCTR) {
452	RTEMS_SYSLOG_WARNING( "FIFO counter not equal\n");
453	}
454	#endif /* DEBUG */
455
456	/* Direct IO */
457	if (out == NULL) {
458	push_data.B.TXDATA = e->idle_char;
459	while (r < n_nc \|\| w < n_nc) {
460	/* Wait for available FIFO */
461	do {
462	sr.R = status->R;
463	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
464
465	/* Write */
466	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
467	++w;
468	ppc_write_word( push_data.R, push);
469	}
470
471	/* Read */
472	if (r < n_nc && sr.B.RXCTR != 0) {
473	pop_data.R = ppc_read_word( pop);
474	in [r] = (unsigned char) pop_data.B.RXDATA;
475	++r;
476	}
477	}
478	} else if (in == NULL) {
479	while (r < n_nc \|\| w < n_nc) {
480	/* Wait for available FIFO */
481	do {
482	sr.R = status->R;
483	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
484
485	/* Write */
486	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
487	push_data.B.TXDATA = out [w];
488	++w;
489	ppc_write_word( push_data.R, push);
490	}
491
492	/* Read */
493	if (r < n_nc && sr.B.RXCTR != 0) {
494	pop_data.R = ppc_read_word( pop);
495	++r;
496	}
497	}
498	} else {
499	while (r < n_nc \|\| w < n_nc) {
500	/* Wait for available FIFO */
501	do {
502	sr.R = status->R;
503	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
504
505	/* Write */
506	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
507	push_data.B.TXDATA = out [w];
508	++w;
509	ppc_write_word( push_data.R, push);
510	}
511
512	/* Read */
513	if (r < n_nc && sr.B.RXCTR != 0) {
514	pop_data.R = ppc_read_word( pop);
515	in [r] = (unsigned char) pop_data.B.RXDATA;
516	++r;
517	}
518	}
519	}
520
521	/* eDMA transfers */
522	if (n_c > 0) {
523	rtems_status_code sc = RTEMS_SUCCESSFUL;
524	unsigned char *in_c = in + n_nc;
525	const unsigned char *out_c = out + n_nc;
526	struct tcd_t tcd_transmit = EDMA_TCD_DEFAULT;
527	struct tcd_t tcd_receive = EDMA_TCD_DEFAULT;
528
529	/* Cache operations */
530	rtems_cache_flush_multiple_data_lines( out_c, (size_t) n_c);
531	rtems_cache_invalidate_multiple_data_lines( in_c, (size_t) n_c);
532
533	/* Set transmit TCD */
534	if (out == NULL) {
535	e->push_data.B.TXDATA = e->idle_char;
536	mpc55xx_dspi_store_push_data( e);
537	tcd_transmit.SADDR = mpc55xx_dspi_push_data_address( e);
538	tcd_transmit.SDF.B.SSIZE = 2;
539	tcd_transmit.SDF.B.SOFF = 0;
540	tcd_transmit.DADDR = (uint32_t) push;
541	tcd_transmit.SDF.B.DSIZE = 2;
542	tcd_transmit.CDF.B.DOFF = 0;
543	tcd_transmit.NBYTES = 4;
544	tcd_transmit.CDF.B.CITER = n_c;
545	tcd_transmit.BMF.B.BITER = n_c;
546	} else {
547	EDMA.CDSBR.R = e->edma_transmit.channel;
548	tcd_transmit.SADDR = (uint32_t) out_c;
549	tcd_transmit.SDF.B.SSIZE = 0;
550	tcd_transmit.SDF.B.SOFF = 1;
551	tcd_transmit.DADDR = mpc55xx_dspi_push_data_address( e) + 3;
552	tcd_transmit.SDF.B.DSIZE = 0;
553	tcd_transmit.CDF.B.DOFF = 0;
554	tcd_transmit.NBYTES = 1;
555	tcd_transmit.CDF.B.CITERE_LINK = 1;
556	tcd_transmit.BMF.B.BITERE_LINK = 1;
557	tcd_transmit.BMF.B.MAJORLINKCH = e->edma_push.channel;
558	tcd_transmit.CDF.B.CITER = EDMA_TCD_LINK_AND_BITER( e->edma_push.channel, n_c);
559	tcd_transmit.BMF.B.BITER = EDMA_TCD_LINK_AND_BITER( e->edma_push.channel, n_c);
560	tcd_transmit.BMF.B.MAJORE_LINK = 1;
561	}
562	tcd_transmit.BMF.B.D_REQ = 1;
563	tcd_transmit.BMF.B.INT_MAJ = 1;
564	EDMA.TCD [e->edma_transmit.channel] = tcd_transmit;
565
566	/* Set receive TCD */
567	if (in == NULL) {
568	tcd_receive.CDF.B.DOFF = 0;
569	tcd_receive.DADDR = mpc55xx_dspi_nirvana_address( e);
570	} else {
571	tcd_receive.CDF.B.DOFF = 1;
572	tcd_receive.DADDR = (uint32_t) in_c;
573	}
574	tcd_receive.SADDR = (uint32_t) pop + 3;
575	tcd_receive.SDF.B.SSIZE = 0;
576	tcd_receive.SDF.B.SOFF = 0;
577	tcd_receive.SDF.B.DSIZE = 0;
578	tcd_receive.NBYTES = 1;
579	tcd_receive.BMF.B.D_REQ = 1;
580	tcd_receive.BMF.B.INT_MAJ = 1;
581	tcd_receive.CDF.B.CITER = n_c;
582	tcd_receive.BMF.B.BITER = n_c;
583	EDMA.TCD [e->edma_receive.channel] = tcd_receive;
584
585	/* Clear request flags */
586	sr.R = 0;
587	sr.B.TFFF = 1;
588	sr.B.RFDF = 1;
589	status->R = sr.R;
590
591	/* Enable hardware requests */
592	mpc55xx_edma_enable_hardware_requests( e->edma_receive.channel, true);
593	mpc55xx_edma_enable_hardware_requests( e->edma_transmit.channel, true);
594
595	/* Wait for transmit update */
596	sc = rtems_semaphore_obtain( e->edma_transmit.id, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
597	RTEMS_CHECK_SC_RV( sc, "transmit update");
598
599	/* Wait for receive update */
600	sc = rtems_semaphore_obtain( e->edma_receive.id, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
601	RTEMS_CHECK_SC_RV( sc, "receive update");
602	}
603
604	return n;
605	}
606
607	/**
608	* @brief Reads @a n characters from bus @a bus and stores it in @a in.
609	*
610	* Writes idle characters to receive data.
611	*
612	* @see mpc55xx_dspi_read_write().
613	*/
614	static int mpc55xx_dspi_read( rtems_libi2c_bus_t bus, unsigned char in, int n)
615	{
616	return mpc55xx_dspi_read_write( bus, in, NULL, n);
617	}
618
619	/**
620	* @brief Writes @a n characters from @a out to bus @a bus.
621	*
622	* Discards the synchronously received data.
623	*
624	* @see mpc55xx_dspi_read_write().
625	*/
626	static int mpc55xx_dspi_write( rtems_libi2c_bus_t bus, unsigned char out, int n)
627	{
628	return mpc55xx_dspi_read_write( bus, NULL, out, n);
629	}
630
631	static int mpc55xx_dspi_ioctl( rtems_libi2c_bus_t bus, int cmd, void arg)
632	{
633	int rv = -1;
634	switch (cmd) {
635	case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
636	rv = mpc55xx_dspi_set_transfer_mode( bus, (const rtems_libi2c_tfr_mode_t *) arg);
637	break;
638	case RTEMS_LIBI2C_IOCTL_READ_WRITE:
639	rv = mpc55xx_dspi_read_write(
640	bus,
641	((rtems_libi2c_read_write_t *) arg)->rd_buf,
642	((rtems_libi2c_read_write_t *) arg)->wr_buf,
643	((rtems_libi2c_read_write_t *) arg)->byte_cnt
644	);
645	break;
646	default:
647	rv = -RTEMS_NOT_DEFINED;
648	break;
649	}
650	return rv;
651	}
652
653	static const rtems_libi2c_bus_ops_t mpc55xx_dspi_ops = {
654	.init = mpc55xx_dspi_init,
655	.send_start = mpc55xx_dspi_send_start,
656	.send_stop = mpc55xx_dspi_send_stop,
657	.send_addr = mpc55xx_dspi_send_addr,
658	.read_bytes = mpc55xx_dspi_read,
659	.write_bytes = mpc55xx_dspi_write,
660	.ioctl = mpc55xx_dspi_ioctl
661	};
662
663	mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [MPC55XX_DSPI_NUMBER] = {
664	{
665	/* DSPI A */
666	.bus = {
667	.ops = &mpc55xx_dspi_ops,
668	.size = sizeof( mpc55xx_dspi_bus_entry)
669	},
670	.table_index = 0,
671	.bus_number = 0,
672	.regs = &DSPI_A,
673	.master = true,
674	.push_data = MPC55XX_ZERO_FLAGS,
675	.edma_transmit = {
676	.channel = 32,
677	.done = mpc55xx_dspi_edma_done,
678	.id = RTEMS_ID_NONE
679	},
680	.edma_push = {
681	.channel = 43,
682	.done = mpc55xx_dspi_edma_done,
683	.id = RTEMS_ID_NONE
684	},
685	.edma_receive = {
686	.channel = 33,
687	.done = mpc55xx_dspi_edma_done,
688	.id = RTEMS_ID_NONE
689	},
690	.idle_char = 0xffffffff,
691	.baud = 0
692	}, {
693	/* DSPI B */
694	.bus = {
695	.ops = &mpc55xx_dspi_ops,
696	.size = sizeof( mpc55xx_dspi_bus_entry)
697	},
698	.table_index = 1,
699	.bus_number = 0,
700	.regs = &DSPI_B,
701	.master = true,
702	.push_data = MPC55XX_ZERO_FLAGS,
703	.edma_transmit = {
704	.channel = 12,
705	.done = mpc55xx_dspi_edma_done,
706	.id = RTEMS_ID_NONE
707	},
708	.edma_push = {
709	.channel = 10,
710	.done = mpc55xx_dspi_edma_done,
711	.id = RTEMS_ID_NONE
712	},
713	.edma_receive = {
714	.channel = 13,
715	.done = mpc55xx_dspi_edma_done,
716	.id = RTEMS_ID_NONE
717	},
718	.idle_char = 0xffffffff,
719	.baud = 0
720	}, {
721	/* DSPI C */
722	.bus = {
723	.ops = &mpc55xx_dspi_ops,
724	.size = sizeof( mpc55xx_dspi_bus_entry)
725	},
726	.table_index = 2,
727	.bus_number = 0,
728	.regs = &DSPI_C,
729	.master = true,
730	.push_data = MPC55XX_ZERO_FLAGS,
731	.edma_transmit = {
732	.channel = 14,
733	.done = mpc55xx_dspi_edma_done,
734	.id = RTEMS_ID_NONE
735	},
736	.edma_push = {
737	.channel = 11,
738	.done = mpc55xx_dspi_edma_done,
739	.id = RTEMS_ID_NONE
740	},
741	.edma_receive = {
742	.channel = 15,
743	.done = mpc55xx_dspi_edma_done,
744	.id = RTEMS_ID_NONE
745	},
746	.idle_char = 0xffffffff,
747	.baud = 0
748	}, {
749	/* DSPI D */
750	.bus = {
751	.ops = &mpc55xx_dspi_ops,
752	.size = sizeof( mpc55xx_dspi_bus_entry)
753	},
754	.table_index = 3,
755	.bus_number = 0,
756	.regs = &DSPI_D,
757	.master = true,
758	.push_data = MPC55XX_ZERO_FLAGS,
759	.edma_transmit = {
760	.channel = 16,
761	.done = mpc55xx_dspi_edma_done,
762	.id = RTEMS_ID_NONE
763	},
764	.edma_push = {
765	.channel = 18,
766	.done = mpc55xx_dspi_edma_done,
767	.id = RTEMS_ID_NONE
768	},
769	.edma_receive = {
770	.channel = 17,
771	.done = mpc55xx_dspi_edma_done,
772	.id = RTEMS_ID_NONE
773	},
774	.idle_char = 0xffffffff,
775	.baud = 0
776	}
777	};

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