Context Navigation

source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c @ 7495494

4.104.115

Last change on this file since 7495494 was 1dab788, checked in by Joel Sherrill <joel.sherrill@…>, on 08/20/08 at 17:29:19

2008-08-20 Sebastian Huber <sebastian.huber@…>

mpc55xx/fec/fec.c: Added copyright information.
mpc55xx/dspi/dspi.c, mpc55xx/edma/edma.c, mpc55xx/esci/esci.c: Fixed nexted extern declarations. Fixed integer conversion warnings.
shared/include/cpuIdent.c: Added missing initializers.

Property mode set to 100644

File size: 18.9 KB

Line
1	/**
2	* @file
3	*
4	* @ingroup mpc55xx_dspi
5	*
6	* @brief Source file for the LibI2C bus driver for the Deserial Serial Peripheral Interface (DSPI).
7	*/
8
9	/*
10	* Copyright (c) 2008
11	* Embedded Brains GmbH
12	* Obere Lagerstr. 30
13	* D-82178 Puchheim
14	* Germany
15	* rtems@embedded-brains.de
16	*
17	* The license and distribution terms for this file may be found in the file
18	* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19	*/
20
21	#include <mpc55xx/regs.h>
22	#include <mpc55xx/dspi.h>
23	#include <mpc55xx/edma.h>
24	#include <mpc55xx/mpc55xx.h>
25
26	#include <libcpu/powerpc-utility.h>
27
28	#define RTEMS_STATUS_CHECKS_USE_PRINTK
29
30	#include <rtems/status-checks.h>
31
32	#define MPC55XX_DSPI_FIFO_SIZE 4
33
34	#define MPC55XX_DSPI_CTAR_NUMBER 8
35
36	#define MPC55XX_DSPI_CTAR_DEFAULT 0
37
38	#define MPC55XX_DSPI_EDMA_MAGIC_SIZE 128
39
40	#define MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE 63
41
42	typedef struct {
43	uint32_t scaler : 26;
44	uint32_t pbr : 2;
45	uint32_t br : 4;
46	} mpc55xx_dspi_baudrate_scaler_entry;
47
48	static const mpc55xx_dspi_baudrate_scaler_entry mpc55xx_dspi_baudrate_scaler_table [MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE] = {
49	{ 4, 0, 0 },
50	{ 6, 1, 0 },
51	{ 8, 0, 1 },
52	{ 10, 2, 0 },
53	{ 12, 1, 1 },
54	{ 14, 3, 0 },
55	{ 16, 0, 3 },
56	{ 18, 1, 2 },
57	{ 20, 2, 1 },
58	{ 24, 1, 3 },
59	{ 28, 3, 1 },
60	{ 30, 2, 2 },
61	{ 32, 0, 4 },
62	{ 40, 2, 3 },
63	{ 42, 3, 2 },
64	{ 48, 1, 4 },
65	{ 56, 3, 3 },
66	{ 64, 0, 5 },
67	{ 80, 2, 4 },
68	{ 96, 1, 5 },
69	{ 112, 3, 4 },
70	{ 128, 0, 6 },
71	{ 160, 2, 5 },
72	{ 192, 1, 6 },
73	{ 224, 3, 5 },
74	{ 256, 0, 7 },
75	{ 320, 2, 6 },
76	{ 384, 1, 7 },
77	{ 448, 3, 6 },
78	{ 512, 0, 8 },
79	{ 640, 2, 7 },
80	{ 768, 1, 8 },
81	{ 896, 3, 7 },
82	{ 1024, 0, 9 },
83	{ 1280, 2, 8 },
84	{ 1536, 1, 9 },
85	{ 1792, 3, 8 },
86	{ 2048, 0, 10 },
87	{ 2560, 2, 9 },
88	{ 3072, 1, 10 },
89	{ 3584, 3, 9 },
90	{ 4096, 0, 11 },
91	{ 5120, 2, 10 },
92	{ 6144, 1, 11 },
93	{ 7168, 3, 10 },
94	{ 8192, 0, 12 },
95	{ 10240, 2, 11 },
96	{ 12288, 1, 12 },
97	{ 14336, 3, 11 },
98	{ 16384, 0, 13 },
99	{ 20480, 2, 12 },
100	{ 24576, 1, 13 },
101	{ 28672, 3, 12 },
102	{ 32768, 0, 14 },
103	{ 40960, 2, 13 },
104	{ 49152, 1, 14 },
105	{ 57344, 3, 13 },
106	{ 65536, 0, 15 },
107	{ 81920, 2, 14 },
108	{ 98304, 1, 15 },
109	{ 114688, 3, 14 },
110	{ 163840, 2, 15 },
111	{ 229376, 3, 15 },
112	};
113
114	static mpc55xx_dspi_baudrate_scaler_entry mpc55xx_dspi_search_baudrate_scaler( uint32_t scaler, int min, int mid, int max)
115	{
116	if (scaler <= mpc55xx_dspi_baudrate_scaler_table [mid].scaler) {
117	max = mid;
118	} else {
119	min = mid;
120	}
121	mid = (min + max) / 2;
122	if (mid == min) {
123	return mpc55xx_dspi_baudrate_scaler_table [max];
124	} else {
125	return mpc55xx_dspi_search_baudrate_scaler( scaler, min, mid, max);
126	}
127	}
128
129	static uint32_t mpc55xx_dspi_push_data [8 * MPC55XX_DSPI_NUMBER] __attribute__ ((aligned (32)));
130
131	static inline void mpc55xx_dspi_store_push_data( mpc55xx_dspi_bus_entry *e)
132	{
133	mpc55xx_dspi_push_data [e->table_index * 8] = e->push_data.R;
134	rtems_cache_flush_multiple_data_lines( &mpc55xx_dspi_push_data [e->table_index * 8], 4);
135	}
136
137	static inline uint32_t mpc55xx_dspi_push_data_address( mpc55xx_dspi_bus_entry *e)
138	{
139	return (uint32_t) &mpc55xx_dspi_push_data [e->table_index * 8];
140	}
141
142	static inline uint32_t mpc55xx_dspi_nirvana_address( mpc55xx_dspi_bus_entry *e)
143	{
144	return (uint32_t) &mpc55xx_dspi_push_data [e->table_index * 8 + 1];
145	}
146
147	static rtems_status_code mpc55xx_dspi_init( rtems_libi2c_bus_t *bus)
148	{
149	rtems_status_code sc = RTEMS_SUCCESSFUL;
150	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
151	union DSPI_MCR_tag mcr = MPC55XX_ZERO_FLAGS;
152	union DSPI_CTAR_tag ctar = MPC55XX_ZERO_FLAGS;
153	union DSPI_RSER_tag rser = MPC55XX_ZERO_FLAGS;
154	struct tcd_t tcd_push = MPC55XX_EDMA_TCD_DEFAULT;
155	int i = 0;
156
157	/* eDMA receive */
158	sc = rtems_semaphore_create (
159	rtems_build_name ( 'S', 'P', 'I', 'R'),
160	0,
161	RTEMS_SIMPLE_BINARY_SEMAPHORE \| RTEMS_INHERIT_PRIORITY \| RTEMS_PRIORITY,
162	RTEMS_NO_PRIORITY,
163	&e->edma_channel_receive_update
164	);
165	CHECK_SC( sc, "Create receive update semaphore");
166
167	sc = mpc55xx_edma_obtain_channel( e->edma_channel_receive, &e->edma_channel_receive_error, e->edma_channel_receive_update);
168	CHECK_SC( sc, "Obtain receive eDMA channel");
169
170	/* eDMA transmit */
171	sc = rtems_semaphore_create (
172	rtems_build_name ( 'S', 'P', 'I', 'T'),
173	0,
174	RTEMS_SIMPLE_BINARY_SEMAPHORE \| RTEMS_INHERIT_PRIORITY \| RTEMS_PRIORITY,
175	RTEMS_NO_PRIORITY,
176	&e->edma_channel_transmit_update
177	);
178	CHECK_SC( sc, "Create transmit update semaphore");
179
180	sc = mpc55xx_edma_obtain_channel( e->edma_channel_transmit, &e->edma_channel_transmit_error, e->edma_channel_transmit_update);
181	CHECK_SC( sc, "Obtain transmit eDMA channel");
182
183	sc = mpc55xx_edma_obtain_channel( e->edma_channel_push, NULL, RTEMS_ID_NONE);
184	CHECK_SC( sc, "Obtain push eDMA channel");
185
186	tcd_push.SADDR = mpc55xx_dspi_push_data_address( e);
187	tcd_push.SSIZE = 2;
188	tcd_push.SOFF = 0;
189	tcd_push.DADDR = (uint32_t) &e->regs->PUSHR.R;
190	tcd_push.DSIZE = 2;
191	tcd_push.DOFF = 0;
192	tcd_push.NBYTES = 4;
193	tcd_push.CITER = 1;
194	tcd_push.BITER = 1;
195
196	EDMA.TCD [e->edma_channel_push] = tcd_push;
197
198	/* Module Control Register */
199	mcr.B.MSTR = e->master ? 1 : 0;
200	mcr.B.CONT_SCKE = 0;
201	mcr.B.DCONF = 0;
202	mcr.B.FRZ = 0;
203	mcr.B.MTFE = 0;
204	mcr.B.PCSSE = 0;
205	mcr.B.ROOE = 0;
206	mcr.B.PCSIS0 = 1;
207	mcr.B.PCSIS1 = 1;
208	mcr.B.PCSIS2 = 1;
209	mcr.B.PCSIS3 = 1;
210	mcr.B.PCSIS5 = 1;
211	mcr.B.MDIS = 0;
212	mcr.B.DIS_TXF = 0;
213	mcr.B.DIS_RXF = 0;
214	mcr.B.CLR_TXF = 0;
215	mcr.B.CLR_RXF = 0;
216	mcr.B.SMPL_PT = 0;
217	mcr.B.HALT = 0;
218
219	e->regs->MCR.R = mcr.R;
220
221	/* Clock and Transfer Attributes Register */
222	ctar.B.DBR = 0;
223	ctar.B.FMSZ = 0x7;
224	ctar.B.CPOL = 0;
225	ctar.B.CPHA = 0;
226	ctar.B.LSBFE = 0;
227	ctar.B.PCSSCK = 0;
228	ctar.B.PASC = 0;
229	ctar.B.PDT = 0;
230	ctar.B.PBR = 0;
231	ctar.B.CSSCK = 0;
232	ctar.B.ASC = 0;
233	ctar.B.DT = 0;
234	ctar.B.BR = 0;
235
236	for (i = 0; i < MPC55XX_DSPI_CTAR_NUMBER; ++i) {
237	e->regs->CTAR [i].R = ctar.R;
238	}
239
240	/* DMA/Interrupt Request Select and Enable Register */
241	rser.B.TFFFRE = 1;
242	rser.B.TFFFDIRS = 1;
243	rser.B.RFDFRE = 1;
244	rser.B.RFDFDIRS = 1;
245
246	e->regs->RSER.R = rser.R;
247
248	return RTEMS_SUCCESSFUL;
249	}
250
251	static rtems_status_code mpc55xx_dspi_send_start( rtems_libi2c_bus_t *bus)
252	{
253	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
254
255	/* Reset chip selects */
256	e->push_data.B.PCS0 = 0;
257	e->push_data.B.PCS1 = 0;
258	e->push_data.B.PCS2 = 0;
259	e->push_data.B.PCS3 = 0;
260	e->push_data.B.PCS4 = 0;
261	e->push_data.B.PCS5 = 0;
262	mpc55xx_dspi_store_push_data( e);
263
264	return RTEMS_SUCCESSFUL;
265	}
266
267	static rtems_status_code mpc55xx_dspi_send_stop( rtems_libi2c_bus_t *bus)
268	{
269	return RTEMS_SUCCESSFUL;
270	}
271
272	static rtems_status_code mpc55xx_dspi_send_addr( rtems_libi2c_bus_t *bus, uint32_t addr, int rw)
273	{
274	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
275	union DSPI_SR_tag sr = MPC55XX_ZERO_FLAGS;
276
277	/* Flush transmit and receive FIFO */
278	e->regs->MCR.B.CLR_TXF = 1;
279	e->regs->MCR.B.CLR_RXF = 1;
280
281	/* Clear status flags */
282	sr.B.EOQF = 1;
283	sr.B.TFFF = 1;
284	sr.B.RFDF = 1;
285	e->regs->SR.R = sr.R;
286
287	/* Frame command */
288	e->push_data.R = 0;
289	e->push_data.B.CONT = 0;
290	e->push_data.B.CTAS = MPC55XX_DSPI_CTAR_DEFAULT;
291	e->push_data.B.EOQ = 0;
292	e->push_data.B.CTCNT = 0;
293	switch (addr) {
294	case 0:
295	e->push_data.B.PCS0 = 1;
296	break;
297	case 1:
298	e->push_data.B.PCS1 = 1;
299	break;
300	case 2:
301	e->push_data.B.PCS2 = 1;
302	break;
303	case 3:
304	e->push_data.B.PCS3 = 1;
305	break;
306	case 4:
307	e->push_data.B.PCS4 = 1;
308	break;
309	case 5:
310	e->push_data.B.PCS5 = 1;
311	break;
312	default:
313	return -RTEMS_INVALID_ADDRESS;
314	}
315	mpc55xx_dspi_store_push_data( e);
316
317	return RTEMS_SUCCESSFUL;
318	}
319
320	/* FIXME, TODO */
321	extern uint32_t bsp_clock_speed;
322
323	static int mpc55xx_dspi_set_transfer_mode( rtems_libi2c_bus_t bus, const rtems_libi2c_tfr_mode_t mode)
324	{
325	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
326	union DSPI_CTAR_tag ctar = MPC55XX_ZERO_FLAGS;
327	uint32_t scaler = bsp_clock_speed / mode->baudrate;
328	mpc55xx_dspi_baudrate_scaler_entry bse = mpc55xx_dspi_search_baudrate_scaler( scaler, 0, MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE / 2, MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE);
329
330	if (mode->bits_per_char != 8) {
331	return -RTEMS_INVALID_NUMBER;
332	}
333
334	e->idle_char = mode->idle_char;
335
336	ctar.R = e->regs->CTAR [MPC55XX_DSPI_CTAR_DEFAULT].R;
337
338	ctar.B.PBR = bse.pbr;
339	ctar.B.BR = bse.br;
340
341	ctar.B.PCSSCK = 0;
342	ctar.B.CSSCK = 0;
343	ctar.B.PASC = 0;
344	ctar.B.ASC = 0;
345
346	ctar.B.LSBFE = mode->lsb_first ? 1 : 0;
347	ctar.B.CPOL = mode->clock_inv ? 1 : 0;
348	ctar.B.CPHA = mode->clock_phs ? 1 : 0;
349
350	e->regs->CTAR [MPC55XX_DSPI_CTAR_DEFAULT].R = ctar.R;
351
352	return 0;
353	}
354
355	/**
356	* @brief Writes @a n characters from @a out to bus @a bus and synchronously stores the received data in @a in.
357	*
358	* eDMA channel usage for transmission:
359	* @dot
360	* digraph push {
361	* push [label="Push Register"];
362	* push_data [label="Push Data"];
363	* idle_push_data [label="Idle Push Data"];
364	* out [shape=box,label="Output Buffer"];
365	* edge [color=red,fontcolor=red];
366	* push -> idle_push_data [label="Transmit Request",URL="\ref mpc55xx_dspi_bus_entry::edma_channel_transmit"];
367	* push -> out [label="Transmit Request",URL="\ref mpc55xx_dspi_bus_entry::edma_channel_transmit"];
368	* out -> push_data [label="Channel Link",URL="\ref mpc55xx_dspi_bus_entry::edma_channel_push"];
369	* edge [color=blue,fontcolor=blue];
370	* out -> push_data [label="Data"];
371	* push_data -> push [label="Data"];
372	* idle_push_data -> push [label="Data"];
373	* }
374	* @enddot
375	*
376	* eDMA channel usage for receiving:
377	* @dot
378	* digraph pop {
379	* pop [label="Pop Register"];
380	* nirvana [label="Nirvana"];
381	* in [shape=box,label="Input Buffer"];
382	* edge [color=red,fontcolor=red];
383	* pop -> nirvana [label="Receive Request",URL="\ref mpc55xx_dspi_bus_entry::edma_channel_receive"];
384	* pop -> in [label="Receive Request",URL="\ref mpc55xx_dspi_bus_entry::edma_channel_receive"];
385	* edge [color=blue,fontcolor=blue];
386	* pop -> nirvana [label="Data"];
387	* pop -> in [label="Data"];
388	* }
389	* @enddot
390	*/
391	static int mpc55xx_dspi_read_write( rtems_libi2c_bus_t bus, unsigned char in, const unsigned char *out, int n)
392	{
393	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
394
395	/* Non cache aligned characters */
396	int n_nc = n;
397
398	/* Cache aligned characters */
399	int n_c = 0;
400
401	/* Register addresses */
402	volatile void *push = &e->regs->PUSHR.R;
403	volatile void *pop = &e->regs->POPR.R;
404	volatile union DSPI_SR_tag *status = &e->regs->SR;
405
406	/* Push and pop data */
407	union DSPI_PUSHR_tag push_data = e->push_data;
408	union DSPI_POPR_tag pop_data;
409
410	/* Status register */
411	union DSPI_SR_tag sr;
412
413	/* Read and write indices */
414	int r = 0;
415	int w = 0;
416
417	if (n == 0) {
418	return 0;
419	} else if (in == NULL && out == NULL) {
420	return -RTEMS_INVALID_ADDRESS;
421	}
422
423	if (n > MPC55XX_DSPI_EDMA_MAGIC_SIZE) {
424	n_nc = (int) mpc55xx_non_cache_aligned_size( in);
425	n_c = (int) mpc55xx_cache_aligned_size( in, (size_t) n);
426	if (n_c > EDMA_TCD_BITER_LINKED_SIZE) {
427	SYSLOG_WARNING( "Buffer size out of range, cannot use eDMA\n");
428	n_nc = n;
429	n_c = 0;
430	} else if (n_nc + n_c != n) {
431	SYSLOG_WARNING( "Input buffer not proper cache aligned, cannot use eDMA\n");
432	n_nc = n;
433	n_c = 0;
434	}
435	}
436
437	#ifdef DEBUG
438	if (e->regs->SR.B.TXCTR != e->regs->SR.B.RXCTR) {
439	SYSLOG_WARNING( "FIFO counter not equal\n");
440	}
441	#endif /* DEBUG */
442
443	/* Direct IO */
444	if (out == NULL) {
445	push_data.B.TXDATA = e->idle_char;
446	while (r < n_nc \|\| w < n_nc) {
447	/* Wait for available FIFO */
448	do {
449	sr.R = status->R;
450	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
451
452	/* Write */
453	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
454	++w;
455	ppc_write_word( push_data.R, push);
456	}
457
458	/* Read */
459	if (r < n_nc && sr.B.RXCTR != 0) {
460	pop_data.R = ppc_read_word( pop);
461	in [r] = (unsigned char) pop_data.B.RXDATA;
462	++r;
463	}
464	}
465	} else if (in == NULL) {
466	while (r < n_nc \|\| w < n_nc) {
467	/* Wait for available FIFO */
468	do {
469	sr.R = status->R;
470	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
471
472	/* Write */
473	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
474	push_data.B.TXDATA = out [w];
475	++w;
476	ppc_write_word( push_data.R, push);
477	}
478
479	/* Read */
480	if (r < n_nc && sr.B.RXCTR != 0) {
481	pop_data.R = ppc_read_word( pop);
482	++r;
483	}
484	}
485	} else {
486	while (r < n_nc \|\| w < n_nc) {
487	/* Wait for available FIFO */
488	do {
489	sr.R = status->R;
490	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
491
492	/* Write */
493	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
494	push_data.B.TXDATA = out [w];
495	++w;
496	ppc_write_word( push_data.R, push);
497	}
498
499	/* Read */
500	if (r < n_nc && sr.B.RXCTR != 0) {
501	pop_data.R = ppc_read_word( pop);
502	in [r] = (unsigned char) pop_data.B.RXDATA;
503	++r;
504	}
505	}
506	}
507
508	/* eDMA transfers */
509	if (n_c > 0) {
510	rtems_status_code sc = RTEMS_SUCCESSFUL;
511	unsigned char *in_c = in + n_nc;
512	const unsigned char *out_c = out + n_nc;
513	struct tcd_t tcd_transmit = MPC55XX_EDMA_TCD_DEFAULT;
514	struct tcd_t tcd_receive = MPC55XX_EDMA_TCD_DEFAULT;
515
516	/* Cache operations */
517	rtems_cache_flush_multiple_data_lines( out_c, (size_t) n_c);
518	rtems_cache_invalidate_multiple_data_lines( in_c, (size_t) n_c);
519
520	/* Set transmit TCD */
521	if (out == NULL) {
522	e->push_data.B.TXDATA = e->idle_char;
523	mpc55xx_dspi_store_push_data( e);
524	tcd_transmit.SADDR = mpc55xx_dspi_push_data_address( e);
525	tcd_transmit.SSIZE = 2;
526	tcd_transmit.SOFF = 0;
527	tcd_transmit.DADDR = (uint32_t) push;
528	tcd_transmit.DSIZE = 2;
529	tcd_transmit.DOFF = 0;
530	tcd_transmit.NBYTES = 4;
531	tcd_transmit.CITER = n_c;
532	tcd_transmit.BITER = n_c;
533	} else {
534	EDMA.CDSBR.R = e->edma_channel_transmit;
535	tcd_transmit.SADDR = (uint32_t) out_c;
536	tcd_transmit.SSIZE = 0;
537	tcd_transmit.SOFF = 1;
538	tcd_transmit.DADDR = mpc55xx_dspi_push_data_address( e) + 3;
539	tcd_transmit.DSIZE = 0;
540	tcd_transmit.DOFF = 0;
541	tcd_transmit.NBYTES = 1;
542	tcd_transmit.CITERE_LINK = 1;
543	tcd_transmit.BITERE_LINK = 1;
544	tcd_transmit.MAJORLINKCH = e->edma_channel_push;
545	tcd_transmit.CITER = EDMA_TCD_LINK_AND_BITER( e->edma_channel_push, n_c);
546	tcd_transmit.BITER = EDMA_TCD_LINK_AND_BITER( e->edma_channel_push, n_c);
547	tcd_transmit.MAJORE_LINK = 1;
548	}
549	tcd_transmit.D_REQ = 1;
550	tcd_transmit.INT_MAJ = 1;
551	EDMA.TCD [e->edma_channel_transmit] = tcd_transmit;
552
553	/* Set receive TCD */
554	if (in == NULL) {
555	tcd_receive.DOFF = 0;
556	tcd_receive.DADDR = mpc55xx_dspi_nirvana_address( e);
557	} else {
558	tcd_receive.DOFF = 1;
559	tcd_receive.DADDR = (uint32_t) in_c;
560	}
561	tcd_receive.SADDR = (uint32_t) pop + 3;
562	tcd_receive.SSIZE = 0;
563	tcd_receive.SOFF = 0;
564	tcd_receive.DSIZE = 0;
565	tcd_receive.NBYTES = 1;
566	tcd_receive.D_REQ = 1;
567	tcd_receive.INT_MAJ = 1;
568	tcd_receive.CITER = n_c;
569	tcd_receive.BITER = n_c;
570	EDMA.TCD [e->edma_channel_receive] = tcd_receive;
571
572	/* Clear request flags */
573	sr.R = 0;
574	sr.B.TFFF = 1;
575	sr.B.RFDF = 1;
576	status->R = sr.R;
577
578	/* Enable hardware requests */
579	sc = mpc55xx_edma_enable_hardware_requests( e->edma_channel_receive, true);
580	CHECK_SCRV( sc, "Enable receive hardware requests");
581	sc = mpc55xx_edma_enable_hardware_requests( e->edma_channel_transmit, true);
582	CHECK_SCRV( sc, "Enable transmit hardware requests");
583
584	/* Wait for transmit update */
585	sc = rtems_semaphore_obtain( e->edma_channel_transmit_update, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
586	CHECK_SCRV( sc, "Transmit update");
587	if (e->edma_channel_transmit_error != 0) {
588	SYSLOG_ERROR( "Transmit error status: 0x%08x\n", e->edma_channel_transmit_error);
589	e->edma_channel_transmit_error = 0;
590	return -RTEMS_IO_ERROR;
591	}
592
593	/* Wait for receive update */
594	sc = rtems_semaphore_obtain( e->edma_channel_receive_update, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
595	CHECK_SCRV( sc, "Receive update");
596	if (e->edma_channel_receive_error != 0) {
597	SYSLOG_ERROR( "Receive error status: 0x%08x\n", e->edma_channel_receive_error);
598	e->edma_channel_receive_error = 0;
599	return -RTEMS_IO_ERROR;
600	}
601	}
602
603	return n;
604	}
605
606	/**
607	* @brief Reads @a n characters from bus @a bus and stores it in @a in.
608	*
609	* Writes idle characters to receive data.
610	*
611	* @see mpc55xx_dspi_read_write().
612	*/
613	static int mpc55xx_dspi_read( rtems_libi2c_bus_t bus, unsigned char in, int n)
614	{
615	return mpc55xx_dspi_read_write( bus, in, NULL, n);
616	}
617
618	/**
619	* @brief Writes @a n characters from @a out to bus @a bus.
620	*
621	* Discards the synchronously received data.
622	*
623	* @see mpc55xx_dspi_read_write().
624	*/
625	static int mpc55xx_dspi_write( rtems_libi2c_bus_t bus, unsigned char out, int n)
626	{
627	return mpc55xx_dspi_read_write( bus, NULL, out, n);
628	}
629
630	static int mpc55xx_dspi_ioctl( rtems_libi2c_bus_t bus, int cmd, void arg)
631	{
632	int rv = -1;
633	switch (cmd) {
634	case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
635	rv = mpc55xx_dspi_set_transfer_mode( bus, (const rtems_libi2c_tfr_mode_t *) arg);
636	break;
637	case RTEMS_LIBI2C_IOCTL_READ_WRITE:
638	rv = mpc55xx_dspi_read_write(
639	bus,
640	((rtems_libi2c_read_write_t *) arg)->rd_buf,
641	((rtems_libi2c_read_write_t *) arg)->wr_buf,
642	((rtems_libi2c_read_write_t *) arg)->byte_cnt
643	);
644	break;
645	default:
646	rv = -RTEMS_NOT_DEFINED;
647	break;
648	}
649	return rv;
650	}
651
652	static const rtems_libi2c_bus_ops_t mpc55xx_dspi_ops = {
653	.init = mpc55xx_dspi_init,
654	.send_start = mpc55xx_dspi_send_start,
655	.send_stop = mpc55xx_dspi_send_stop,
656	.send_addr = mpc55xx_dspi_send_addr,
657	.read_bytes = mpc55xx_dspi_read,
658	.write_bytes = mpc55xx_dspi_write,
659	.ioctl = mpc55xx_dspi_ioctl
660	};
661
662	mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [MPC55XX_DSPI_NUMBER] = { {
663	/* DSPI A */
664	.bus = {
665	.ops = &mpc55xx_dspi_ops,
666	.size = sizeof( mpc55xx_dspi_bus_entry)
667	},
668	.table_index = 0,
669	.bus_number = 0,
670	.regs = &DSPI_A,
671	.master = 1,
672	.push_data = MPC55XX_ZERO_FLAGS,
673	.edma_channel_transmit = 32,
674	.edma_channel_push = 43,
675	.edma_channel_receive = 33,
676	.edma_channel_transmit_update = 0,
677	.edma_channel_receive_update = 0,
678	.edma_channel_transmit_error = 0,
679	.edma_channel_receive_error = 0,
680	.idle_char = 0xffffffff,
681	}, {
682	/* DSPI B */
683	.bus = {
684	.ops = &mpc55xx_dspi_ops,
685	.size = sizeof( mpc55xx_dspi_bus_entry)
686	},
687	.table_index = 1,
688	.bus_number = 0,
689	.regs = &DSPI_B,
690	.master = 1,
691	.push_data = MPC55XX_ZERO_FLAGS,
692	.edma_channel_transmit = 12,
693	.edma_channel_push = 10,
694	.edma_channel_receive = 13,
695	.edma_channel_transmit_update = 0,
696	.edma_channel_receive_update = 0,
697	.edma_channel_transmit_error = 0,
698	.edma_channel_receive_error = 0,
699	.idle_char = 0xffffffff,
700	}, {
701	/* DSPI C */
702	.bus = {
703	.ops = &mpc55xx_dspi_ops,
704	.size = sizeof( mpc55xx_dspi_bus_entry)
705	},
706	.table_index = 2,
707	.bus_number = 0,
708	.regs = &DSPI_C,
709	.master = 1,
710	.push_data = MPC55XX_ZERO_FLAGS,
711	.edma_channel_transmit = 14,
712	.edma_channel_push = 11,
713	.edma_channel_receive = 15,
714	.edma_channel_transmit_update = 0,
715	.edma_channel_receive_update = 0,
716	.edma_channel_transmit_error = 0,
717	.edma_channel_receive_error = 0,
718	.idle_char = 0xffffffff,
719	}, {
720	/* DSPI D */
721	.bus = {
722	.ops = &mpc55xx_dspi_ops,
723	.size = sizeof( mpc55xx_dspi_bus_entry)
724	},
725	.table_index = 3,
726	.bus_number = 0,
727	.regs = &DSPI_D,
728	.master = 1,
729	.push_data = MPC55XX_ZERO_FLAGS,
730	.edma_channel_transmit = 16,
731	.edma_channel_push = 18,
732	.edma_channel_receive = 17,
733	.edma_channel_transmit_update = 0,
734	.edma_channel_receive_update = 0,
735	.edma_channel_transmit_error = 0,
736	.edma_channel_receive_error = 0,
737	.idle_char = 0xffffffff,
738	},
739	};

Note: See TracBrowser for help on using the repository browser.

Download in other formats: