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source: rtems/c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c @ 0e27119

4.115

Last change on this file since 0e27119 was 0e27119, checked in by Joel Sherrill <joel.sherrill@…>, on 10/11/12 at 20:52:18
Use proper 3 line form of license text
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1	/**
2	* @file
3	*
4	* @ingroup mpc55xx_dspi
5	*
6	* @brief Source file for the LibI2C bus driver for the Deserial Serial Peripheral Interface (DSPI).
7	*/
8
9	/*
10	* Copyright (c) 2008
11	* Embedded Brains GmbH
12	* Obere Lagerstr. 30
13	* D-82178 Puchheim
14	* Germany
15	* rtems@embedded-brains.de
16	*
17	* The license and distribution terms for this file may be
18	* found in the file LICENSE in this distribution or at
19	* http://www.rtems.com/license/LICENSE.
20	*/
21
22	#include <mpc55xx/regs.h>
23	#include <mpc55xx/dspi.h>
24	#include <mpc55xx/mpc55xx.h>
25
26	#include <bsp/irq.h>
27
28	#include <libcpu/powerpc-utility.h>
29
30	#define RTEMS_STATUS_CHECKS_USE_PRINTK
31
32	#include <rtems/status-checks.h>
33
34	#define MPC55XX_DSPI_FIFO_SIZE 4
35
36	#define MPC55XX_DSPI_CTAR_NUMBER 8
37
38	#define MPC55XX_DSPI_CTAR_DEFAULT 0
39
40	#define MPC55XX_DSPI_EDMA_MAGIC_SIZE 128
41
42	#define MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE 63
43
44	typedef struct {
45	uint32_t scaler : 26;
46	uint32_t pbr : 2;
47	uint32_t br : 4;
48	} mpc55xx_dspi_baudrate_scaler_entry;
49
50	static const mpc55xx_dspi_baudrate_scaler_entry mpc55xx_dspi_baudrate_scaler_table [MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE] = {
51	{ 4, 0, 0 },
52	{ 6, 1, 0 },
53	{ 8, 0, 1 },
54	{ 10, 2, 0 },
55	{ 12, 1, 1 },
56	{ 14, 3, 0 },
57	{ 16, 0, 3 },
58	{ 18, 1, 2 },
59	{ 20, 2, 1 },
60	{ 24, 1, 3 },
61	{ 28, 3, 1 },
62	{ 30, 2, 2 },
63	{ 32, 0, 4 },
64	{ 40, 2, 3 },
65	{ 42, 3, 2 },
66	{ 48, 1, 4 },
67	{ 56, 3, 3 },
68	{ 64, 0, 5 },
69	{ 80, 2, 4 },
70	{ 96, 1, 5 },
71	{ 112, 3, 4 },
72	{ 128, 0, 6 },
73	{ 160, 2, 5 },
74	{ 192, 1, 6 },
75	{ 224, 3, 5 },
76	{ 256, 0, 7 },
77	{ 320, 2, 6 },
78	{ 384, 1, 7 },
79	{ 448, 3, 6 },
80	{ 512, 0, 8 },
81	{ 640, 2, 7 },
82	{ 768, 1, 8 },
83	{ 896, 3, 7 },
84	{ 1024, 0, 9 },
85	{ 1280, 2, 8 },
86	{ 1536, 1, 9 },
87	{ 1792, 3, 8 },
88	{ 2048, 0, 10 },
89	{ 2560, 2, 9 },
90	{ 3072, 1, 10 },
91	{ 3584, 3, 9 },
92	{ 4096, 0, 11 },
93	{ 5120, 2, 10 },
94	{ 6144, 1, 11 },
95	{ 7168, 3, 10 },
96	{ 8192, 0, 12 },
97	{ 10240, 2, 11 },
98	{ 12288, 1, 12 },
99	{ 14336, 3, 11 },
100	{ 16384, 0, 13 },
101	{ 20480, 2, 12 },
102	{ 24576, 1, 13 },
103	{ 28672, 3, 12 },
104	{ 32768, 0, 14 },
105	{ 40960, 2, 13 },
106	{ 49152, 1, 14 },
107	{ 57344, 3, 13 },
108	{ 65536, 0, 15 },
109	{ 81920, 2, 14 },
110	{ 98304, 1, 15 },
111	{ 114688, 3, 14 },
112	{ 163840, 2, 15 },
113	{ 229376, 3, 15 },
114	};
115
116	static void mpc55xx_dspi_edma_done( mpc55xx_edma_channel_entry *e, uint32_t error_status)
117	{
118	rtems_semaphore_release( e->id);
119
120	if (error_status != 0) {
121	RTEMS_SYSLOG_ERROR( "eDMA error: 0x%08x\n", error_status);
122	}
123	}
124
125	static mpc55xx_dspi_baudrate_scaler_entry mpc55xx_dspi_search_baudrate_scaler( uint32_t scaler, int min, int mid, int max)
126	{
127	if (scaler <= mpc55xx_dspi_baudrate_scaler_table [mid].scaler) {
128	max = mid;
129	} else {
130	min = mid;
131	}
132	mid = (min + max) / 2;
133	if (mid == min) {
134	return mpc55xx_dspi_baudrate_scaler_table [max];
135	} else {
136	return mpc55xx_dspi_search_baudrate_scaler( scaler, min, mid, max);
137	}
138	}
139
140	static uint32_t mpc55xx_dspi_push_data [8 * MPC55XX_DSPI_NUMBER] __attribute__ ((aligned (32)));
141
142	static inline void mpc55xx_dspi_store_push_data( mpc55xx_dspi_bus_entry *e)
143	{
144	mpc55xx_dspi_push_data [e->table_index * 8] = e->push_data.R;
145	rtems_cache_flush_multiple_data_lines( &mpc55xx_dspi_push_data [e->table_index * 8], 4);
146	}
147
148	static inline uint32_t mpc55xx_dspi_push_data_address( mpc55xx_dspi_bus_entry *e)
149	{
150	return (uint32_t) &mpc55xx_dspi_push_data [e->table_index * 8];
151	}
152
153	static inline uint32_t mpc55xx_dspi_nirvana_address( mpc55xx_dspi_bus_entry *e)
154	{
155	return (uint32_t) &mpc55xx_dspi_push_data [e->table_index * 8 + 1];
156	}
157
158	static rtems_status_code mpc55xx_dspi_init( rtems_libi2c_bus_t *bus)
159	{
160	rtems_status_code sc = RTEMS_SUCCESSFUL;
161	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
162	union DSPI_MCR_tag mcr = MPC55XX_ZERO_FLAGS;
163	union DSPI_CTAR_tag ctar = MPC55XX_ZERO_FLAGS;
164	union DSPI_RSER_tag rser = MPC55XX_ZERO_FLAGS;
165	struct tcd_t tcd_push = EDMA_TCD_DEFAULT;
166	int i = 0;
167
168	/* eDMA receive */
169	sc = rtems_semaphore_create (
170	rtems_build_name ( 'S', 'P', 'I', 'R'),
171	0,
172	RTEMS_SIMPLE_BINARY_SEMAPHORE,
173	0,
174	&e->edma_receive.id
175	);
176	RTEMS_CHECK_SC( sc, "create receive update semaphore");
177
178	sc = mpc55xx_edma_obtain_channel( &e->edma_receive, MPC55XX_INTC_DEFAULT_PRIORITY);
179	RTEMS_CHECK_SC( sc, "obtain receive eDMA channel");
180
181	/* eDMA transmit */
182	sc = rtems_semaphore_create (
183	rtems_build_name ( 'S', 'P', 'I', 'T'),
184	0,
185	RTEMS_SIMPLE_BINARY_SEMAPHORE,
186	0,
187	&e->edma_transmit.id
188	);
189	RTEMS_CHECK_SC( sc, "create transmit update semaphore");
190
191	sc = mpc55xx_edma_obtain_channel( &e->edma_transmit, MPC55XX_INTC_DEFAULT_PRIORITY);
192	RTEMS_CHECK_SC( sc, "obtain transmit eDMA channel");
193
194	sc = mpc55xx_edma_obtain_channel( &e->edma_push, MPC55XX_INTC_DEFAULT_PRIORITY);
195	RTEMS_CHECK_SC( sc, "obtain push eDMA channel");
196
197	tcd_push.SADDR = mpc55xx_dspi_push_data_address( e);
198	tcd_push.SDF.B.SSIZE = 2;
199	tcd_push.SDF.B.SOFF = 0;
200	tcd_push.DADDR = (uint32_t) &e->regs->PUSHR.R;
201	tcd_push.SDF.B.DSIZE = 2;
202	tcd_push.CDF.B.DOFF = 0;
203	tcd_push.NBYTES = 4;
204	tcd_push.CDF.B.CITER = 1;
205	tcd_push.BMF.B.BITER = 1;
206
207	EDMA.TCD [e->edma_push.channel] = tcd_push;
208
209	/* Module Control Register */
210	mcr.B.MSTR = e->master ? 1 : 0;
211	mcr.B.CONT_SCKE = 0;
212	mcr.B.DCONF = 0;
213	mcr.B.FRZ = 0;
214	mcr.B.MTFE = 0;
215	mcr.B.PCSSE = 0;
216	mcr.B.ROOE = 0;
217	mcr.B.PCSIS0 = 1;
218	mcr.B.PCSIS1 = 1;
219	mcr.B.PCSIS2 = 1;
220	mcr.B.PCSIS3 = 1;
221	mcr.B.PCSIS5 = 1;
222	mcr.B.MDIS = 0;
223	mcr.B.DIS_TXF = 0;
224	mcr.B.DIS_RXF = 0;
225	mcr.B.CLR_TXF = 0;
226	mcr.B.CLR_RXF = 0;
227	mcr.B.SMPL_PT = 0;
228	mcr.B.HALT = 0;
229
230	e->regs->MCR.R = mcr.R;
231
232	/* Clock and Transfer Attributes Register */
233	ctar.B.DBR = 0;
234	ctar.B.FMSZ = 0x7;
235	ctar.B.CPOL = 0;
236	ctar.B.CPHA = 0;
237	ctar.B.LSBFE = 0;
238	ctar.B.PCSSCK = 0;
239	ctar.B.PASC = 0;
240	ctar.B.PDT = 0;
241	ctar.B.PBR = 0;
242	ctar.B.CSSCK = 0;
243	ctar.B.ASC = 0;
244	ctar.B.DT = 0;
245	ctar.B.BR = 0;
246
247	for (i = 0; i < MPC55XX_DSPI_CTAR_NUMBER; ++i) {
248	e->regs->CTAR [i].R = ctar.R;
249	}
250
251	/* DMA/Interrupt Request Select and Enable Register */
252	rser.B.TFFFRE = 1;
253	rser.B.TFFFDIRS = 1;
254	rser.B.RFDFRE = 1;
255	rser.B.RFDFDIRS = 1;
256
257	e->regs->RSER.R = rser.R;
258
259	return RTEMS_SUCCESSFUL;
260	}
261
262	static rtems_status_code mpc55xx_dspi_send_start( rtems_libi2c_bus_t *bus)
263	{
264	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
265
266	/* Reset chip selects */
267	e->push_data.B.PCS0 = 0;
268	e->push_data.B.PCS1 = 0;
269	e->push_data.B.PCS2 = 0;
270	e->push_data.B.PCS3 = 0;
271	e->push_data.B.PCS4 = 0;
272	e->push_data.B.PCS5 = 0;
273	mpc55xx_dspi_store_push_data( e);
274
275	return RTEMS_SUCCESSFUL;
276	}
277
278	static rtems_status_code mpc55xx_dspi_send_stop( rtems_libi2c_bus_t *bus)
279	{
280	return RTEMS_SUCCESSFUL;
281	}
282
283	static rtems_status_code mpc55xx_dspi_send_addr( rtems_libi2c_bus_t *bus, uint32_t addr, int rw)
284	{
285	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
286	union DSPI_SR_tag sr = MPC55XX_ZERO_FLAGS;
287
288	/* Flush transmit and receive FIFO */
289	e->regs->MCR.B.CLR_TXF = 1;
290	e->regs->MCR.B.CLR_RXF = 1;
291
292	/* Clear status flags */
293	sr.B.EOQF = 1;
294	sr.B.TFFF = 1;
295	sr.B.RFDF = 1;
296	e->regs->SR.R = sr.R;
297
298	/* Frame command */
299	e->push_data.R = 0;
300	e->push_data.B.CONT = 0;
301	e->push_data.B.CTAS = MPC55XX_DSPI_CTAR_DEFAULT;
302	e->push_data.B.EOQ = 0;
303	e->push_data.B.CTCNT = 0;
304	switch (addr) {
305	case 0:
306	e->push_data.B.PCS0 = 1;
307	break;
308	case 1:
309	e->push_data.B.PCS1 = 1;
310	break;
311	case 2:
312	e->push_data.B.PCS2 = 1;
313	break;
314	case 3:
315	e->push_data.B.PCS3 = 1;
316	break;
317	case 4:
318	e->push_data.B.PCS4 = 1;
319	break;
320	case 5:
321	e->push_data.B.PCS5 = 1;
322	break;
323	default:
324	return -RTEMS_INVALID_ADDRESS;
325	}
326	mpc55xx_dspi_store_push_data( e);
327
328	return RTEMS_SUCCESSFUL;
329	}
330
331	/* FIXME, TODO */
332	extern uint32_t bsp_clock_speed;
333
334	static int mpc55xx_dspi_set_transfer_mode( rtems_libi2c_bus_t bus, const rtems_libi2c_tfr_mode_t mode)
335	{
336	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
337	union DSPI_CTAR_tag ctar = MPC55XX_ZERO_FLAGS;
338
339	if (mode->bits_per_char != 8) {
340	return -RTEMS_INVALID_NUMBER;
341	}
342
343	e->idle_char = mode->idle_char;
344
345	ctar.R = e->regs->CTAR [MPC55XX_DSPI_CTAR_DEFAULT].R;
346
347	ctar.B.PCSSCK = 0;
348	ctar.B.CSSCK = 0;
349	ctar.B.PASC = 0;
350	ctar.B.ASC = 0;
351
352	ctar.B.LSBFE = mode->lsb_first ? 1 : 0;
353	ctar.B.CPOL = mode->clock_inv ? 1 : 0;
354	ctar.B.CPHA = mode->clock_phs ? 1 : 0;
355
356	if (mode->baudrate != e->baud) {
357	uint32_t scaler = bsp_clock_speed / mode->baudrate;
358	mpc55xx_dspi_baudrate_scaler_entry bse = mpc55xx_dspi_search_baudrate_scaler( scaler, 0, MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE / 2, MPC55XX_DSPI_BAUDRATE_SCALER_TABLE_SIZE);
359
360	ctar.B.PBR = bse.pbr;
361	ctar.B.BR = bse.br;
362
363	e->baud = mode->baudrate;
364	}
365
366	e->regs->CTAR [MPC55XX_DSPI_CTAR_DEFAULT].R = ctar.R;
367
368	return 0;
369	}
370
371	/**
372	* @brief Writes @a n characters from @a out to bus @a bus and synchronously stores the received data in @a in.
373	*
374	* eDMA channel usage for transmission:
375	* @dot
376	* digraph push {
377	* push [label="Push Register"];
378	* push_data [label="Push Data"];
379	* idle_push_data [label="Idle Push Data"];
380	* out [shape=box,label="Output Buffer"];
381	* edge [color=red,fontcolor=red];
382	* push -> idle_push_data [label="Transmit Request",URL="\ref mpc55xx_dspi_bus_entry::edma_transmit"];
383	* push -> out [label="Transmit Request",URL="\ref mpc55xx_dspi_bus_entry::edma_transmit"];
384	* out -> push_data [label="Channel Link",URL="\ref mpc55xx_dspi_bus_entry::edma_push"];
385	* edge [color=blue,fontcolor=blue];
386	* out -> push_data [label="Data"];
387	* push_data -> push [label="Data"];
388	* idle_push_data -> push [label="Data"];
389	* }
390	* @enddot
391	*
392	* eDMA channel usage for receiving:
393	* @dot
394	* digraph pop {
395	* pop [label="Pop Register"];
396	* nirvana [label="Nirvana"];
397	* in [shape=box,label="Input Buffer"];
398	* edge [color=red,fontcolor=red];
399	* pop -> nirvana [label="Receive Request",URL="\ref mpc55xx_dspi_bus_entry::edma_receive"];
400	* pop -> in [label="Receive Request",URL="\ref mpc55xx_dspi_bus_entry::edma_receive"];
401	* edge [color=blue,fontcolor=blue];
402	* pop -> nirvana [label="Data"];
403	* pop -> in [label="Data"];
404	* }
405	* @enddot
406	*/
407	static int mpc55xx_dspi_read_write( rtems_libi2c_bus_t bus, unsigned char in, const unsigned char *out, int n)
408	{
409	mpc55xx_dspi_bus_entry e = (mpc55xx_dspi_bus_entry ) bus;
410
411	/* Non cache aligned characters */
412	int n_nc = n;
413
414	/* Cache aligned characters */
415	int n_c = 0;
416
417	/* Register addresses */
418	volatile void *push = &e->regs->PUSHR.R;
419	volatile void *pop = &e->regs->POPR.R;
420	volatile union DSPI_SR_tag *status = &e->regs->SR;
421
422	/* Push and pop data */
423	union DSPI_PUSHR_tag push_data = e->push_data;
424	union DSPI_POPR_tag pop_data;
425
426	/* Status register */
427	union DSPI_SR_tag sr;
428
429	/* Read and write indices */
430	int r = 0;
431	int w = 0;
432
433	if (n == 0) {
434	return 0;
435	} else if (in == NULL && out == NULL) {
436	return -RTEMS_INVALID_ADDRESS;
437	}
438
439	if (n > MPC55XX_DSPI_EDMA_MAGIC_SIZE) {
440	n_nc = (int) mpc55xx_non_cache_aligned_size( in);
441	n_c = (int) mpc55xx_cache_aligned_size( in, (size_t) n);
442	if (n_c > EDMA_TCD_BITER_LINKED_SIZE) {
443	RTEMS_SYSLOG_WARNING( "buffer size out of range, cannot use eDMA\n");
444	n_nc = n;
445	n_c = 0;
446	} else if (n_nc + n_c != n) {
447	RTEMS_SYSLOG_WARNING( "input buffer not proper cache aligned, cannot use eDMA\n");
448	n_nc = n;
449	n_c = 0;
450	}
451	}
452
453	#ifdef DEBUG
454	if (e->regs->SR.B.TXCTR != e->regs->SR.B.RXCTR) {
455	RTEMS_SYSLOG_WARNING( "FIFO counter not equal\n");
456	}
457	#endif /* DEBUG */
458
459	/* Direct IO */
460	if (out == NULL) {
461	push_data.B.TXDATA = e->idle_char;
462	while (r < n_nc \|\| w < n_nc) {
463	/* Wait for available FIFO */
464	do {
465	sr.R = status->R;
466	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
467
468	/* Write */
469	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
470	++w;
471	ppc_write_word( push_data.R, push);
472	}
473
474	/* Read */
475	if (r < n_nc && sr.B.RXCTR != 0) {
476	pop_data.R = ppc_read_word( pop);
477	in [r] = (unsigned char) pop_data.B.RXDATA;
478	++r;
479	}
480	}
481	} else if (in == NULL) {
482	while (r < n_nc \|\| w < n_nc) {
483	/* Wait for available FIFO */
484	do {
485	sr.R = status->R;
486	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
487
488	/* Write */
489	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
490	push_data.B.TXDATA = out [w];
491	++w;
492	ppc_write_word( push_data.R, push);
493	}
494
495	/* Read */
496	if (r < n_nc && sr.B.RXCTR != 0) {
497	pop_data.R = ppc_read_word( pop);
498	++r;
499	}
500	}
501	} else {
502	while (r < n_nc \|\| w < n_nc) {
503	/* Wait for available FIFO */
504	do {
505	sr.R = status->R;
506	} while (sr.B.TXCTR == MPC55XX_DSPI_FIFO_SIZE && sr.B.RXCTR == 0);
507
508	/* Write */
509	if (w < n_nc && (w - r) < MPC55XX_DSPI_FIFO_SIZE && sr.B.TXCTR != MPC55XX_DSPI_FIFO_SIZE) {
510	push_data.B.TXDATA = out [w];
511	++w;
512	ppc_write_word( push_data.R, push);
513	}
514
515	/* Read */
516	if (r < n_nc && sr.B.RXCTR != 0) {
517	pop_data.R = ppc_read_word( pop);
518	in [r] = (unsigned char) pop_data.B.RXDATA;
519	++r;
520	}
521	}
522	}
523
524	/* eDMA transfers */
525	if (n_c > 0) {
526	rtems_status_code sc = RTEMS_SUCCESSFUL;
527	unsigned char *in_c = in + n_nc;
528	const unsigned char *out_c = out + n_nc;
529	struct tcd_t tcd_transmit = EDMA_TCD_DEFAULT;
530	struct tcd_t tcd_receive = EDMA_TCD_DEFAULT;
531
532	/* Cache operations */
533	rtems_cache_flush_multiple_data_lines( out_c, (size_t) n_c);
534	rtems_cache_invalidate_multiple_data_lines( in_c, (size_t) n_c);
535
536	/* Set transmit TCD */
537	if (out == NULL) {
538	e->push_data.B.TXDATA = e->idle_char;
539	mpc55xx_dspi_store_push_data( e);
540	tcd_transmit.SADDR = mpc55xx_dspi_push_data_address( e);
541	tcd_transmit.SDF.B.SSIZE = 2;
542	tcd_transmit.SDF.B.SOFF = 0;
543	tcd_transmit.DADDR = (uint32_t) push;
544	tcd_transmit.SDF.B.DSIZE = 2;
545	tcd_transmit.CDF.B.DOFF = 0;
546	tcd_transmit.NBYTES = 4;
547	tcd_transmit.CDF.B.CITER = n_c;
548	tcd_transmit.BMF.B.BITER = n_c;
549	} else {
550	EDMA.CDSBR.R = e->edma_transmit.channel;
551	tcd_transmit.SADDR = (uint32_t) out_c;
552	tcd_transmit.SDF.B.SSIZE = 0;
553	tcd_transmit.SDF.B.SOFF = 1;
554	tcd_transmit.DADDR = mpc55xx_dspi_push_data_address( e) + 3;
555	tcd_transmit.SDF.B.DSIZE = 0;
556	tcd_transmit.CDF.B.DOFF = 0;
557	tcd_transmit.NBYTES = 1;
558	tcd_transmit.CDF.B.CITERE_LINK = 1;
559	tcd_transmit.BMF.B.BITERE_LINK = 1;
560	tcd_transmit.BMF.B.MAJORLINKCH = e->edma_push.channel;
561	tcd_transmit.CDF.B.CITER = EDMA_TCD_LINK_AND_BITER( e->edma_push.channel, n_c);
562	tcd_transmit.BMF.B.BITER = EDMA_TCD_LINK_AND_BITER( e->edma_push.channel, n_c);
563	tcd_transmit.BMF.B.MAJORE_LINK = 1;
564	}
565	tcd_transmit.BMF.B.D_REQ = 1;
566	tcd_transmit.BMF.B.INT_MAJ = 1;
567	EDMA.TCD [e->edma_transmit.channel] = tcd_transmit;
568
569	/* Set receive TCD */
570	if (in == NULL) {
571	tcd_receive.CDF.B.DOFF = 0;
572	tcd_receive.DADDR = mpc55xx_dspi_nirvana_address( e);
573	} else {
574	tcd_receive.CDF.B.DOFF = 1;
575	tcd_receive.DADDR = (uint32_t) in_c;
576	}
577	tcd_receive.SADDR = (uint32_t) pop + 3;
578	tcd_receive.SDF.B.SSIZE = 0;
579	tcd_receive.SDF.B.SOFF = 0;
580	tcd_receive.SDF.B.DSIZE = 0;
581	tcd_receive.NBYTES = 1;
582	tcd_receive.BMF.B.D_REQ = 1;
583	tcd_receive.BMF.B.INT_MAJ = 1;
584	tcd_receive.CDF.B.CITER = n_c;
585	tcd_receive.BMF.B.BITER = n_c;
586	EDMA.TCD [e->edma_receive.channel] = tcd_receive;
587
588	/* Clear request flags */
589	sr.R = 0;
590	sr.B.TFFF = 1;
591	sr.B.RFDF = 1;
592	status->R = sr.R;
593
594	/* Enable hardware requests */
595	mpc55xx_edma_enable_hardware_requests( e->edma_receive.channel, true);
596	mpc55xx_edma_enable_hardware_requests( e->edma_transmit.channel, true);
597
598	/* Wait for transmit update */
599	sc = rtems_semaphore_obtain( e->edma_transmit.id, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
600	RTEMS_CHECK_SC_RV( sc, "transmit update");
601
602	/* Wait for receive update */
603	sc = rtems_semaphore_obtain( e->edma_receive.id, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
604	RTEMS_CHECK_SC_RV( sc, "receive update");
605	}
606
607	return n;
608	}
609
610	/**
611	* @brief Reads @a n characters from bus @a bus and stores it in @a in.
612	*
613	* Writes idle characters to receive data.
614	*
615	* @see mpc55xx_dspi_read_write().
616	*/
617	static int mpc55xx_dspi_read( rtems_libi2c_bus_t bus, unsigned char in, int n)
618	{
619	return mpc55xx_dspi_read_write( bus, in, NULL, n);
620	}
621
622	/**
623	* @brief Writes @a n characters from @a out to bus @a bus.
624	*
625	* Discards the synchronously received data.
626	*
627	* @see mpc55xx_dspi_read_write().
628	*/
629	static int mpc55xx_dspi_write( rtems_libi2c_bus_t bus, unsigned char out, int n)
630	{
631	return mpc55xx_dspi_read_write( bus, NULL, out, n);
632	}
633
634	static int mpc55xx_dspi_ioctl( rtems_libi2c_bus_t bus, int cmd, void arg)
635	{
636	int rv = -1;
637	switch (cmd) {
638	case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
639	rv = mpc55xx_dspi_set_transfer_mode( bus, (const rtems_libi2c_tfr_mode_t *) arg);
640	break;
641	case RTEMS_LIBI2C_IOCTL_READ_WRITE:
642	rv = mpc55xx_dspi_read_write(
643	bus,
644	((rtems_libi2c_read_write_t *) arg)->rd_buf,
645	((rtems_libi2c_read_write_t *) arg)->wr_buf,
646	((rtems_libi2c_read_write_t *) arg)->byte_cnt
647	);
648	break;
649	default:
650	rv = -RTEMS_NOT_DEFINED;
651	break;
652	}
653	return rv;
654	}
655
656	static const rtems_libi2c_bus_ops_t mpc55xx_dspi_ops = {
657	.init = mpc55xx_dspi_init,
658	.send_start = mpc55xx_dspi_send_start,
659	.send_stop = mpc55xx_dspi_send_stop,
660	.send_addr = mpc55xx_dspi_send_addr,
661	.read_bytes = mpc55xx_dspi_read,
662	.write_bytes = mpc55xx_dspi_write,
663	.ioctl = mpc55xx_dspi_ioctl
664	};
665
666	mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [MPC55XX_DSPI_NUMBER] = {
667	{
668	/* DSPI A */
669	.bus = {
670	.ops = &mpc55xx_dspi_ops,
671	.size = sizeof( mpc55xx_dspi_bus_entry)
672	},
673	.table_index = 0,
674	.bus_number = 0,
675	.regs = &DSPI_A,
676	.master = true,
677	.push_data = MPC55XX_ZERO_FLAGS,
678	.edma_transmit = {
679	.channel = 32,
680	.done = mpc55xx_dspi_edma_done,
681	.id = RTEMS_ID_NONE
682	},
683	.edma_push = {
684	.channel = 43,
685	.done = mpc55xx_dspi_edma_done,
686	.id = RTEMS_ID_NONE
687	},
688	.edma_receive = {
689	.channel = 33,
690	.done = mpc55xx_dspi_edma_done,
691	.id = RTEMS_ID_NONE
692	},
693	.idle_char = 0xffffffff,
694	.baud = 0
695	}, {
696	/* DSPI B */
697	.bus = {
698	.ops = &mpc55xx_dspi_ops,
699	.size = sizeof( mpc55xx_dspi_bus_entry)
700	},
701	.table_index = 1,
702	.bus_number = 0,
703	.regs = &DSPI_B,
704	.master = true,
705	.push_data = MPC55XX_ZERO_FLAGS,
706	.edma_transmit = {
707	.channel = 12,
708	.done = mpc55xx_dspi_edma_done,
709	.id = RTEMS_ID_NONE
710	},
711	.edma_push = {
712	.channel = 10,
713	.done = mpc55xx_dspi_edma_done,
714	.id = RTEMS_ID_NONE
715	},
716	.edma_receive = {
717	.channel = 13,
718	.done = mpc55xx_dspi_edma_done,
719	.id = RTEMS_ID_NONE
720	},
721	.idle_char = 0xffffffff,
722	.baud = 0
723	}, {
724	/* DSPI C */
725	.bus = {
726	.ops = &mpc55xx_dspi_ops,
727	.size = sizeof( mpc55xx_dspi_bus_entry)
728	},
729	.table_index = 2,
730	.bus_number = 0,
731	.regs = &DSPI_C,
732	.master = true,
733	.push_data = MPC55XX_ZERO_FLAGS,
734	.edma_transmit = {
735	.channel = 14,
736	.done = mpc55xx_dspi_edma_done,
737	.id = RTEMS_ID_NONE
738	},
739	.edma_push = {
740	.channel = 11,
741	.done = mpc55xx_dspi_edma_done,
742	.id = RTEMS_ID_NONE
743	},
744	.edma_receive = {
745	.channel = 15,
746	.done = mpc55xx_dspi_edma_done,
747	.id = RTEMS_ID_NONE
748	},
749	.idle_char = 0xffffffff,
750	.baud = 0
751	#ifdef DSPI_D
752	}, {
753	/* DSPI D */
754	.bus = {
755	.ops = &mpc55xx_dspi_ops,
756	.size = sizeof( mpc55xx_dspi_bus_entry)
757	},
758	.table_index = 3,
759	.bus_number = 0,
760	.regs = &DSPI_D,
761	.master = true,
762	.push_data = MPC55XX_ZERO_FLAGS,
763	.edma_transmit = {
764	.channel = 16,
765	.done = mpc55xx_dspi_edma_done,
766	.id = RTEMS_ID_NONE
767	},
768	.edma_push = {
769	.channel = 18,
770	.done = mpc55xx_dspi_edma_done,
771	.id = RTEMS_ID_NONE
772	},
773	.edma_receive = {
774	.channel = 17,
775	.done = mpc55xx_dspi_edma_done,
776	.id = RTEMS_ID_NONE
777	},
778	.idle_char = 0xffffffff,
779	.baud = 0
780	#endif
781	}
782	};

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