source: rtems/c/src/lib/libcpu/mips/tx49/include/tx4938.h @ 63defa58

Last change on this file since 63defa58 was 63defa58, checked in by Jennifer Averett <jennifer.averett@…>, on 04/04/12 at 13:39:46

PR 1993 - Convert MIPS to PIC IRQ model
  • Property mode set to 100644
File size: 6.7 KB
Line 
1/**
2 *  @file
3 * 
4 *  MIPS Tx4938 specific information
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifndef __TX4938_h
19#define __TX4938_h
20
21#define TX4938_REG_BASE 0xFF1F0000
22
23/* PCI1 Registers */
24#define TX4938_PCI1_PCIID       0x7000
25#define TX4938_PCI1_PCISTATUS   0x7004
26#define TX4938_PCI1_PCICFG1     0x700c
27#define TX4938_PCI1_P2GM1PLBASE 0x7018
28#define TX4938_PCI1_P2GCFG      0x7090
29#define TX4938_PCI1_PBAREQPORT  0x7100
30#define TX4938_PCI1_PBACFG      0x7104
31#define TX4938_PCI1_G2PM0GBASE  0x7120
32#define TX4938_PCI1_G2PIOGBASE  0x7138
33#define TX4938_PCI1_G2PM0MASK   0x7140
34#define TX4938_PCI1_G2PIOMASK   0x714c
35#define TX4938_PCI1_G2PM0PBASE  0x7150
36#define TX4938_PCI1_G2PIOPBASE  0x7168
37#define TX4938_PCI1_PCICCFG     0x7170
38#define TX4938_PCI1_PCICSTATUS  0x7174
39#define TX4938_PCI1_P2GM1GBASE  0x7188
40#define TX4938_PCI1_G2PCFGADRS  0x71a0
41#define TX4938_PCI1_G2PCFGDATA  0x71a4
42
43/*
44 *  Configuration Registers
45 */
46#define TX4938_CFG_CCFG 0xE000          /* Chip Configuration Register */
47#define TX4938_CFG_REVID 0xE008         /* Chip Revision ID Register */
48#define TX4938_CFG_PCFG 0xE010          /* Pin Configuration Register */
49#define TX4938_CFG_TOEA 0xE018          /* TimeOut Error Access Address Register */
50#define TX4938_CFG_CLKCTR 0xE020                /* Clock Control Register */
51#define TX4938_CFG_GARBC 0xE030         /* GBUS Arbiter Control Register */
52#define TX4938_CFG_RAMP 0xE048          /* Register Address Mapping Register */
53
54/* Pin Configuration register bits */
55#define SELCHI  0x00100000
56#define SELTMR0 0x00000200
57
58
59/*
60 *  Timer Registers
61 */
62
63#define TX4938_TIMER0_BASE 0xF000
64#define TX4938_TIMER1_BASE 0xF100
65#define TX4938_TIMER2_BASE 0xF200
66
67#define TX4938_TIMER_TCR  0x00                  /* Timer Control Register */
68#define TX4938_TIMER_TISR 0x04                  /* Timer Interrupt Status Register */
69#define TX4938_TIMER_CPRA 0x08                  /* Compare Register A */
70#define TX4938_TIMER_CPRB 0x0C                  /* Compare Register B */
71#define TX4938_TIMER_ITMR 0x10                  /* Interval Timer Mode Register */
72#define TX4938_TIMER_CCDR 0x20                  /* Divide Cycle Register */
73#define TX4938_TIMER_PGMR 0x30                  /* Pulse Generator Mode Register */
74#define TX4938_TIMER_WTMR 0x40                  /* Reserved Register */
75#define TX4938_TIMER_TRR  0xF0                  /* Timer Read Register */
76
77/* ITMR register bits */
78#define TIMER_CLEAR_ENABLE_MASK         0x1
79#define TIMER_INT_ENABLE_MASK   0x8000
80
81/* PGMR register bits */
82#define FFI                     0x1
83#define TPIAE           0x4000
84#define TPIBE           0x8000
85
86/* TISR register bits */
87#define TIIS    0x1
88#define TPIAS   0x2
89#define TPIBS   0x4
90#define TWIS    0x8
91
92
93/*
94 *      Interrupt Controller Registers
95 */
96#define TX4938_IRQCTL_DEN 0xF600                /* Interrupt Detection Enable Register */
97#define TX4938_IRQCTL_DM0 0xF604                /* Interrupt Detection Mode Register 0 */
98#define TX4938_IRQCTL_DM1 0xF608                /* Interrupt Detection Mode Register 1 */
99#define TX4938_IRQCTL_LVL0 0xF610               /* Interrupt Level Register 0 */
100#define TX4938_IRQCTL_LVL1 0xF614               /* Interrupt Level Register 1 */
101#define TX4938_IRQCTL_LVL2 0xF618               /* Interrupt Level Register 2 */
102#define TX4938_IRQCTL_LVL3 0xF61C               /* Interrupt Level Register 3 */
103#define TX4938_IRQCTL_LVL4 0xF620               /* Interrupt Level Register 4 */
104#define TX4938_IRQCTL_LVL5 0xF624               /* Interrupt Level Register 5 */
105#define TX4938_IRQCTL_LVL6 0xF628               /* Interrupt Level Register 6 */
106#define TX4938_IRQCTL_LVL7 0xF62C               /* Interrupt Level Register 7 */
107#define TX4938_IRQCTL_MSK 0xF640                /* Interrupt Mask Register */
108#define TX4938_IRQCTL_EDC 0xF660                /* Interrupt Edge Detection Clear Register */
109#define TX4938_IRQCTL_PND 0xF680                /* Interrupt Pending Register */
110#define TX4938_IRQCTL_CS 0xF6A0                 /* Interrupt Current Status Register */
111#define TX4938_IRQCTL_FLAG0 0xF510              /* Interrupt Request Flag Register 0 */
112#define TX4938_IRQCTL_FLAG1 0xF514              /* Interrupt Request Flag Register 1 */
113#define TX4938_IRQCTL_POL 0xF518                /* Interrupt Request Polarity Control Register */
114#define TX4938_IRQCTL_RCNT 0xF51C               /* Interrupt Request Control Register */
115#define TX4938_IRQCTL_MASKINT 0xF520    /* Interrupt Request Internal Interrupt Mask Register */
116#define TX4938_IRQCTL_MASKEXT 0xF524    /* Interrupt Request External Interrupt Mask Register */
117
118#define TX4938_REG_READ( _base, _register ) \
119  *((volatile uint32_t *)((_base) + (_register)))
120
121#define TX4938_REG_WRITE( _base, _register, _value ) \
122  *((volatile uint32_t *)((_base) + (_register))) = (_value)
123
124/************************************************************************
125 *      TX49 Register field encodings
126*************************************************************************/
127/******** reg: CCFG ********/
128/* field: PCIDIVMODE */
129#define TX4938_CCFG_SYSSP_SHF  6
130#define TX4938_CCFG_SYSSP_MSK  (MSK(2) << TX4938_CCFG_SYSSP_SHF)
131
132/* field: PCI1DMD */
133#define TX4938_CCFG_PCI1DMD_SHF  8
134#define TX4938_CCFG_PCI1DMD_MSK  (MSK(1) << TX4938_CCFG_PCI1DMD_SHF)
135
136/* field: PCIDIVMODE */
137#define TX4938_CCFG_PCIDIVMODE_SHF  10
138#define TX4938_CCFG_PCIDIVMODE_MSK  (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF)
139
140/* field: PCI1-66 */
141#define TX4938_CCFG_PCI166_SHF  21
142#define TX4938_CCFG_PCI166_MSK  ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF)
143
144/* field: PCIMODE */
145#define TX4938_CCFG_PCIMODE_SHF  22
146#define TX4938_CCFG_PCIMODE_MSK  ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF)
147
148/* field: BRDTY */
149#define TX4938_CCFG_BRDTY_SHF  36
150#define TX4938_CCFG_RRDTY_MSK  ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF)
151
152/* field: BRDRV */
153#define TX4938_CCFG_BRDRV_SHF  32
154#define TX4938_CCFG_BRDRV_MSK  ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF)
155
156/******** reg: CLKCTR ********/
157/* field: PCIC1RST */
158#define TX4938_CLKCTR_PCIC1RST_SHF  11
159#define TX4938_CLKCTR_PCIC1RST_MSK  (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF)
160
161/******** reg: PCISTATUS ********/
162/* field: MEMSP */
163#define TX4938_PCI_PCISTATUS_MEMSP_SHF 1
164#define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF)
165
166/* field: BM */
167#define TX4938_PCI_PCISTATUS_BM_SHF    2
168#define TX4938_PCI_PCISTATUS_BM_MSK    (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF)
169
170/******** reg: PBACFG ********/
171/* field: RPBA */
172#define TX4938_PCI_PBACFG_RPBA_SHF     2
173#define TX4938_PCI_PBACFG_RPBA_MSK    (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF)
174
175/* field: PBAEN */
176#define TX4938_PCI_PBACFG_PBAEN_SHF    1
177#define TX4938_PCI_PBACFG_PBAEN_MSK   (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF)
178
179/******** reg: PCICFG ********/
180/* field: G2PM0EN */
181#define TX4938_PCI_PCICFG_G2PM0EN_SHF  6
182#define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF)
183
184/* field: G2PIOEN */
185#define TX4938_PCI_PCICFG_G2PIOEN_SHF  5
186#define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF)
187
188/* field: TCAR */
189#define TX4938_PCI_PCICFG_TCAR_SHF  4
190#define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF)
191
192
193#endif
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