source: rtems/c/src/lib/libcpu/mips/tx49/include/tx4938.h @ 359e537

4.104.115
Last change on this file since 359e537 was 359e537, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/30/09 at 05:09:41

Whitespace removal.
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1/*
2 *  MIPS Tx4938 specific information
3 *
4 *  tx4938.h,v 1.0 2004/06/23 19:54:22
5 */
6
7#ifndef __TX4938_h
8#define __TX4938_h
9
10#define TX4938_REG_BASE 0xFF1F0000
11
12/* PCI1 Registers */
13#define TX4938_PCI1_PCIID       0x7000
14#define TX4938_PCI1_PCISTATUS   0x7004
15#define TX4938_PCI1_PCICFG1     0x700c
16#define TX4938_PCI1_P2GM1PLBASE 0x7018
17#define TX4938_PCI1_P2GCFG      0x7090
18#define TX4938_PCI1_PBAREQPORT  0x7100
19#define TX4938_PCI1_PBACFG      0x7104
20#define TX4938_PCI1_G2PM0GBASE  0x7120
21#define TX4938_PCI1_G2PIOGBASE  0x7138
22#define TX4938_PCI1_G2PM0MASK   0x7140
23#define TX4938_PCI1_G2PIOMASK   0x714c
24#define TX4938_PCI1_G2PM0PBASE  0x7150
25#define TX4938_PCI1_G2PIOPBASE  0x7168
26#define TX4938_PCI1_PCICCFG     0x7170
27#define TX4938_PCI1_PCICSTATUS  0x7174
28#define TX4938_PCI1_P2GM1GBASE  0x7188
29#define TX4938_PCI1_G2PCFGADRS  0x71a0
30#define TX4938_PCI1_G2PCFGDATA  0x71a4
31
32/*
33 *  Configuration Registers
34 */
35#define TX4938_CFG_CCFG 0xE000          /* Chip Configuration Register */
36#define TX4938_CFG_REVID 0xE008         /* Chip Revision ID Register */
37#define TX4938_CFG_PCFG 0xE010          /* Pin Configuration Register */
38#define TX4938_CFG_TOEA 0xE018          /* TimeOut Error Access Address Register */
39#define TX4938_CFG_CLKCTR 0xE020                /* Clock Control Register */
40#define TX4938_CFG_GARBC 0xE030         /* GBUS Arbiter Control Register */
41#define TX4938_CFG_RAMP 0xE048          /* Register Address Mapping Register */
42
43/* Pin Configuration register bits */
44#define SELCHI  0x00100000
45#define SELTMR0 0x00000200
46
47
48/*
49 *  Timer Registers
50 */
51
52#define TX4938_TIMER0_BASE 0xF000
53#define TX4938_TIMER1_BASE 0xF100
54#define TX4938_TIMER2_BASE 0xF200
55
56#define TX4938_TIMER_TCR  0x00                  /* Timer Control Register */
57#define TX4938_TIMER_TISR 0x04                  /* Timer Interrupt Status Register */
58#define TX4938_TIMER_CPRA 0x08                  /* Compare Register A */
59#define TX4938_TIMER_CPRB 0x0C                  /* Compare Register B */
60#define TX4938_TIMER_ITMR 0x10                  /* Interval Timer Mode Register */
61#define TX4938_TIMER_CCDR 0x20                  /* Divide Cycle Register */
62#define TX4938_TIMER_PGMR 0x30                  /* Pulse Generator Mode Register */
63#define TX4938_TIMER_WTMR 0x40                  /* Reserved Register */
64#define TX4938_TIMER_TRR  0xF0                  /* Timer Read Register */
65
66/* ITMR register bits */
67#define TIMER_CLEAR_ENABLE_MASK         0x1
68#define TIMER_INT_ENABLE_MASK   0x8000
69
70/* PGMR register bits */
71#define FFI                     0x1
72#define TPIAE           0x4000
73#define TPIBE           0x8000
74
75/* TISR register bits */
76#define TIIS    0x1
77#define TPIAS   0x2
78#define TPIBS   0x4
79#define TWIS    0x8
80
81
82/*
83 *      Interrupt Controller Registers
84 */
85#define TX4938_IRQCTL_DEN 0xF600                /* Interrupt Detection Enable Register */
86#define TX4938_IRQCTL_DM0 0xF604                /* Interrupt Detection Mode Register 0 */
87#define TX4938_IRQCTL_DM1 0xF608                /* Interrupt Detection Mode Register 1 */
88#define TX4938_IRQCTL_LVL0 0xF610               /* Interrupt Level Register 0 */
89#define TX4938_IRQCTL_LVL1 0xF614               /* Interrupt Level Register 1 */
90#define TX4938_IRQCTL_LVL2 0xF618               /* Interrupt Level Register 2 */
91#define TX4938_IRQCTL_LVL3 0xF61C               /* Interrupt Level Register 3 */
92#define TX4938_IRQCTL_LVL4 0xF620               /* Interrupt Level Register 4 */
93#define TX4938_IRQCTL_LVL5 0xF624               /* Interrupt Level Register 5 */
94#define TX4938_IRQCTL_LVL6 0xF628               /* Interrupt Level Register 6 */
95#define TX4938_IRQCTL_LVL7 0xF62C               /* Interrupt Level Register 7 */
96#define TX4938_IRQCTL_MSK 0xF640                /* Interrupt Mask Register */
97#define TX4938_IRQCTL_EDC 0xF660                /* Interrupt Edge Detection Clear Register */
98#define TX4938_IRQCTL_PND 0xF680                /* Interrupt Pending Register */
99#define TX4938_IRQCTL_CS 0xF6A0                 /* Interrupt Current Status Register */
100#define TX4938_IRQCTL_FLAG0 0xF510              /* Interrupt Request Flag Register 0 */
101#define TX4938_IRQCTL_FLAG1 0xF514              /* Interrupt Request Flag Register 1 */
102#define TX4938_IRQCTL_POL 0xF518                /* Interrupt Request Polarity Control Register */
103#define TX4938_IRQCTL_RCNT 0xF51C               /* Interrupt Request Control Register */
104#define TX4938_IRQCTL_MASKINT 0xF520    /* Interrupt Request Internal Interrupt Mask Register */
105#define TX4938_IRQCTL_MASKEXT 0xF524    /* Interrupt Request External Interrupt Mask Register */
106
107#define TX4938_REG_READ( _base, _register ) \
108  *((volatile uint32_t *)((_base) + (_register)))
109
110#define TX4938_REG_WRITE( _base, _register, _value ) \
111  *((volatile uint32_t *)((_base) + (_register))) = (_value)
112
113/*
114 *  Interrupt Vector Numbers
115 *
116 */
117#define TX4938_IRQ_ECC         MIPS_INTERRUPT_BASE+0
118#define TX4938_IRQ_WTE         MIPS_INTERRUPT_BASE+1
119#define TX4938_IRQ_INT0        MIPS_INTERRUPT_BASE+2
120#define TX4938_IRQ_INT1        MIPS_INTERRUPT_BASE+3
121#define TX4938_IRQ_INT2        MIPS_INTERRUPT_BASE+4
122#define TX4938_IRQ_INT3        MIPS_INTERRUPT_BASE+5
123#define TX4938_IRQ_INT4        MIPS_INTERRUPT_BASE+6
124#define TX4938_IRQ_INT5        MIPS_INTERRUPT_BASE+7
125#define TX4938_IRQ_SIO0        MIPS_INTERRUPT_BASE+8
126#define TX4938_IRQ_SIO1        MIPS_INTERRUPT_BASE+9
127#define TX4938_IRQ_DMAC00      MIPS_INTERRUPT_BASE+10
128#define TX4938_IRQ_DMAC01      MIPS_INTERRUPT_BASE+11
129#define TX4938_IRQ_DMAC02      MIPS_INTERRUPT_BASE+12
130#define TX4938_IRQ_DMAC03      MIPS_INTERRUPT_BASE+13
131#define TX4938_IRQ_IRC         MIPS_INTERRUPT_BASE+14
132#define TX4938_IRQ_PDMAC       MIPS_INTERRUPT_BASE+15
133#define TX4938_IRQ_PCIC        MIPS_INTERRUPT_BASE+16
134#define TX4938_IRQ_TMR0        MIPS_INTERRUPT_BASE+17
135#define TX4938_IRQ_TMR1        MIPS_INTERRUPT_BASE+18
136#define TX4938_IRQ_TMR2        MIPS_INTERRUPT_BASE+19
137#define TX4938_IRQ_RSV1        MIPS_INTERRUPT_BASE+20
138#define TX4938_IRQ_NDFMC       MIPS_INTERRUPT_BASE+21
139#define TX4938_IRQ_PCIERR      MIPS_INTERRUPT_BASE+22
140#define TX4938_IRQ_PCIPMC      MIPS_INTERRUPT_BASE+23
141#define TX4938_IRQ_ACLC        MIPS_INTERRUPT_BASE+24
142#define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+25
143#define TX4938_IRQ_PCIC1NT     MIPS_INTERRUPT_BASE+26
144#define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
145#define TX4938_IRQ_DMAC10      MIPS_INTERRUPT_BASE+28
146#define TX4938_IRQ_DMAC11      MIPS_INTERRUPT_BASE+29
147#define TX4938_IRQ_DMAC12      MIPS_INTERRUPT_BASE+30
148#define TX4938_IRQ_DMAC13      MIPS_INTERRUPT_BASE+31
149
150#define TX4938_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
151#define TX4938_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
152#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
153
154/************************************************************************
155 *      TX49 Register field encodings
156*************************************************************************/
157/******** reg: CCFG ********/
158/* field: PCIDIVMODE */
159#define TX4938_CCFG_SYSSP_SHF  6
160#define TX4938_CCFG_SYSSP_MSK  (MSK(2) << TX4938_CCFG_SYSSP_SHF)
161
162/* field: PCI1DMD */
163#define TX4938_CCFG_PCI1DMD_SHF  8
164#define TX4938_CCFG_PCI1DMD_MSK  (MSK(1) << TX4938_CCFG_PCI1DMD_SHF)
165
166/* field: PCIDIVMODE */
167#define TX4938_CCFG_PCIDIVMODE_SHF  10
168#define TX4938_CCFG_PCIDIVMODE_MSK  (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF)
169
170/* field: PCI1-66 */
171#define TX4938_CCFG_PCI166_SHF  21
172#define TX4938_CCFG_PCI166_MSK  ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF)
173
174/* field: PCIMODE */
175#define TX4938_CCFG_PCIMODE_SHF  22
176#define TX4938_CCFG_PCIMODE_MSK  ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF)
177
178/* field: BRDTY */
179#define TX4938_CCFG_BRDTY_SHF  36
180#define TX4938_CCFG_RRDTY_MSK  ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF)
181
182/* field: BRDRV */
183#define TX4938_CCFG_BRDRV_SHF  32
184#define TX4938_CCFG_BRDRV_MSK  ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF)
185
186/******** reg: CLKCTR ********/
187/* field: PCIC1RST */
188#define TX4938_CLKCTR_PCIC1RST_SHF  11
189#define TX4938_CLKCTR_PCIC1RST_MSK  (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF)
190
191/******** reg: PCISTATUS ********/
192/* field: MEMSP */
193#define TX4938_PCI_PCISTATUS_MEMSP_SHF 1
194#define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF)
195
196/* field: BM */
197#define TX4938_PCI_PCISTATUS_BM_SHF    2
198#define TX4938_PCI_PCISTATUS_BM_MSK    (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF)
199
200/******** reg: PBACFG ********/
201/* field: RPBA */
202#define TX4938_PCI_PBACFG_RPBA_SHF     2
203#define TX4938_PCI_PBACFG_RPBA_MSK    (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF)
204
205/* field: PBAEN */
206#define TX4938_PCI_PBACFG_PBAEN_SHF    1
207#define TX4938_PCI_PBACFG_PBAEN_MSK   (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF)
208
209/******** reg: PCICFG ********/
210/* field: G2PM0EN */
211#define TX4938_PCI_PCICFG_G2PM0EN_SHF  6
212#define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF)
213
214/* field: G2PIOEN */
215#define TX4938_PCI_PCICFG_G2PIOEN_SHF  5
216#define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF)
217
218/* field: TCAR */
219#define TX4938_PCI_PCICFG_TCAR_SHF  4
220#define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF)
221
222
223#endif
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