source: rtems/c/src/lib/libcpu/mips/tx49/include/tx4925.h @ f68401e

4.115
Last change on this file since f68401e was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.

  • Property mode set to 100644
File size: 4.0 KB
Line 
1/**
2 *  @file
3 * 
4 *  MIPS Tx4925 specific information
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 */
15
16#ifndef __TX4925_h
17#define __TX4925_h
18
19#define TX4925_REG_BASE 0xFF1F0000
20
21
22/*
23 *  Configuration Registers
24 */
25#define TX4925_CFG_CCFG 0xE000          /* Chip Configuration Register */
26#define TX4925_CFG_REVID 0xE004         /* Chip Revision ID Register */
27#define TX4925_CFG_PCFG 0xE008          /* Pin Configuration Register */
28#define TX4925_CFG_TOEA 0xE00C          /* TimeOut Error Access Address Register */
29#define TX4925_CFG_PDNCTR 0xE010        /* Power Down Control Register */
30#define TX4925_CFG_GARBP 0xE018         /* GBUS Arbiter Priority Register */
31#define TX4925_CFG_TOCNT 0xE020         /* Timeout Count Register */
32#define TX4925_CFG_DRQCTR 0xE024                /* DMA Request Control Register */
33#define TX4925_CFG_CLKCTR 0xE028                /* Clock Control Register */
34#define TX4925_CFG_GARBC 0xE02C         /* GBUS Arbiter Control Register */
35#define TX4925_CFG_RAMP 0xE030          /* Register Address Mapping Register */
36
37/* Pin Configuration register bits */
38#define SELCHI  0x00100000
39#define SELTMR0 0x00000200
40
41
42/*
43 *  Timer Registers
44 */
45
46#define TX4925_TIMER0_BASE 0xF000
47#define TX4925_TIMER1_BASE 0xF100
48#define TX4925_TIMER2_BASE 0xF200
49
50#define TX4925_TIMER_TCR  0x00                  /* Timer Control Register */
51#define TX4925_TIMER_TISR 0x04                  /* Timer Interrupt Status Register */
52#define TX4925_TIMER_CPRA 0x08                  /* Compare Register A */
53#define TX4925_TIMER_CPRB 0x0C                  /* Compare Register B */
54#define TX4925_TIMER_ITMR 0x10                  /* Interval Timer Mode Register */
55#define TX4925_TIMER_CCDR 0x20                  /* Divide Cycle Register */
56#define TX4925_TIMER_PGMR 0x30                  /* Pulse Generator Mode Register */
57#define TX4925_TIMER_WTMR 0x40                  /* Reserved Register */
58#define TX4925_TIMER_TRR  0xF0                  /* Timer Read Register */
59
60/* ITMR register bits */
61#define TIMER_CLEAR_ENABLE_MASK         0x1
62#define TIMER_INT_ENABLE_MASK   0x8000
63
64/* PGMR register bits */
65#define FFI                     0x1
66#define TPIAE           0x4000
67#define TPIBE           0x8000
68
69/* TISR register bits */
70#define TIIS    0x1
71#define TPIAS   0x2
72#define TPIBS   0x4
73#define TWIS    0x8
74
75
76/*
77 *      Interrupt Controller Registers
78 */
79#define TX4925_IRQCTL_DEN 0xF600                /* Interrupt Detection Enable Register */
80#define TX4925_IRQCTL_DM0 0xF604                /* Interrupt Detection Mode Register 0 */
81#define TX4925_IRQCTL_DM1 0xF608                /* Interrupt Detection Mode Register 1 */
82#define TX4925_IRQCTL_LVL0 0xF610               /* Interrupt Level Register 0 */
83#define TX4925_IRQCTL_LVL1 0xF614               /* Interrupt Level Register 1 */
84#define TX4925_IRQCTL_LVL2 0xF618               /* Interrupt Level Register 2 */
85#define TX4925_IRQCTL_LVL3 0xF61C               /* Interrupt Level Register 3 */
86#define TX4925_IRQCTL_LVL4 0xF620               /* Interrupt Level Register 4 */
87#define TX4925_IRQCTL_LVL5 0xF624               /* Interrupt Level Register 5 */
88#define TX4925_IRQCTL_LVL6 0xF628               /* Interrupt Level Register 6 */
89#define TX4925_IRQCTL_LVL7 0xF62C               /* Interrupt Level Register 7 */
90#define TX4925_IRQCTL_MSK 0xF640                /* Interrupt Mask Register */
91#define TX4925_IRQCTL_EDC 0xF660                /* Interrupt Edge Detection Clear Register */
92#define TX4925_IRQCTL_PND 0xF680                /* Interrupt Pending Register */
93#define TX4925_IRQCTL_CS 0xF6A0                 /* Interrupt Current Status Register */
94#define TX4925_IRQCTL_FLAG0 0xF510              /* Interrupt Request Flag Register 0 */
95#define TX4925_IRQCTL_FLAG1 0xF514              /* Interrupt Request Flag Register 1 */
96#define TX4925_IRQCTL_POL 0xF518                /* Interrupt Request Polarity Control Register */
97#define TX4925_IRQCTL_RCNT 0xF51C               /* Interrupt Request Control Register */
98#define TX4925_IRQCTL_MASKINT 0xF520    /* Interrupt Request Internal Interrupt Mask Register */
99#define TX4925_IRQCTL_MASKEXT 0xF524    /* Interrupt Request External Interrupt Mask Register */
100
101#define TX4925_REG_READ( _base, _register ) \
102  *((volatile uint32_t *)((_base) + (_register)))
103
104#define TX4925_REG_WRITE( _base, _register, _value ) \
105  *((volatile uint32_t *)((_base) + (_register))) = (_value)
106
107#endif
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