[0c0181d] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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[3a3e5dae] | 4 | * MIPS Tx4925 specific information |
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[0c0181d] | 5 | */ |
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| 6 | |
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| 7 | /* |
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| 8 | * COPYRIGHT (c) 1989-2012. |
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| 9 | * On-Line Applications Research Corporation (OAR). |
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[3a3e5dae] | 10 | * |
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[0c0181d] | 11 | * The license and distribution terms for this file may be |
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| 12 | * found in the file LICENSE in this distribution or at |
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[c499856] | 13 | * http://www.rtems.org/license/LICENSE. |
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[3a3e5dae] | 14 | */ |
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| 15 | |
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| 16 | #ifndef __TX4925_h |
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| 17 | #define __TX4925_h |
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| 18 | |
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| 19 | #define TX4925_REG_BASE 0xFF1F0000 |
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| 20 | |
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| 21 | |
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| 22 | /* |
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| 23 | * Configuration Registers |
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| 24 | */ |
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| 25 | #define TX4925_CFG_CCFG 0xE000 /* Chip Configuration Register */ |
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| 26 | #define TX4925_CFG_REVID 0xE004 /* Chip Revision ID Register */ |
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| 27 | #define TX4925_CFG_PCFG 0xE008 /* Pin Configuration Register */ |
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| 28 | #define TX4925_CFG_TOEA 0xE00C /* TimeOut Error Access Address Register */ |
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| 29 | #define TX4925_CFG_PDNCTR 0xE010 /* Power Down Control Register */ |
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| 30 | #define TX4925_CFG_GARBP 0xE018 /* GBUS Arbiter Priority Register */ |
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| 31 | #define TX4925_CFG_TOCNT 0xE020 /* Timeout Count Register */ |
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| 32 | #define TX4925_CFG_DRQCTR 0xE024 /* DMA Request Control Register */ |
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| 33 | #define TX4925_CFG_CLKCTR 0xE028 /* Clock Control Register */ |
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| 34 | #define TX4925_CFG_GARBC 0xE02C /* GBUS Arbiter Control Register */ |
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| 35 | #define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */ |
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| 36 | |
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| 37 | /* Pin Configuration register bits */ |
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[359e537] | 38 | #define SELCHI 0x00100000 |
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[3a3e5dae] | 39 | #define SELTMR0 0x00000200 |
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| 40 | |
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| 41 | |
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| 42 | /* |
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| 43 | * Timer Registers |
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| 44 | */ |
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| 45 | |
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| 46 | #define TX4925_TIMER0_BASE 0xF000 |
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| 47 | #define TX4925_TIMER1_BASE 0xF100 |
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| 48 | #define TX4925_TIMER2_BASE 0xF200 |
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| 49 | |
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| 50 | #define TX4925_TIMER_TCR 0x00 /* Timer Control Register */ |
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| 51 | #define TX4925_TIMER_TISR 0x04 /* Timer Interrupt Status Register */ |
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| 52 | #define TX4925_TIMER_CPRA 0x08 /* Compare Register A */ |
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| 53 | #define TX4925_TIMER_CPRB 0x0C /* Compare Register B */ |
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| 54 | #define TX4925_TIMER_ITMR 0x10 /* Interval Timer Mode Register */ |
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| 55 | #define TX4925_TIMER_CCDR 0x20 /* Divide Cycle Register */ |
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| 56 | #define TX4925_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */ |
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| 57 | #define TX4925_TIMER_WTMR 0x40 /* Reserved Register */ |
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| 58 | #define TX4925_TIMER_TRR 0xF0 /* Timer Read Register */ |
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| 59 | |
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| 60 | /* ITMR register bits */ |
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| 61 | #define TIMER_CLEAR_ENABLE_MASK 0x1 |
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| 62 | #define TIMER_INT_ENABLE_MASK 0x8000 |
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| 63 | |
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| 64 | /* PGMR register bits */ |
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| 65 | #define FFI 0x1 |
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| 66 | #define TPIAE 0x4000 |
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| 67 | #define TPIBE 0x8000 |
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| 68 | |
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| 69 | /* TISR register bits */ |
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| 70 | #define TIIS 0x1 |
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| 71 | #define TPIAS 0x2 |
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| 72 | #define TPIBS 0x4 |
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| 73 | #define TWIS 0x8 |
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| 74 | |
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| 75 | |
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[359e537] | 76 | /* |
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[3a3e5dae] | 77 | * Interrupt Controller Registers |
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| 78 | */ |
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| 79 | #define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ |
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| 80 | #define TX4925_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */ |
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| 81 | #define TX4925_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */ |
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| 82 | #define TX4925_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */ |
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| 83 | #define TX4925_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */ |
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| 84 | #define TX4925_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */ |
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| 85 | #define TX4925_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */ |
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| 86 | #define TX4925_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */ |
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| 87 | #define TX4925_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */ |
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| 88 | #define TX4925_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */ |
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| 89 | #define TX4925_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */ |
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| 90 | #define TX4925_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */ |
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| 91 | #define TX4925_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */ |
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| 92 | #define TX4925_IRQCTL_PND 0xF680 /* Interrupt Pending Register */ |
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| 93 | #define TX4925_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */ |
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| 94 | #define TX4925_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */ |
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| 95 | #define TX4925_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */ |
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| 96 | #define TX4925_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */ |
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| 97 | #define TX4925_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */ |
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| 98 | #define TX4925_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */ |
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| 99 | #define TX4925_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */ |
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| 100 | |
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| 101 | #define TX4925_REG_READ( _base, _register ) \ |
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| 102 | *((volatile uint32_t *)((_base) + (_register))) |
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| 103 | |
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| 104 | #define TX4925_REG_WRITE( _base, _register, _value ) \ |
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| 105 | *((volatile uint32_t *)((_base) + (_register))) = (_value) |
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| 106 | |
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| 107 | #endif |
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