source: rtems/c/src/lib/libcpu/mips/tx39/include/tx3904.h @ ae5901be

4.104.114.84.95
Last change on this file since ae5901be was ae5901be, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 31, 2004 at 11:11:30 AM

2004-03-31 Ralf Corsepius <ralf_corsepius@…>

  • mongoosev/duart/mg5uart.c, mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, shared/interrupts/vectorexceptions.c, tx39/include/tx3904.h: Cosmetics.
  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 *  MIPS Tx3904 specific information
3 *
4 *  NOTE: This is far from complete.  --joel (13 Dec 2000)
5 *
6 *  $Id$
7 */
8
9#ifndef __TX3904_h
10#define __TX3904_h
11
12/*
13 *  Timer Base Addresses and Offsets
14 */
15
16#define TX3904_TIMER0_BASE 0xFFFFF000
17#define TX3904_TIMER1_BASE 0xFFFFF100
18#define TX3904_TIMER2_BASE 0xFFFFF200
19
20#define TX3904_TIMER_TCR  0x00
21#define TX3904_TIMER_TISR 0x04
22#define TX3904_TIMER_CPRA 0x08
23#define TX3904_TIMER_CPRB 0x0C
24#define TX3904_TIMER_ITMR 0x10
25#define TX3904_TIMER_CCDR 0x20
26#define TX3904_TIMER_PGMR 0x30
27#define TX3904_TIMER_WTMR 0x40
28#define TX3904_TIMER_TRR  0xF0
29
30#define TX3904_TIMER_READ( _base, _register ) \
31  *((volatile uint32_t*)((_base) + (_register)))
32
33#define TX3904_TIMER_WRITE( _base, _register, _value ) \
34  *((volatile uint32_t*)((_base) + (_register))) = (_value)
35
36/*
37 *  Interrupt Vector Numbers
38 *
39 *  NOTE: Numbers 0-15 directly map to levels on the IRC.
40 *        Number 16 is "1xxxx" per p. 164 of the TX3904 manual.
41 */
42
43#define TX3904_IRQ_INT1        MIPS_INTERRUPT_BASE+0
44#define TX3904_IRQ_INT2        MIPS_INTERRUPT_BASE+1
45#define TX3904_IRQ_INT3        MIPS_INTERRUPT_BASE+2
46#define TX3904_IRQ_INT4        MIPS_INTERRUPT_BASE+3
47#define TX3904_IRQ_INT5        MIPS_INTERRUPT_BASE+4
48#define TX3904_IRQ_INT6        MIPS_INTERRUPT_BASE+5
49#define TX3904_IRQ_INT7        MIPS_INTERRUPT_BASE+6
50#define TX3904_IRQ_DMAC3       MIPS_INTERRUPT_BASE+7
51#define TX3904_IRQ_DMAC2       MIPS_INTERRUPT_BASE+8
52#define TX3904_IRQ_DMAC1       MIPS_INTERRUPT_BASE+9
53#define TX3904_IRQ_DMAC0       MIPS_INTERRUPT_BASE+10
54#define TX3904_IRQ_SIO0        MIPS_INTERRUPT_BASE+11
55#define TX3904_IRQ_SIO1        MIPS_INTERRUPT_BASE+12
56#define TX3904_IRQ_TMR0        MIPS_INTERRUPT_BASE+13
57#define TX3904_IRQ_TMR1        MIPS_INTERRUPT_BASE+14
58#define TX3904_IRQ_TMR2        MIPS_INTERRUPT_BASE+15
59#define TX3904_IRQ_INT0        MIPS_INTERRUPT_BASE+16
60#define TX3904_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+17
61#define TX3904_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+18
62#define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
63
64#endif
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