1 | /* |
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2 | * MIPS Tx3904 specific information |
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3 | * |
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4 | * NOTE: This is far from complete. --joel (13 Dec 2000) |
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5 | * |
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6 | * $Id$ |
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7 | */ |
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8 | |
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9 | #ifndef __TX3904_h |
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10 | #define __TX3904_h |
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11 | |
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12 | /* |
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13 | * Timer Base Addresses and Offsets |
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14 | */ |
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15 | |
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16 | #define TX3904_TIMER0_BASE 0xFFFFF000 |
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17 | #define TX3904_TIMER1_BASE 0xFFFFF100 |
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18 | #define TX3904_TIMER2_BASE 0xFFFFF200 |
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19 | |
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20 | #define TX3904_TIMER_TCR 0x00 |
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21 | #define TX3904_TIMER_TISR 0x04 |
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22 | #define TX3904_TIMER_CPRA 0x08 |
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23 | #define TX3904_TIMER_CPRB 0x0C |
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24 | #define TX3904_TIMER_ITMR 0x10 |
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25 | #define TX3904_TIMER_CCDR 0x20 |
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26 | #define TX3904_TIMER_PGMR 0x30 |
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27 | #define TX3904_TIMER_WTMR 0x40 |
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28 | #define TX3904_TIMER_TRR 0xF0 |
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29 | |
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30 | #define TX3904_TIMER_READ( _base, _register ) \ |
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31 | *((volatile uint32_t *)((_base) + (_register))) |
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32 | |
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33 | #define TX3904_TIMER_WRITE( _base, _register, _value ) \ |
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34 | *((volatile uint32_t *)((_base) + (_register))) = (_value) |
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35 | |
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36 | /* |
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37 | * Interrupt Vector Numbers |
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38 | * |
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39 | * NOTE: Numbers 0-15 directly map to levels on the IRC. |
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40 | * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. |
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41 | */ |
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42 | |
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43 | #define TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0 |
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44 | #define TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1 |
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45 | #define TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2 |
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46 | #define TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3 |
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47 | #define TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4 |
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48 | #define TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5 |
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49 | #define TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6 |
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50 | #define TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7 |
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51 | #define TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8 |
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52 | #define TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9 |
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53 | #define TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10 |
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54 | #define TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11 |
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55 | #define TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12 |
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56 | #define TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13 |
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57 | #define TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14 |
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58 | #define TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15 |
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59 | #define TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16 |
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60 | #define TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17 |
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61 | #define TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18 |
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62 | #define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19 |
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63 | |
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64 | #endif |
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