1 | /* |
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2 | * This file contains the raw entry points for the exceptions. |
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3 | * |
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4 | * COPYRIGHT (c) 1989-2000. |
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5 | * On-Line Applications Research Corporation (OAR). |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.OARcorp.com/rtems/license.html. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | /* @(#)cpu_asm.S 08/20/96 1.15 */ |
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14 | |
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15 | #include <asm.h> |
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16 | #include "iregdef.h" |
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17 | #include "idtcpu.h" |
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18 | |
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19 | /* |
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20 | * MIPS ISA Level 1 entries |
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21 | */ |
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22 | |
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23 | #if __mips == 1 |
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24 | |
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25 | FRAME(exc_norm_code,sp,0,ra) |
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26 | la k0, _ISR_Handler /* generic external int hndlr */ |
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27 | j k0 |
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28 | nop |
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29 | ENDFRAME(exc_norm_code) |
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30 | |
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31 | /* XXX this is dependent on IDT/SIM and needs to be addressed */ |
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32 | FRAME(exc_utlb_code,sp,0,ra) |
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33 | la k0, (R_VEC+((48)*8)) |
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34 | j k0 |
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35 | nop |
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36 | ENDFRAME(exc_tlb_code) |
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37 | |
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38 | /* |
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39 | * MIPS ISA Level 3 |
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40 | * XXX Again, reliance on SIM. Not good. |
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41 | */ |
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42 | #elif __mips == 3 |
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43 | |
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44 | FRAME(exc_tlb_code,sp,0,ra) |
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45 | la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ |
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46 | j k0 |
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47 | nop |
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48 | ENDFRAME(exc_tlb_code) |
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49 | |
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50 | FRAME(exc_xtlb_code,sp,0,ra) |
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51 | la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ |
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52 | j k0 |
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53 | nop |
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54 | |
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55 | ENDFRAME(exc_xtlb_code) |
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56 | |
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57 | FRAME(exc_cache_code,sp,0,ra) |
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58 | la k0, (R_VEC+((112)*8)) /* R4000 Sim location */ |
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59 | j k0 |
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60 | nop |
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61 | ENDFRAME(exc_cache_code) |
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62 | |
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63 | FRAME(exc_norm_code,sp,0,ra) |
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64 | la k0, _ISR_Handler /* generic external int hndlr */ |
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65 | j k0 |
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66 | nop |
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67 | ENDFRAME(exc_norm_code) |
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68 | |
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69 | #else |
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70 | |
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71 | #error "isr_entries.S: ISA support problem" |
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72 | |
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73 | #endif |
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74 | |
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