source: rtems/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S @ acdb6558

4.104.114.84.95
Last change on this file since acdb6558 was b4d0d18e, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 13, 2000 at 5:52:53 PM

2000-12-13 Joel Sherrill <joel@…>

  • shared/.cvsignore, shared/Makefile.am, shared/cache/.cvsignore, shared/cache/Makefile.am, shared/cache/cache.c, shared/cache/cache_.h, shared/interrupts/.cvsignore, shared/interrupts/Makefile.am, shared/interrupts/installisrentries.c, shared/interrupts/isr_entries.S, shared/interrupts/maxvectors.c, tx39/.cvsignore, tx39/Makefile.am, tx39/include/.cvsignore, tx39/include/Makefile.am, tx39/include/tx3904.h: New file. Moved some pieces of interrupt processing from score/cpu to libcpu/mips since many interrupt servicing characteristics are CPU model dependent. This patch addresses the number of interrupt sources and where the ISR prologues are located. The only way to currently install the ISR prologues requires that the prologues be installed into RAM.
  • Property mode set to 100644
File size: 1.4 KB
Line 
1/*
2 *  This file contains the raw entry points for the exceptions.
3 *
4 *  COPYRIGHT (c) 1989-2000.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13/* @(#)cpu_asm.S       08/20/96     1.15 */
14
15#include <asm.h>
16#include "iregdef.h"
17#include "idtcpu.h"
18
19/*
20 *  MIPS ISA Level 1 entries
21 */
22
23#if __mips == 1
24
25FRAME(exc_norm_code,sp,0,ra)
26        la      k0, _ISR_Handler /* generic external int hndlr */
27        j       k0
28        nop
29ENDFRAME(exc_norm_code)
30
31/* XXX this is dependent on IDT/SIM and needs to be addressed */
32FRAME(exc_utlb_code,sp,0,ra)
33        la      k0, (R_VEC+((48)*8))
34        j       k0
35        nop
36ENDFRAME(exc_tlb_code)
37
38/*
39 * MIPS ISA Level 3
40 * XXX Again, reliance on SIM. Not good.
41 */
42#elif __mips == 3
43
44FRAME(exc_tlb_code,sp,0,ra)
45        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
46        j       k0
47        nop
48ENDFRAME(exc_tlb_code)
49
50FRAME(exc_xtlb_code,sp,0,ra)
51        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
52        j       k0
53        nop
54
55ENDFRAME(exc_xtlb_code)
56
57FRAME(exc_cache_code,sp,0,ra)
58        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
59        j       k0
60        nop
61ENDFRAME(exc_cache_code)
62
63FRAME(exc_norm_code,sp,0,ra)
64        la      k0, _ISR_Handler /* generic external int hndlr */
65        j       k0
66        nop
67ENDFRAME(exc_norm_code)
68
69#else
70
71#error "isr_entries.S: ISA support problem"
72
73#endif
74
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