source: rtems/c/src/lib/libcpu/mips/shared/cache/cache_.h @ acdb6558

4.104.114.84.95
Last change on this file since acdb6558 was b4d0d18e, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 13, 2000 at 5:52:53 PM

2000-12-13 Joel Sherrill <joel@…>

  • shared/.cvsignore, shared/Makefile.am, shared/cache/.cvsignore, shared/cache/Makefile.am, shared/cache/cache.c, shared/cache/cache_.h, shared/interrupts/.cvsignore, shared/interrupts/Makefile.am, shared/interrupts/installisrentries.c, shared/interrupts/isr_entries.S, shared/interrupts/maxvectors.c, tx39/.cvsignore, tx39/Makefile.am, tx39/include/.cvsignore, tx39/include/Makefile.am, tx39/include/tx3904.h: New file. Moved some pieces of interrupt processing from score/cpu to libcpu/mips since many interrupt servicing characteristics are CPU model dependent. This patch addresses the number of interrupt sources and where the ISR prologues are located. The only way to currently install the ISR prologues requires that the prologues be installed into RAM.
  • Property mode set to 100644
File size: 157 bytes
Line 
1/*
2 *  MIPS Cache Manager Support
3 */
4
5#ifndef __MIPS_CACHE_h
6#define __MIPS_CACHE_h
7
8#include <libcpu/cache.h>
9
10/* TBD */
11
12#endif
13/* end of include file */
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