1 | /* |
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2 | * ISR Vectoring support for the Synova Mongoose-V. |
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3 | * |
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4 | * COPYRIGHT (c) 1989-2001. |
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5 | * On-Line Applications Research Corporation (OAR). |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | #include <rtems.h> |
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15 | #include <stdlib.h> |
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16 | #include <libcpu/mongoose-v.h> |
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17 | |
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18 | #include "iregdef.h" |
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19 | #include "idtcpu.h" |
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20 | |
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21 | |
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22 | #include <rtems/bspIo.h> /* for printk */ |
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23 | |
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24 | |
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25 | |
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26 | int mips_default_isr( int vector ) |
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27 | { |
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28 | unsigned int sr, sr2; |
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29 | unsigned int cause; |
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30 | |
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31 | mips_get_sr( sr ); |
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32 | mips_get_cause( cause ); |
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33 | |
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34 | sr2 = sr & ~0xffff; |
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35 | mips_set_sr(sr2); |
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36 | |
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37 | printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr ); |
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38 | rtems_fatal_error_occurred(1); |
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39 | return 0; |
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40 | } |
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41 | |
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42 | /* userspace routine to assert either software interrupt */ |
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43 | |
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44 | int assertSoftwareInterrupt( uint32_t n ) |
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45 | { |
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46 | if( n<2 ) |
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47 | { |
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48 | uint32_t c; |
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49 | |
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50 | mips_get_cause(c); |
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51 | c = ((n+1) << CAUSE_IPSHIFT); |
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52 | mips_set_cause(c); |
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53 | |
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54 | return n; |
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55 | } |
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56 | else return -1; |
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57 | } |
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58 | |
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59 | |
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60 | |
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61 | |
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62 | |
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63 | |
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64 | #define CALL_ISR(_vector,_frame) \ |
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65 | do { \ |
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66 | if( _ISR_Vector_table[_vector] ) \ |
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67 | (_ISR_Vector_table[_vector])(_vector,_frame); \ |
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68 | else \ |
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69 | mips_default_isr(_vector); \ |
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70 | } while (0) |
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71 | |
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72 | |
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73 | // |
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74 | // Instrumentation tweaks for isr timing measurement, turning them off |
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75 | // via this #if will remove the code entirely from the RTEMS kernel. |
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76 | // |
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77 | |
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78 | #if 0 |
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79 | #define SET_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 1; |
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80 | #define CLR_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 0; |
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81 | #else |
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82 | #define SET_ISR_FLAG( offset ) |
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83 | #define CLR_ISR_FLAG( offset ) |
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84 | #endif |
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85 | |
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86 | |
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87 | |
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88 | |
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89 | |
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90 | |
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91 | static volatile uint32_t _ivcause, _ivsr; |
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92 | |
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93 | |
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94 | static uint32_t READ_CAUSE(void) |
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95 | { |
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96 | mips_get_cause( _ivcause ); |
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97 | _ivcause &= SR_IMASK; // mask off everything other than the interrupt bits |
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98 | |
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99 | return ((_ivcause & (_ivsr & SR_IMASK)) >> CAUSE_IPSHIFT); |
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100 | } |
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101 | |
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102 | |
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103 | |
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104 | // |
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105 | // This rather strangely coded routine enforces an interrupt priority |
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106 | // scheme. As it runs thru finding whichever interrupt caused it to get |
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107 | // here, it test for other interrupts arriving in the meantime (maybe it |
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108 | // occured while the vector code is executing for instance). Each new |
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109 | // interrupt will be served in order of its priority. In an effort to |
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110 | // minimize overhead, the cause register is only fetched after an |
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111 | // interrupt is serviced. Because of the intvect goto's, this routine |
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112 | // will only exit when all interrupts have been serviced and no more |
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113 | // have arrived, this improves interrupt latency at the cost of |
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114 | // increasing scheduling jitter; though scheduling jitter should only |
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115 | // become apparent in high interrupt load conditions. |
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116 | // |
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117 | void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) |
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118 | { |
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119 | uint32_t cshifted; |
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120 | |
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121 | /* mips_get_sr( sr ); */ |
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122 | _ivsr = frame->c0_sr; |
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123 | |
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124 | cshifted = READ_CAUSE(); |
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125 | |
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126 | intvect: |
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127 | |
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128 | if( cshifted & 0x3 ) |
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129 | { |
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130 | // making the software interrupt the highest priority is kind of |
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131 | // stupid, but it makes the bit testing lots easier. On the other |
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132 | // hand, these ints are infrequently used and the testing overhead |
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133 | // is minimal. Who knows, high-priority software ints might be |
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134 | // handy in some situation. |
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135 | |
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136 | /* unset both software int cause bits */ |
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137 | mips_set_cause( _ivcause & ~(3 << CAUSE_IPSHIFT) ); |
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138 | |
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139 | if ( cshifted & 0x01 ) /* SW[0] */ |
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140 | { |
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141 | CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame ); |
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142 | } |
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143 | if ( cshifted & 0x02 ) /* SW[1] */ |
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144 | { |
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145 | CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame ); |
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146 | } |
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147 | cshifted = READ_CAUSE(); |
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148 | } |
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149 | |
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150 | |
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151 | if ( cshifted & 0x04 ) /* IP[0] ==> INT0 == TIMER1 */ |
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152 | { |
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153 | SET_ISR_FLAG( 0x4 ); |
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154 | CALL_ISR( MONGOOSEV_IRQ_TIMER1, frame ); |
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155 | CLR_ISR_FLAG( 0x4 ); |
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156 | if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect; |
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157 | } |
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158 | |
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159 | if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/ |
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160 | { |
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161 | SET_ISR_FLAG( 0x8 ); |
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162 | CALL_ISR( MONGOOSEV_IRQ_TIMER2, frame ); |
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163 | CLR_ISR_FLAG( 0x8 ); |
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164 | if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect; |
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165 | } |
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166 | |
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167 | if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */ |
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168 | { |
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169 | SET_ISR_FLAG( 0x10 ); |
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170 | CALL_ISR( MONGOOSEV_IRQ_INT2, frame ); |
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171 | CLR_ISR_FLAG( 0x10 ); |
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172 | if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect; |
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173 | } |
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174 | |
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175 | if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */ |
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176 | { |
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177 | SET_ISR_FLAG( 0x20 ); |
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178 | CALL_ISR( MONGOOSEV_IRQ_INT3, frame ); |
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179 | CLR_ISR_FLAG( 0x20 ); |
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180 | if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect; |
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181 | } |
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182 | |
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183 | if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */ |
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184 | { |
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185 | SET_ISR_FLAG( 0x40 ); |
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186 | CALL_ISR( MONGOOSEV_IRQ_INT4, frame ); |
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187 | CLR_ISR_FLAG( 0x40 ); |
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188 | if( (cshifted = READ_CAUSE()) & 0x3f ) goto intvect; |
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189 | } |
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190 | |
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191 | if ( cshifted & 0x80 ) /* IP[5] ==> INT5, peripheral interrupt */ |
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192 | { |
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193 | uint32_t bit; |
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194 | uint32_t pf_icr, pf_mask, pf_reset = 0; |
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195 | uint32_t i, m; |
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196 | |
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197 | pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER ); |
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198 | |
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199 | /* |
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200 | for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 ) |
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201 | { |
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202 | if ( pf_icr & pf_mask ) |
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203 | { |
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204 | SET_ISR_FLAG( 0x80 + (bit*4) ); |
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205 | CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit, frame ); |
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206 | CLR_ISR_FLAG( 0x80 + (bit*4) ); |
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207 | pf_reset |= pf_mask; |
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208 | if( (cshifted = READ_CAUSE()) & 0xff ) break; |
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209 | } |
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210 | } |
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211 | */ |
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212 | |
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213 | // |
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214 | // iterate thru 32 bits in 4 chunks of 8 bits each. This lets us |
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215 | // quickly get past unasserted interrupts instead of flogging our |
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216 | // way thru a full 32 bits. pf_mask shifts left 8 bits at a time |
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217 | // to serve as a interrupt cause test mask. |
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218 | // |
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219 | for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) ) |
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220 | { |
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221 | if ( pf_icr & pf_mask ) |
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222 | { |
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223 | // one or more of the 8 bits we're testing is high |
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224 | |
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225 | m = (1 << bit); |
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226 | |
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227 | // iterate thru the 8 bits, servicing any of the interrupts |
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228 | for(i=0; (i<8 && pf_icr); (i++, m <<= 1)) |
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229 | { |
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230 | if( pf_icr & m ) |
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231 | { |
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232 | SET_ISR_FLAG( 0x80 + ((bit + i) * 4) ); |
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233 | CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit + i, frame ); |
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234 | CLR_ISR_FLAG( 0x80 + ((bit + i) * 4) ); |
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235 | |
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236 | // or each serviced interrupt into our interrupt clear |
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237 | // mask |
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238 | pf_reset |= m; |
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239 | |
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240 | // xor off each int we service so we can immediately |
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241 | // exit once we get the last one |
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242 | pf_icr %= m; |
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243 | |
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244 | // if another interrupt has arrived, jump out right |
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245 | // away but be sure to reset all the interrupts we've |
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246 | // already serviced |
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247 | if( READ_CAUSE() & 0xff ) goto pfexit; |
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248 | } |
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249 | } |
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250 | } |
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251 | } |
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252 | pfexit: |
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253 | MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, pf_reset ); |
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254 | } |
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255 | |
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256 | // |
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257 | // this is a last ditch interrupt check, if an interrupt arrives |
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258 | // after this step, servicing it will incur the entire interrupt |
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259 | // overhead cost. |
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260 | // |
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261 | if( (cshifted = READ_CAUSE()) & 0xff ) goto intvect; |
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262 | } |
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263 | |
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264 | |
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265 | |
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266 | // eof |
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