source: rtems/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c @ 7c05d28

4.104.114.84.95
Last change on this file since 7c05d28 was 7c05d28, checked in by Joel Sherrill <joel.sherrill@…>, on May 24, 2001 at 7:54:22 PM

2000-05-24 Joel Sherrill <joel@…>

  • mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, r46xx/vectorisrs/vectorisrs.c, tx39/vectorisrs/vectorisrs.c, tx39/include/tx3904.h: All exceptions were given low numbers and thus can be now be installed and processed in a uniform manner just like interrupts. Variances between various MIPS ISA levels are not accounted for at this time.
  • mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/maxvectors.c, r46xx/vectorisrs/Makefile.am, r46xx/vectorisrs/maxvectors.c, tx39/vectorisrs/Makefile.am, tx39/vectorisrs/maxvectors.c, shared/interrupts/maxvectors.c, shared/interrupts/Makefile.am: Split the shared maxvectors.c into a variety of CPU model specific versions to simplify the build process and reduce depdencies. Deleted shared/interrupts/maxvectors.c and created various CPU model versions.
  • Property mode set to 100644
File size: 3.3 KB
Line 
1/*
2 *  ISR Vectoring support for the Synova Mongoose-V.
3 *
4 *  COPYRIGHT (c) 1989-2001.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#include <rtems.h>
15#include <stdlib.h>
16#include <libcpu/mongoose-v.h>
17
18#include "iregdef.h"
19#include "idtcpu.h"
20
21
22#define CALL_ISR(_vector,_frame) \
23  do { \
24    if ( _ISR_Vector_table[_vector] ) \
25      (_ISR_Vector_table[_vector])(_vector,_frame); \
26    else \
27      mips_default_isr(_vector); \
28  } while (0)
29
30#include <bspIo.h>  /* for printk */
31
32void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
33{
34  unsigned32  sr, srmaskoff;
35  unsigned32  cause, cshifted;
36  unsigned32  bit;
37  unsigned32  pf_icr;
38
39  /* mips_get_sr( sr ); */
40  sr = frame->regs[ R_SR ];
41
42  mips_get_cause( cause );
43
44  /* mask off everything other than the interrupt bits */
45  cause &= SR_IMASK;
46
47  /* mask off the pending interrupts in the status register */
48  srmaskoff = sr & ~cause;
49  mips_set_sr( srmaskoff );
50
51  /* allow nesting for all non-pending interrupts */
52  asm volatile( "rfe" );
53
54  cshifted = (cause & (sr & SR_IMASK)) >> CAUSE_IPSHIFT;
55
56  if ( cshifted & 0x04 )       /* IP[0] ==> INT0 == TIMER1 */
57    CALL_ISR( MONGOOSEV_IRQ_TIMER1, frame );
58   
59  if ( cshifted & 0x08 )       /* IP[1] ==> INT1 == TIMER2*/
60    CALL_ISR( MONGOOSEV_IRQ_TIMER2, frame );
61   
62  if ( cshifted & 0x10 )       /* IP[2] ==> INT2 */
63    CALL_ISR( MONGOOSEV_IRQ_INT2, frame );
64   
65  if ( cshifted & 0x20 )       /* IP[3] ==> INT3 == FPU interrupt */
66    CALL_ISR( MONGOOSEV_IRQ_INT3, frame );
67   
68  if ( cshifted & 0x40 )       /* IP[4] ==> INT4, external interrupt */
69    CALL_ISR( MONGOOSEV_IRQ_INT4, frame );
70
71  if ( cshifted & 0x80 )       /* IP[5] ==> INT5, peripheral interrupt */
72  {
73     pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
74
75     /* if !pf_icr */
76     for ( bit=0 ; bit <= 31 ; bit++, pf_icr >>= 1 ) 
77     {
78        if ( pf_icr & 1 )
79        {
80           CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit, frame );
81        }
82     } 
83  }
84
85
86  /* all the pending interrupts were serviced, now re-enable them */
87  mips_get_sr( sr );
88
89  /* we allow the 2 software interrupts to nest freely, under the
90   * assumption that the program knows what its doing... 
91   */
92
93  if( cshifted & 0x3 )
94  {
95     sr |= (SR_IBIT1 | SR_IBIT1);
96     cause &= ~(SR_IBIT1 | SR_IBIT1);
97
98     mips_set_cause(cause);
99     mips_set_sr(sr);
100
101     if ( cshifted & 0x01 )       /* SW[0] */
102     {
103        CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame );
104     } 
105     if ( cshifted & 0x02 )       /* SW[1] */
106     {
107        CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame );
108     }
109  }
110
111  sr |= cause;
112  mips_set_sr( sr );
113}
114
115void mips_default_isr( int vector )
116{
117  unsigned int sr;
118  unsigned int cause;
119
120  mips_get_sr( sr );
121  mips_get_cause( cause );
122
123  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
124    vector, cause, sr );
125  rtems_fatal_error_occurred(1);
126}
127
128/* userspace routine to assert either software interrupt */
129
130int assertSoftwareInterrupt( unsigned32 n )
131{
132   if( n >= 0 && n<2 )
133   {
134      unsigned32 c;
135
136      mips_get_cause(c);
137      c = ((n+1) << 8);
138      mips_set_cause(c);
139
140      return n;
141   }
142   else return -1;
143}
144
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