source: rtems/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c @ 2e7ed911

4.104.114.84.95
Last change on this file since 2e7ed911 was 2e7ed911, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2001 at 11:20:14 PM

2001-05-22 Greg Menke <gregory.menke@…>

  • Assisted in design and debug by Joel Sherrill <joel@…>.
  • mongoosev/duart/mg5uart.c, mongoosev/duart/mg5uart.h, mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, shared/interrupts/maxvectors.c: Now works. Significant rework of exceptions and interrupt vectoring to clean things up.
  • shared/interrupts/vectorexceptions.c: Removed.
  • shared/interrupts/Makefile.am: Reflects above.
  • Property mode set to 100644
File size: 6.8 KB
Line 
1/*
2 *  ISR Vectoring support for the Synova Mongoose-V.
3 *
4 *  COPYRIGHT (c) 1989-2001.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#include <rtems.h>
15#include <stdlib.h>
16#include <libcpu/mongoose-v.h>
17
18#include "iregdef.h"
19#include "idtcpu.h"
20
21
22#define CALL_ISR(_vector,_frame) \
23  do { \
24    if ( _ISR_Vector_table[_vector] ) \
25      (_ISR_Vector_table[_vector])(_vector,_frame); \
26    else \
27      mips_default_isr(_vector); \
28  } while (0)
29
30#include <bspIo.h>  /* for printk */
31
32
33
34
35
36
37void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
38{
39  unsigned32  sr, srmaskoff;
40  unsigned32  cause, cshifted;
41  unsigned32  bit;
42  unsigned32  pf_icr;
43
44  /* mips_get_sr( sr ); */
45  sr = frame->regs[ R_SR ];
46
47  mips_get_cause( cause );
48
49  /* mask off everything other than the interrupt bits */
50  cause &= SR_IMASK;
51
52  /* mask off the pending interrupts in the status register */
53  srmaskoff = sr & ~cause;
54  mips_set_sr( srmaskoff );
55
56  /* allow nesting for all non-pending interrupts */
57  asm volatile( "rfe" );
58
59  cshifted = (cause & (sr & SR_IMASK)) >> CAUSE_IPSHIFT;
60
61  if ( cshifted & 0x04 )       /* IP[0] ==> INT0 == TIMER1 */
62    CALL_ISR( MONGOOSEV_IRQ_TIMER1, frame );
63   
64  if ( cshifted & 0x08 )       /* IP[1] ==> INT1 == TIMER2*/
65    CALL_ISR( MONGOOSEV_IRQ_TIMER2, frame );
66   
67  if ( cshifted & 0x10 )       /* IP[2] ==> INT2 */
68    CALL_ISR( MONGOOSEV_IRQ_INT2, frame );
69   
70  if ( cshifted & 0x20 )       /* IP[3] ==> INT3 == FPU interrupt */
71    CALL_ISR( MONGOOSEV_IRQ_INT3, frame );
72   
73  if ( cshifted & 0x40 )       /* IP[4] ==> INT4, external interrupt */
74    CALL_ISR( MONGOOSEV_IRQ_INT4, frame );
75
76  if ( cshifted & 0x80 )       /* IP[5] ==> INT5, peripheral interrupt */
77  {
78     pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
79
80     /* if !pf_icr */
81     for ( bit=0 ; bit <= 31 ; bit++, pf_icr >>= 1 ) 
82     {
83        if ( pf_icr & 1 )
84        {
85           CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit, frame );
86        }
87     } 
88  }
89
90
91  /* all the pending interrupts were serviced, now re-enable them */
92  mips_get_sr( sr );
93
94  /* we allow the 2 software interrupts to nest freely, under the
95   * assumption that the program knows what its doing... 
96   */
97
98  if( cshifted & 0x3 )
99  {
100     sr |= (SR_IBIT1 | SR_IBIT1);
101     cause &= ~(SR_IBIT1 | SR_IBIT1);
102
103     mips_set_cause(cause);
104     mips_set_sr(sr);
105
106     if ( cshifted & 0x01 )       /* SW[0] */
107     {
108        CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame );
109     } 
110     if ( cshifted & 0x02 )       /* SW[1] */
111     {
112        CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame );
113     }
114  }
115
116  sr |= cause;
117  mips_set_sr( sr );
118}
119
120
121
122
123
124
125
126void mips_default_isr( int vector )
127{
128  unsigned int sr;
129  unsigned int cause;
130
131  mips_get_sr( sr );
132  mips_get_cause( cause );
133
134  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr );
135  rtems_fatal_error_occurred(1);
136}
137
138
139
140
141
142
143
144
145/* userspace routine to assert either software interrupt */
146
147int assertSoftwareInterrupt( unsigned32 n )
148{
149   if( n >= 0 && n<2 )
150   {
151      unsigned32 c;
152
153      mips_get_cause(c);
154      c = ((n+1) << 8);
155      mips_set_cause(c);
156
157      return n;
158   }
159   else return -1;
160}
161
162
163
164
165
166
167
168
169
170
171
172/* exception vectoring, from vectorexceptions.c  */
173
174/*#include <rtems.h>
175#include <stdlib.h>
176#include "iregdef.h"
177#include <bsp.h>
178#include <bspIo.h>*/
179
180
181
182
183char *cause_strings[32] = 
184{
185  /*  0 */ "Int",
186  /*  1 */ "TLB Mods",
187  /*  2 */ "TLB Load",
188  /*  3 */ "TLB Store",
189  /*  4 */ "Address Load",
190  /*  5 */ "Address Store",
191  /*  6 */ "Instruction Bus Error",
192  /*  7 */ "Data Bus Error",
193  /*  9 */ "Syscall",
194  /* 10 */ "Breakpoint",
195  /* 11 */ "Reserved Instruction",
196  /* 12 */ "Coprocessor Unuseable",
197  /* 13 */ "Overflow",
198  /* 14 */ "Trap",
199  /* 15 */ "Instruction Virtual Coherency Error",
200  /* 16 */ "FP Exception",
201  /* 17 */ "Reserved 17",
202  /* 18 */ "Reserved 17",
203  /* 19 */ "Reserved 17",
204  /* 20 */ "Reserved 20",
205  /* 21 */ "Reserved 21",
206  /* 22 */ "Reserved 22",
207  /* 23 */ "Watch",
208  /* 24 */ "Reserved 24",
209  /* 25 */ "Reserved 25",
210  /* 26 */ "Reserved 26",
211  /* 27 */ "Reserved 27",
212  /* 28 */ "Reserved 28",
213  /* 29 */ "Reserved 29",
214  /* 30 */ "Reserved 30",
215  /* 31 */ "Data Virtual Coherency Error"
216};
217
218
219
220struct regdef
221{
222      int  offset;
223      char *name;
224};
225
226
227/*
228 *  this struct holds the set of registers we're going to dump on an
229 *  exception, the symbols are defined by iregdef.h, and they are set
230 *  by cpu_asm.S into the CPU_Interrupt_frame passed here by
231 *  ISR_Handler.  Note not all registers are stored, only those used
232 *  by the cpu_asm.S code.  Refer to cpu_asm.S
233 */
234
235
236struct regdef dumpregs[]= { { R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" }, { R_A0, "R_A0" }, { R_A1,   "R_A1" }, { R_A2,   "R_A2" }, \
237                            { R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" }, { R_T2, "R_T2" }, { R_T3,   "R_T3" }, { R_T4,   "R_T4" }, \
238                            { R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" }, { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" }, \
239                            { R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" }, { R_EPC,"R_EPC"}, { -1, NULL } };
240
241
242
243void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame )
244{
245  unsigned int sr;
246  unsigned int cause;
247  int   i, j;
248
249  mips_get_sr( sr );
250  mips_get_cause( cause );
251
252  printk( "Unhandled exception %d\n", exc );
253  printk( "sr: 0x%08x  cause: 0x%08x --> %s\n", sr, cause, cause_strings[(cause >> 2) &0x1f] );
254
255  for(i=0; dumpregs[i].offset > -1; i++)
256  {
257     printk("   %s", dumpregs[i].name);
258     for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" ");
259     printk("  %08X\n", frame->regs[dumpregs[i].offset] );
260  }
261 
262  rtems_fatal_error_occurred(1);
263}
264
265
266
267
268
269
270
271#define CALL_EXC(_vector,_frame) \
272   do { \
273        if( _ISR_Vector_table[_vector] ) \
274             (_ISR_Vector_table[_vector])(_vector,_frame); \
275          else \
276             mips_default_exception_code_handler( _vector, _frame ); \
277   } while(0)
278
279
280
281
282
283void mips_vector_exceptions( CPU_Interrupt_frame *frame )
284{
285  unsigned32 cause;
286  unsigned32 exc;
287
288  mips_get_cause( cause );
289  exc = (cause >> 2) & 0x1f;
290
291  if( exc == 4 )
292     CALL_EXC( MONGOOSEV_EXCEPTION_ADEL, frame );
293
294  else if( exc == 5 )
295     CALL_EXC( MONGOOSEV_EXCEPTION_ADES, frame );
296
297  else if( exc == 6 )
298     CALL_EXC( MONGOOSEV_EXCEPTION_IBE, frame );
299
300  else if( exc == 7 )
301     CALL_EXC( MONGOOSEV_EXCEPTION_DBE, frame );
302
303  else if( exc == 8 )
304     CALL_EXC( MONGOOSEV_EXCEPTION_SYSCALL, frame );
305
306  else if( exc == 9 )
307     CALL_EXC( MONGOOSEV_EXCEPTION_BREAK, frame );
308
309  else if( exc == 10 )
310     CALL_EXC( MONGOOSEV_EXCEPTION_RI, frame );
311
312  else if( exc == 11 )
313     CALL_EXC( MONGOOSEV_EXCEPTION_CPU, frame );
314
315  else if( exc == 12 )
316     CALL_EXC( MONGOOSEV_EXCEPTION_OVERFLOW, frame );
317
318  else
319     mips_default_exception_code_handler( exc, frame );
320}
321
322
323// eof
324
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