[acdb6558] | 1 | /* |
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| 2 | * ISR Vectoring support for the Synova Mongoose-V. |
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| 3 | * |
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| 4 | * COPYRIGHT (c) 1989-2001. |
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| 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * http://www.OARcorp.com/rtems/license.html. |
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| 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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| 14 | #include <rtems.h> |
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| 15 | #include <stdlib.h> |
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| 16 | #include <libcpu/mongoose-v.h> |
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| 17 | |
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[2e7ed911] | 18 | #include "iregdef.h" |
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| 19 | #include "idtcpu.h" |
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[acdb6558] | 20 | |
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[2e7ed911] | 21 | |
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| 22 | #define CALL_ISR(_vector,_frame) \ |
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[acdb6558] | 23 | do { \ |
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| 24 | if ( _ISR_Vector_table[_vector] ) \ |
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[2e7ed911] | 25 | (_ISR_Vector_table[_vector])(_vector,_frame); \ |
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[acdb6558] | 26 | else \ |
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[2e7ed911] | 27 | mips_default_isr(_vector); \ |
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[acdb6558] | 28 | } while (0) |
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| 29 | |
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| 30 | #include <bspIo.h> /* for printk */ |
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| 31 | |
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[2e7ed911] | 32 | |
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| 33 | |
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| 34 | |
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| 35 | |
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| 36 | |
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| 37 | void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) |
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[acdb6558] | 38 | { |
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[2e7ed911] | 39 | unsigned32 sr, srmaskoff; |
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| 40 | unsigned32 cause, cshifted; |
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| 41 | unsigned32 bit; |
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| 42 | unsigned32 pf_icr; |
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| 43 | |
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| 44 | /* mips_get_sr( sr ); */ |
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| 45 | sr = frame->regs[ R_SR ]; |
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| 46 | |
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| 47 | mips_get_cause( cause ); |
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| 48 | |
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| 49 | /* mask off everything other than the interrupt bits */ |
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| 50 | cause &= SR_IMASK; |
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| 51 | |
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| 52 | /* mask off the pending interrupts in the status register */ |
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| 53 | srmaskoff = sr & ~cause; |
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| 54 | mips_set_sr( srmaskoff ); |
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| 55 | |
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| 56 | /* allow nesting for all non-pending interrupts */ |
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| 57 | asm volatile( "rfe" ); |
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| 58 | |
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| 59 | cshifted = (cause & (sr & SR_IMASK)) >> CAUSE_IPSHIFT; |
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| 60 | |
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| 61 | if ( cshifted & 0x04 ) /* IP[0] ==> INT0 == TIMER1 */ |
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| 62 | CALL_ISR( MONGOOSEV_IRQ_TIMER1, frame ); |
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| 63 | |
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| 64 | if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/ |
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| 65 | CALL_ISR( MONGOOSEV_IRQ_TIMER2, frame ); |
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| 66 | |
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| 67 | if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */ |
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| 68 | CALL_ISR( MONGOOSEV_IRQ_INT2, frame ); |
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| 69 | |
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| 70 | if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */ |
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| 71 | CALL_ISR( MONGOOSEV_IRQ_INT3, frame ); |
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| 72 | |
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| 73 | if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */ |
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| 74 | CALL_ISR( MONGOOSEV_IRQ_INT4, frame ); |
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| 75 | |
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| 76 | if ( cshifted & 0x80 ) /* IP[5] ==> INT5, peripheral interrupt */ |
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| 77 | { |
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| 78 | pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER ); |
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| 79 | |
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| 80 | /* if !pf_icr */ |
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| 81 | for ( bit=0 ; bit <= 31 ; bit++, pf_icr >>= 1 ) |
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| 82 | { |
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| 83 | if ( pf_icr & 1 ) |
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| 84 | { |
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| 85 | CALL_ISR( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit, frame ); |
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| 86 | } |
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| 87 | } |
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| 88 | } |
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| 89 | |
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| 90 | |
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| 91 | /* all the pending interrupts were serviced, now re-enable them */ |
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| 92 | mips_get_sr( sr ); |
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| 93 | |
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| 94 | /* we allow the 2 software interrupts to nest freely, under the |
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| 95 | * assumption that the program knows what its doing... |
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| 96 | */ |
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| 97 | |
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| 98 | if( cshifted & 0x3 ) |
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| 99 | { |
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| 100 | sr |= (SR_IBIT1 | SR_IBIT1); |
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| 101 | cause &= ~(SR_IBIT1 | SR_IBIT1); |
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| 102 | |
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| 103 | mips_set_cause(cause); |
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| 104 | mips_set_sr(sr); |
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| 105 | |
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| 106 | if ( cshifted & 0x01 ) /* SW[0] */ |
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| 107 | { |
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| 108 | CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame ); |
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| 109 | } |
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| 110 | if ( cshifted & 0x02 ) /* SW[1] */ |
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| 111 | { |
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| 112 | CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame ); |
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| 113 | } |
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| 114 | } |
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| 115 | |
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| 116 | sr |= cause; |
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| 117 | mips_set_sr( sr ); |
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| 118 | } |
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| 119 | |
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| 120 | |
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| 121 | |
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| 122 | |
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| 123 | |
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| 124 | |
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| 125 | |
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| 126 | void mips_default_isr( int vector ) |
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| 127 | { |
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| 128 | unsigned int sr; |
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| 129 | unsigned int cause; |
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| 130 | |
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| 131 | mips_get_sr( sr ); |
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| 132 | mips_get_cause( cause ); |
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| 133 | |
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| 134 | printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr ); |
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[acdb6558] | 135 | rtems_fatal_error_occurred(1); |
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| 136 | } |
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| 137 | |
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[2e7ed911] | 138 | |
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| 139 | |
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| 140 | |
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| 141 | |
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| 142 | |
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| 143 | |
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| 144 | |
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| 145 | /* userspace routine to assert either software interrupt */ |
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| 146 | |
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| 147 | int assertSoftwareInterrupt( unsigned32 n ) |
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| 148 | { |
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| 149 | if( n >= 0 && n<2 ) |
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| 150 | { |
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| 151 | unsigned32 c; |
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| 152 | |
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| 153 | mips_get_cause(c); |
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| 154 | c = ((n+1) << 8); |
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| 155 | mips_set_cause(c); |
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| 156 | |
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| 157 | return n; |
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| 158 | } |
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| 159 | else return -1; |
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| 160 | } |
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| 161 | |
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| 162 | |
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| 163 | |
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| 164 | |
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| 165 | |
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| 166 | |
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| 167 | |
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| 168 | |
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| 169 | |
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| 170 | |
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| 171 | |
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| 172 | /* exception vectoring, from vectorexceptions.c */ |
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| 173 | |
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| 174 | /*#include <rtems.h> |
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| 175 | #include <stdlib.h> |
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| 176 | #include "iregdef.h" |
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| 177 | #include <bsp.h> |
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| 178 | #include <bspIo.h>*/ |
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| 179 | |
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| 180 | |
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| 181 | |
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| 182 | |
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| 183 | char *cause_strings[32] = |
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| 184 | { |
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| 185 | /* 0 */ "Int", |
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| 186 | /* 1 */ "TLB Mods", |
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| 187 | /* 2 */ "TLB Load", |
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| 188 | /* 3 */ "TLB Store", |
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| 189 | /* 4 */ "Address Load", |
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| 190 | /* 5 */ "Address Store", |
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| 191 | /* 6 */ "Instruction Bus Error", |
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| 192 | /* 7 */ "Data Bus Error", |
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| 193 | /* 9 */ "Syscall", |
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| 194 | /* 10 */ "Breakpoint", |
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| 195 | /* 11 */ "Reserved Instruction", |
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| 196 | /* 12 */ "Coprocessor Unuseable", |
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| 197 | /* 13 */ "Overflow", |
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| 198 | /* 14 */ "Trap", |
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| 199 | /* 15 */ "Instruction Virtual Coherency Error", |
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| 200 | /* 16 */ "FP Exception", |
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| 201 | /* 17 */ "Reserved 17", |
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| 202 | /* 18 */ "Reserved 17", |
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| 203 | /* 19 */ "Reserved 17", |
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| 204 | /* 20 */ "Reserved 20", |
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| 205 | /* 21 */ "Reserved 21", |
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| 206 | /* 22 */ "Reserved 22", |
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| 207 | /* 23 */ "Watch", |
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| 208 | /* 24 */ "Reserved 24", |
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| 209 | /* 25 */ "Reserved 25", |
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| 210 | /* 26 */ "Reserved 26", |
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| 211 | /* 27 */ "Reserved 27", |
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| 212 | /* 28 */ "Reserved 28", |
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| 213 | /* 29 */ "Reserved 29", |
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| 214 | /* 30 */ "Reserved 30", |
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| 215 | /* 31 */ "Data Virtual Coherency Error" |
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| 216 | }; |
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| 217 | |
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| 218 | |
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| 219 | |
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| 220 | struct regdef |
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| 221 | { |
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| 222 | int offset; |
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| 223 | char *name; |
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| 224 | }; |
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| 225 | |
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| 226 | |
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| 227 | /* |
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| 228 | * this struct holds the set of registers we're going to dump on an |
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| 229 | * exception, the symbols are defined by iregdef.h, and they are set |
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| 230 | * by cpu_asm.S into the CPU_Interrupt_frame passed here by |
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| 231 | * ISR_Handler. Note not all registers are stored, only those used |
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| 232 | * by the cpu_asm.S code. Refer to cpu_asm.S |
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| 233 | */ |
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| 234 | |
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| 235 | |
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| 236 | struct regdef dumpregs[]= { { R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" }, { R_A0, "R_A0" }, { R_A1, "R_A1" }, { R_A2, "R_A2" }, \ |
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| 237 | { R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" }, { R_T2, "R_T2" }, { R_T3, "R_T3" }, { R_T4, "R_T4" }, \ |
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| 238 | { R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" }, { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" }, \ |
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| 239 | { R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" }, { R_EPC,"R_EPC"}, { -1, NULL } }; |
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| 240 | |
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| 241 | |
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| 242 | |
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| 243 | void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame ) |
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[acdb6558] | 244 | { |
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| 245 | unsigned int sr; |
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| 246 | unsigned int cause; |
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[2e7ed911] | 247 | int i, j; |
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[acdb6558] | 248 | |
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| 249 | mips_get_sr( sr ); |
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| 250 | mips_get_cause( cause ); |
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| 251 | |
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[2e7ed911] | 252 | printk( "Unhandled exception %d\n", exc ); |
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| 253 | printk( "sr: 0x%08x cause: 0x%08x --> %s\n", sr, cause, cause_strings[(cause >> 2) &0x1f] ); |
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[acdb6558] | 254 | |
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[2e7ed911] | 255 | for(i=0; dumpregs[i].offset > -1; i++) |
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| 256 | { |
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| 257 | printk(" %s", dumpregs[i].name); |
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| 258 | for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" "); |
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| 259 | printk(" %08X\n", frame->regs[dumpregs[i].offset] ); |
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[acdb6558] | 260 | } |
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[2e7ed911] | 261 | |
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| 262 | rtems_fatal_error_occurred(1); |
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| 263 | } |
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| 264 | |
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| 265 | |
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| 266 | |
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| 267 | |
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| 268 | |
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| 269 | |
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| 270 | |
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| 271 | #define CALL_EXC(_vector,_frame) \ |
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| 272 | do { \ |
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| 273 | if( _ISR_Vector_table[_vector] ) \ |
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| 274 | (_ISR_Vector_table[_vector])(_vector,_frame); \ |
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| 275 | else \ |
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| 276 | mips_default_exception_code_handler( _vector, _frame ); \ |
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| 277 | } while(0) |
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| 278 | |
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| 279 | |
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| 280 | |
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| 281 | |
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[acdb6558] | 282 | |
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[2e7ed911] | 283 | void mips_vector_exceptions( CPU_Interrupt_frame *frame ) |
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| 284 | { |
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| 285 | unsigned32 cause; |
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| 286 | unsigned32 exc; |
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| 287 | |
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| 288 | mips_get_cause( cause ); |
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| 289 | exc = (cause >> 2) & 0x1f; |
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| 290 | |
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| 291 | if( exc == 4 ) |
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| 292 | CALL_EXC( MONGOOSEV_EXCEPTION_ADEL, frame ); |
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| 293 | |
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| 294 | else if( exc == 5 ) |
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| 295 | CALL_EXC( MONGOOSEV_EXCEPTION_ADES, frame ); |
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| 296 | |
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| 297 | else if( exc == 6 ) |
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| 298 | CALL_EXC( MONGOOSEV_EXCEPTION_IBE, frame ); |
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| 299 | |
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| 300 | else if( exc == 7 ) |
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| 301 | CALL_EXC( MONGOOSEV_EXCEPTION_DBE, frame ); |
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| 302 | |
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| 303 | else if( exc == 8 ) |
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| 304 | CALL_EXC( MONGOOSEV_EXCEPTION_SYSCALL, frame ); |
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[acdb6558] | 305 | |
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[2e7ed911] | 306 | else if( exc == 9 ) |
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| 307 | CALL_EXC( MONGOOSEV_EXCEPTION_BREAK, frame ); |
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| 308 | |
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| 309 | else if( exc == 10 ) |
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| 310 | CALL_EXC( MONGOOSEV_EXCEPTION_RI, frame ); |
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| 311 | |
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| 312 | else if( exc == 11 ) |
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| 313 | CALL_EXC( MONGOOSEV_EXCEPTION_CPU, frame ); |
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| 314 | |
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| 315 | else if( exc == 12 ) |
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| 316 | CALL_EXC( MONGOOSEV_EXCEPTION_OVERFLOW, frame ); |
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| 317 | |
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| 318 | else |
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| 319 | mips_default_exception_code_handler( exc, frame ); |
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[acdb6558] | 320 | } |
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[2e7ed911] | 321 | |
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| 322 | |
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| 323 | // eof |
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| 324 | |
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