source: rtems/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h @ b85df34

4.104.114.84.95
Last change on this file since b85df34 was b85df34, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 20, 2001 at 1:24:39 PM

2001-04-20 Joel Sherrill <joel@…>

  • mongoosev/duart/mg5uart.c (mg5uart_enable_interrupts): Honor the other bits set in the Peripheral Function Interrupt Mask Register when modifying those enabled for the DUART.
  • mongoosev/include/mongoose-v.h (MONGOOSEV_ATOMIC_MASK, MONGOOSEV_PFICR, MONGOOSEV_PFIMR, mongoosev_set_in_pficr, mongoosev_clear_in_pficr, mongoosev_set_in_pfimr, mongoosev_clear_in_pfimr, MONGOOSEV_UART_ALL_IRQ_BITS): New macros.
  • Property mode set to 100644
File size: 11.8 KB
Line 
1/*
2 *  MIPS Mongoose-V specific information
3 *
4 *  COPYRIGHT (c) 1989-2001.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#ifndef __MONGOOSEV_h
15#define __MONGOOSEV_h
16
17/*
18 *  Macros to assist in accessing memory mapped Mongoose registers
19 */
20
21#define MONGOOSEV_READ( _base ) \
22  *((volatile unsigned32 *)(_base))
23
24#define MONGOOSEV_WRITE( _base, _value ) \
25  *((volatile unsigned32 *)(_base)) = (_value)
26
27#define MONGOOSEV_READ_REGISTER( _base, _register ) \
28  *((volatile unsigned32 *)((_base) + (_register)))
29
30#define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \
31  *((volatile unsigned32 *)((_base) + (_register))) = (_value)
32
33#define MONGOOSEV_ATOMIC_MASK( _addr, _mask, _new ) \
34  do { \
35    rtems_interrupt_level  Irql; \
36    rtems_unsigned32       tmp; \
37    \
38    rtems_interrupt_disable(Irql); \
39      tmp = *((volatile unsigned32 *)(_addr)) & ~(_mask); \
40      *((volatile unsigned32 *)(_addr)) = tmp | (_new); \
41    rtems_interrupt_enable(Irql); \
42  } while (0)
43
44/*
45 *  BIU and DRAM Registers
46 */
47
48#define MONGOOSEV_BIU_CACHE_CONFIGURATION_REGISTER       0xFFFE0130
49#define MONGOOSEV_DRAM_CONFIGURATION_REGISTER            0xFFFE0120
50#define MONGOOSEV_REFRESH_TIMER_INITIAL_COUNTER_REGISTER 0xFFFE0010
51#define MONGOOSEV_WAIT_STATE_CONFIGURATION_REGISTER_BASE 0xFFFE0100
52
53/*
54 *  Peripheral Function Addresses
55 *
56 *  NOTE: Status and Interrupt Cause use the same bits
57 */
58
59#define MONGOOSEV_PERIPHERAL_COMMAND_REGISTER                   0xFFFE0180
60#define MONGOOSEV_PERIPHERAL_STATUS_REGISTER                    0xFFFE0184
61#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER  0xFFFE0188
62#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER   0xFFFE018C
63
64#define MONGOOSEV_PFICR MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER
65#define MONGOOSEV_PFIMR MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER
66
67#define mongoosev_set_in_pficr( _mask, _bits ) \
68  MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFICR, _mask, _bits )
69#define mongoosev_clear_in_pficr( _mask, _bits ) \
70  MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFICR, _mask, ~(_bits) )
71
72#define mongoosev_set_in_pfimr( _mask, _bits ) \
73  MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFIMR, _mask, _bits )
74#define mongoosev_clear_in_pfimr( _mask, _bits ) \
75  MONGOOSEV_ATOMIC_MASK( MONGOOSEV_PFIMR, _mask, ~(_bits) )
76
77/* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */
78#define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS   0x0001
79#define MONGOOSEV_UART_CMD_LOOPBACK_CTSN      0x0002
80#define MONGOOSEV_UART_CMD_LOOPBACK_RXTX      0x0004
81
82#define MONGOOSEV_UART_CMD_TX_ENABLE        0x001
83#define MONGOOSEV_UART_CMD_TX_DISABLE       0x000
84#define MONGOOSEV_UART_CMD_RX_ENABLE        0x002
85#define MONGOOSEV_UART_CMD_RX_DISABLE       0x000
86#define MONGOOSEV_UART_CMD_TX_READY         0x004
87#define MONGOOSEV_UART_CMD_PARITY_ENABLE    0x008
88#define MONGOOSEV_UART_CMD_PARITY_DISABLE   0x000
89#define MONGOOSEV_UART_CMD_PARITY_EVEN      0x800
90#define MONGOOSEV_UART_CMD_PARITY_ODD       0x000
91
92#define MONGOOSEV_UART0_CMD_SHIFT 5
93#define MONGOOSEV_UART1_CMD_SHIFT 11
94
95#define MONGOOSEV_UART_CMD_TX_ENABLE_0 \
96        (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
97#define MONGOOSEV_UART_CMD_RX_ENABLE_0 \
98        (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
99#define MONGOOSEV_UART_CMD_TX_READY_0 \
100        (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
101#define MONGOOSEV_UART_CMD_PARITY_ENABLE_0 \
102        (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
103#define MONGOOSEV_UART_CMD_PARITY_DISABLE_0 \
104        (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
105#define MONGOOSEV_UART_CMD_PARITY_EVEN_0 \
106        (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
107#define MONGOOSEV_UART_CMD_PARITY_ODD_0 \
108        (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
109
110#define MONGOOSEV_UART_CMD_TX_ENABLE_1 \
111        (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
112#define MONGOOSEV_UART_CMD_RX_ENABLE_1 \
113        (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
114#define MONGOOSEV_UART_CMD_TX_READY_1 \
115        (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
116#define MONGOOSEV_UART_CMD_PARITY_ENABLE_1 \
117        (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
118#define MONGOOSEV_UART_CMD_PARITY_DISABLE_1 \
119        (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
120#define MONGOOSEV_UART_CMD_PARITY_EVEN_1 \
121        (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
122#define MONGOOSEV_UART_CMD_PARITY_ODD_1 \
123        (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
124
125/* UART Bits in Peripheral Status and Interrupt Cause Register */
126#define MONGOOSEV_UART_RX_FRAME_ERROR              0x0001
127#define MONGOOSEV_UART_RX_OVERRUN_ERROR            0x0002
128#define MONGOOSEV_UART_TX_EMPTY                    0x0004
129#define MONGOOSEV_UART_TX_READY                    0x0008
130#define MONGOOSEV_UART_RX_READY                    0x0010
131
132#define MONGOOSEV_UART_ALL_RX_STATUS_BITS          0x0003
133#define MONGOOSEV_UART_ALL_STATUS_BITS             0x001F
134#define MONGOOSEV_UART_ALL_IRQ_BITS                0x001F
135
136/*
137 *  The Peripheral Interrupt Status, Cause, and Mask registers have the
138 *  same bit assignments although some revisions of the document have
139 *  the Cause and Status registers incorrect. 
140 */
141
142#define MONGOOSEV_UART0_IRQ_SHIFT 11
143#define MONGOOSEV_UART1_IRQ_SHIFT 17
144
145#define MONGOOSEV_UART_FRAME_ERROR_1 \
146        (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
147#define MONGOOSEV_UART_RX_OVERRUN_ERROR_1 \
148        (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
149#define MONGOOSEV_UART_TX_EMPTY_1 \
150        (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
151#define MONGOOSEV_UART_TX_READY_1 \
152        (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
153#define MONGOOSEV_UART_RX_READY_1 \
154        (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
155
156#define MONGOOSEV_UART_FRAME_ERROR_0 \
157        (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
158#define MONGOOSEV_UART_RX_OVERRUN_ERROR_0 \
159        (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
160#define MONGOOSEV_UART_TX_EMPTY_0 \
161        (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
162#define MONGOOSEV_UART_TX_READY_0 \
163        (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
164#define MONGOOSEV_UART_RX_READY_0 \
165        (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
166
167/*
168 *  Bits in the Peripheral Interrupt Mask Register
169 */
170
171/*
172** Interrupt Status/Cause/Mask register bits - from 31 to 0
173*/
174#define MONGOOSEV_EDAC_SERR_BIT          0x80000000
175#define MONGOOSEV_EDAC_MERR_BIT          0x40000000
176/* 29 - 24 reserved */
177#define MONGOOSEV_UART_0_RX_READY        0x00008000
178#define MONGOOSEV_UART_0_TX_READY        0x00004000
179#define MONGOOSEV_UART_0_TX_EMPTY        0x00002000
180#define MONGOOSEV_UART_0_RX_OVERRUN      0x00001000
181#define MONGOOSEV_UART_0_FRAME_ERROR     0x00000800
182#define MONGOOSEV_UART_0_RESERVED        0x00000400
183#define MONGOOSEV_UART_1_RX_READY        0x00200000
184#define MONGOOSEV_UART_1_TX_READY        0x00100000
185#define MONGOOSEV_UART_1_TX_EMPTY        0x00080000
186#define MONGOOSEV_UART_1_RX_OVERRUN      0x00040000
187#define MONGOOSEV_UART_1_FRAME_ERROR     0x00020000
188#define MONGOOSEV_UART_1_RESERVED        0x00010000
189#define MONGOOSEV_MAVN_WRITE_ACCESS      0x00400000
190#define MONGOOSEV_MAVN_READ_ACCESS       0x00800000
191#define MONGOOSEV_EXTERN_INT_9           0x00000200
192#define MONGOOSEV_EXTERN_INT_8           0x00000100
193#define MONGOOSEV_EXTERN_INT_7           0x00000080
194#define MONGOOSEV_EXTERN_INT_6           0x00000040
195#define MONGOOSEV_EXTERN_INT_5           0x00000020
196#define MONGOOSEV_EXTERN_INT_4           0x00000010
197#define MONGOOSEV_EXTERN_INT_3           0x00000008
198#define MONGOOSEV_EXTERN_INT_2           0x00000004
199#define MONGOOSEV_EXTERN_INT_1           0x00000002
200#define MONGOOSEV_EXTERN_INT_0           0x00000001
201
202
203/*
204 *  EDAC Registers
205 */
206
207#define MONGOOSEV_EDAC_ERROR_ADDRESS_REGISTER       0xFFFE0190
208#define MONGOOSEV_EDAC_PARITY_TEST_MODE_REGISTER    0xFFFE0194
209
210/*
211 *  MAVN Registers
212 */
213
214#define MONGOOSEV_MAVN_TEST_REGISTER               0xFFFE01B4
215#define MONGOOSEV_MAVN_ACCESS_PRIVILEGE_REGISTER   0xFFFE01B8
216#define MONGOOSEV_MAVN_ACCESS_VIOLATION_REGISTER   0xFFFE01BC
217#define MONGOOSEV_MAVN_RANGE_0_REGISTER            0xFFFE01C0
218#define MONGOOSEV_MAVN_RANGE_1_REGISTER            0xFFFE01C4
219#define MONGOOSEV_MAVN_RANGE_2_REGISTER            0xFFFE01C8
220#define MONGOOSEV_MAVN_RANGE_3_REGISTER            0xFFFE01CC
221#define MONGOOSEV_MAVN_RANGE_4_REGISTER            0xFFFE01D0
222#define MONGOOSEV_MAVN_RANGE_5_REGISTER            0xFFFE01D4
223#define MONGOOSEV_MAVN_RANGE_6_REGISTER            0xFFFE01D8
224#define MONGOOSEV_MAVN_RANGE_7_REGISTER            0xFFFE01DC
225
226/*
227 *  Timer Base Addresses, Offsets, and Values
228 */
229
230#define MONGOOSEV_TIMER1_BASE    0xFFFE0000
231#define MONGOOSEV_TIMER2_BASE    0xFFFE0008
232
233#define MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER 0
234#define MONGOOSEV_TIMER_CONTROL_REGISTER         4
235
236/* Timer Control Register Constants */
237#define MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE    0x04
238#define MONGOOSEV_TIMER_CONTROL_INTERRUPT_ENABLE  0x02
239#define MONGOOSEV_TIMER_CONTROL_TIMEOUT           0x01
240
241/*
242 *  UART Base Addresses and Offsets
243 *
244 *  Many bits in the peripheral command register are UART related
245 *  and the bits are defined there.
246 */
247
248#define MONGOOSEV_UART0_BASE   0xFFFE01E8
249#define MONGOOSEV_UART1_BASE   0xFFFE01F4
250
251#define MONGOOSEV_RX_BUFFER    0
252#define MONGOOSEV_TX_BUFFER    4
253#define MONGOOSEV_BAUD_RATE    8
254
255/*
256 *  Interrupt Vector Numbers
257 *
258 *  NOTE: IRQ INT5 is logical or of peripheral cause register
259 *        per p. 5-22 of Mongoose-V manual.
260 */
261
262#define MONGOOSEV_IRQ_INT0                    0
263#define MONGOOSEV_IRQ_TIMER1                  MONGOOSEV_IRQ_INT0
264#define MONGOOSEV_IRQ_INT1                    1
265#define MONGOOSEV_IRQ_TIMER2                  MONGOOSEV_IRQ_INT1
266#define MONGOOSEV_IRQ_INT2                    2
267#define MONGOOSEV_IRQ_INT4                    3
268/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
269#define MONGOOSEV_IRQ_PERIPHERAL_BASE         4
270#define MONGOOSEV_IRQ_XINT0                   4
271#define MONGOOSEV_IRQ_XINT1                   5
272#define MONGOOSEV_IRQ_XINT2                   6
273#define MONGOOSEV_IRQ_XINT3                   7
274#define MONGOOSEV_IRQ_XINT4                   8
275#define MONGOOSEV_IRQ_XINT5                   9
276#define MONGOOSEV_IRQ_XINT6                  10
277#define MONGOOSEV_IRQ_XINT7                  11
278#define MONGOOSEV_IRQ_XINT8                  12
279#define MONGOOSEV_IRQ_XINT9                  13
280#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION  14
281#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION 15
282#define MONGOOSEV_IRQ_RESERVED_BIT_12        16
283#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR   17
284#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR 18
285#define MONGOOSEV_IRQ_UART1_TX_EMPTY         19
286#define MONGOOSEV_IRQ_UART1_TX_READY         20
287#define MONGOOSEV_IRQ_UART1_RX_READY         21
288#define MONGOOSEV_IRQ_RESERVED_BIT_18        22
289#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR   23
290#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR 24
291#define MONGOOSEV_IRQ_UART0_TX_EMPTY         25
292#define MONGOOSEV_IRQ_UART0_TX_READY         26
293#define MONGOOSEV_IRQ_UART0_RX_READY         27
294#define MONGOOSEV_IRQ_RESERVED_24            28
295#define MONGOOSEV_IRQ_RESERVED_25            29
296#define MONGOOSEV_IRQ_RESERVED_26            30
297#define MONGOOSEV_IRQ_RESERVED_27            31
298#define MONGOOSEV_IRQ_RESERVED_28            32
299#define MONGOOSEV_IRQ_RESERVED_29            33
300#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR    34
301#define MONGOOSEV_IRQ_CORRECTABLE_ERROR      35
302
303#define MONGOOSEV_IRQ_SOFTWARE_1             36
304#define MONGOOSEV_IRQ_SOFTWARE_2             37
305
306#endif
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