source: rtems/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h @ acdb6558

4.104.114.84.9
Last change on this file since acdb6558 was acdb6558, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 14, 2001 at 12:49:17 AM

2001-03-13 Joel Sherrill <joel@…>

  • Added mongoose-v, mongoose-v/include, and mongoose-v/vectorisrs directories.
  • mongoosev/.cvsignore, mongoosev/Makefile.am, mongoosev/README, mongoosev/duart/.cvsignore, mongoosev/duart/Makefile.am, mongoosev/duart/README.mguart, mongoosev/duart/mg5uart.c, mongoosev/duart/mg5uart.h, mongoosev/duart/mg5uart_reg.c, mongoosev/include/.cvsignore, mongoosev/include/Makefile.am, mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/.cvsignore, mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/vectorisrs.c: New files.
  • Makefile.am, configure.in, shared/interrupts/Makefile.am, shared/interrupts/maxvectors.c: Added support for mongoosev.
  • tx39/vectorisrs/vectorisrs.c: Corrected warning.
  • Property mode set to 100644
File size: 10.8 KB
Line 
1/*
2 *  MIPS Mongoose-V specific information
3 *
4 *  COPYRIGHT (c) 1989-2001.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#ifndef __MONGOOSEV_h
15#define __MONGOOSEV_h
16
17/*
18 *  Macros to assist in accessing memory mapped Mongoose registers
19 */
20
21#define MONGOOSEV_READ( _base ) \
22  *((volatile unsigned32 *)(_base))
23
24#define MONGOOSEV_WRITE( _base, _value ) \
25  *((volatile unsigned32 *)(_base)) = (_value)
26
27#define MONGOOSEV_READ_REGISTER( _base, _register ) \
28  *((volatile unsigned32 *)((_base) + (_register)))
29
30#define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \
31  *((volatile unsigned32 *)((_base) + (_register))) = (_value)
32
33/*
34 *  BIU and DRAM Registers
35 */
36
37#define MONGOOSEV_BIU_CACHE_CONFIGURATION_REGISTER       0xFFFE0130
38#define MONGOOSEV_DRAM_CONFIGURATION_REGISTER            0xFFFE0120
39#define MONGOOSEV_REFRESH_TIMER_INITIAL_COUNTER_REGISTER 0xFFFE0010
40#define MONGOOSEV_WAIT_STATE_CONFIGURATION_REGISTER_BASE 0xFFFE0100
41
42/*
43 *  Peripheral Function Addresses
44 *
45 *  NOTE: Status and Interrupt Cause use the same bits
46 */
47
48#define MONGOOSEV_PERIPHERAL_COMMAND_REGISTER                   0xFFFE0180
49#define MONGOOSEV_PERIPHERAL_STATUS_REGISTER                    0xFFFE0184
50#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER  0xFFFE0188
51#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER   0xFFFE018C
52
53/* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */
54#define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS   0x0001
55#define MONGOOSEV_UART_CMD_LOOPBACK_CTSN      0x0002
56#define MONGOOSEV_UART_CMD_LOOPBACK_RXTX      0x0004
57
58#define MONGOOSEV_UART_CMD_TX_ENABLE        0x001
59#define MONGOOSEV_UART_CMD_TX_DISABLE       0x000
60#define MONGOOSEV_UART_CMD_RX_ENABLE        0x002
61#define MONGOOSEV_UART_CMD_RX_DISABLE       0x000
62#define MONGOOSEV_UART_CMD_TX_READY         0x004
63#define MONGOOSEV_UART_CMD_PARITY_ENABLE    0x008
64#define MONGOOSEV_UART_CMD_PARITY_DISABLE   0x000
65#define MONGOOSEV_UART_CMD_PARITY_EVEN      0x800
66#define MONGOOSEV_UART_CMD_PARITY_ODD       0x000
67
68#define MONGOOSEV_UART0_CMD_SHIFT 5
69#define MONGOOSEV_UART1_CMD_SHIFT 11
70
71#define MONGOOSEV_UART_CMD_TX_ENABLE_0 \
72        (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
73#define MONGOOSEV_UART_CMD_RX_ENABLE_0 \
74        (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
75#define MONGOOSEV_UART_CMD_TX_READY_0 \
76        (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
77#define MONGOOSEV_UART_CMD_PARITY_ENABLE_0 \
78        (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
79#define MONGOOSEV_UART_CMD_PARITY_DISABLE_0 \
80        (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
81#define MONGOOSEV_UART_CMD_PARITY_EVEN_0 \
82        (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
83#define MONGOOSEV_UART_CMD_PARITY_ODD_0 \
84        (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
85
86#define MONGOOSEV_UART_CMD_TX_ENABLE_1 \
87        (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
88#define MONGOOSEV_UART_CMD_RX_ENABLE_1 \
89        (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
90#define MONGOOSEV_UART_CMD_TX_READY_1 \
91        (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
92#define MONGOOSEV_UART_CMD_PARITY_ENABLE_1 \
93        (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
94#define MONGOOSEV_UART_CMD_PARITY_DISABLE_1 \
95        (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
96#define MONGOOSEV_UART_CMD_PARITY_EVEN_1 \
97        (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
98#define MONGOOSEV_UART_CMD_PARITY_ODD_1 \
99        (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
100
101/* UART Bits in Peripheral Status and Interrupt Cause Register */
102#define MONGOOSEV_UART_RX_FRAME_ERROR              0x0001
103#define MONGOOSEV_UART_RX_OVERRUN_ERROR            0x0002
104#define MONGOOSEV_UART_TX_EMPTY                    0x0004
105#define MONGOOSEV_UART_TX_READY                    0x0008
106#define MONGOOSEV_UART_RX_READY                    0x0010
107
108#define MONGOOSEV_UART_ALL_RX_STATUS_BITS          0x0003
109#define MONGOOSEV_UART_ALL_STATUS_BITS             0x001F
110
111/*
112 *  The Peripheral Interrupt Status, Cause, and Mask registers have the
113 *  same bit assignments although some revisions of the document have
114 *  the Cause and Status registers incorrect. 
115 */
116
117#define MONGOOSEV_UART0_IRQ_SHIFT 11
118#define MONGOOSEV_UART1_IRQ_SHIFT 17
119
120#define MONGOOSEV_UART_FRAME_ERROR_1 \
121        (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
122#define MONGOOSEV_UART_RX_OVERRUN_ERROR_1 \
123        (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
124#define MONGOOSEV_UART_TX_EMPTY_1 \
125        (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
126#define MONGOOSEV_UART_TX_READY_1 \
127        (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
128#define MONGOOSEV_UART_RX_READY_1 \
129        (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
130
131#define MONGOOSEV_UART_FRAME_ERROR_0 \
132        (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
133#define MONGOOSEV_UART_RX_OVERRUN_ERROR_0 \
134        (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
135#define MONGOOSEV_UART_TX_EMPTY_0 \
136        (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
137#define MONGOOSEV_UART_TX_READY_0 \
138        (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
139#define MONGOOSEV_UART_RX_READY_0 \
140        (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
141
142/*
143 *  Bits in the Peripheral Interrupt Mask Register
144 */
145
146/*
147** Interrupt Status/Cause/Mask register bits - from 31 to 0
148*/
149#define MONGOOSEV_EDAC_SERR_BIT          0x80000000
150#define MONGOOSEV_EDAC_MERR_BIT          0x40000000
151/* 29 - 24 reserved */
152#define MONGOOSEV_UART_0_RX_READY        0x00008000
153#define MONGOOSEV_UART_0_TX_READY        0x00004000
154#define MONGOOSEV_UART_0_TX_EMPTY        0x00002000
155#define MONGOOSEV_UART_0_RX_OVERRUN      0x00001000
156#define MONGOOSEV_UART_0_FRAME_ERROR     0x00000800
157#define MONGOOSEV_UART_0_RESERVED        0x00000400
158#define MONGOOSEV_UART_1_RX_READY        0x00200000
159#define MONGOOSEV_UART_1_TX_READY        0x00100000
160#define MONGOOSEV_UART_1_TX_EMPTY        0x00080000
161#define MONGOOSEV_UART_1_RX_OVERRUN      0x00040000
162#define MONGOOSEV_UART_1_FRAME_ERROR     0x00020000
163#define MONGOOSEV_UART_1_RESERVED        0x00010000
164#define MONGOOSEV_MAVN_WRITE_ACCESS      0x00400000
165#define MONGOOSEV_MAVN_READ_ACCESS       0x00800000
166#define MONGOOSEV_EXTERN_INT_9           0x00000200
167#define MONGOOSEV_EXTERN_INT_8           0x00000100
168#define MONGOOSEV_EXTERN_INT_7           0x00000080
169#define MONGOOSEV_EXTERN_INT_6           0x00000040
170#define MONGOOSEV_EXTERN_INT_5           0x00000020
171#define MONGOOSEV_EXTERN_INT_4           0x00000010
172#define MONGOOSEV_EXTERN_INT_3           0x00000008
173#define MONGOOSEV_EXTERN_INT_2           0x00000004
174#define MONGOOSEV_EXTERN_INT_1           0x00000002
175#define MONGOOSEV_EXTERN_INT_0           0x00000001
176
177
178/*
179 *  EDAC Registers
180 */
181
182#define MONGOOSEV_EDAC_ERROR_ADDRESS_REGISTER       0xFFFE0190
183#define MONGOOSEV_EDAC_PARITY_TEST_MODE_REGISTER    0xFFFE0194
184
185/*
186 *  MAVN Registers
187 */
188
189#define MONGOOSEV_MAVN_TEST_REGISTER               0xFFFE01B4
190#define MONGOOSEV_MAVN_ACCESS_PRIVILEGE_REGISTER   0xFFFE01B8
191#define MONGOOSEV_MAVN_ACCESS_VIOLATION_REGISTER   0xFFFE01BC
192#define MONGOOSEV_MAVN_RANGE_0_REGISTER            0xFFFE01C0
193#define MONGOOSEV_MAVN_RANGE_1_REGISTER            0xFFFE01C4
194#define MONGOOSEV_MAVN_RANGE_2_REGISTER            0xFFFE01C8
195#define MONGOOSEV_MAVN_RANGE_3_REGISTER            0xFFFE01CC
196#define MONGOOSEV_MAVN_RANGE_4_REGISTER            0xFFFE01D0
197#define MONGOOSEV_MAVN_RANGE_5_REGISTER            0xFFFE01D4
198#define MONGOOSEV_MAVN_RANGE_6_REGISTER            0xFFFE01D8
199#define MONGOOSEV_MAVN_RANGE_7_REGISTER            0xFFFE01DC
200
201/*
202 *  Timer Base Addresses, Offsets, and Values
203 */
204
205#define MONGOOSEV_TIMER1_BASE    0xFFFE0000
206#define MONGOOSEV_TIMER2_BASE    0xFFFE0008
207
208#define MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER 0
209#define MONGOOSEV_TIMER_CONTROL_REGISTER         4
210
211/* Timer Control Register Constants */
212#define MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE    0x04
213#define MONGOOSEV_TIMER_CONTROL_INTERRUPT_ENABLE  0x02
214#define MONGOOSEV_TIMER_CONTROL_TIMEOUT           0x01
215
216/*
217 *  UART Base Addresses and Offsets
218 *
219 *  Many bits in the peripheral command register are UART related
220 *  and the bits are defined there.
221 */
222
223#define MONGOOSEV_UART0_BASE   0xFFFE01E8
224#define MONGOOSEV_UART1_BASE   0xFFFE01F4
225
226#define MONGOOSEV_RX_BUFFER    0
227#define MONGOOSEV_TX_BUFFER    4
228#define MONGOOSEV_BAUD_RATE    8
229
230/*
231 *  Interrupt Vector Numbers
232 *
233 *  NOTE: IRQ INT5 is logical or of peripheral cause register
234 *        per p. 5-22 of Mongoose-V manual.
235 */
236
237#define MONGOOSEV_IRQ_INT0                    0
238#define MONGOOSEV_IRQ_TIMER1                  MONGOOSEV_IRQ_INT0
239#define MONGOOSEV_IRQ_INT1                    1
240#define MONGOOSEV_IRQ_TIMER2                  MONGOOSEV_IRQ_INT1
241#define MONGOOSEV_IRQ_INT2                    2
242#define MONGOOSEV_IRQ_INT4                    3
243/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
244#define MONGOOSEV_IRQ_PERIPHERAL_BASE         4
245#define MONGOOSEV_IRQ_XINT0                   4
246#define MONGOOSEV_IRQ_XINT1                   5
247#define MONGOOSEV_IRQ_XINT2                   6
248#define MONGOOSEV_IRQ_XINT3                   7
249#define MONGOOSEV_IRQ_XINT4                   8
250#define MONGOOSEV_IRQ_XINT5                   9
251#define MONGOOSEV_IRQ_XINT6                  10
252#define MONGOOSEV_IRQ_XINT7                  11
253#define MONGOOSEV_IRQ_XINT8                  12
254#define MONGOOSEV_IRQ_XINT9                  13
255#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION  14
256#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION 15
257#define MONGOOSEV_IRQ_RESERVED_BIT_12        16
258#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR   17
259#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR 18
260#define MONGOOSEV_IRQ_UART1_TX_EMPTY         19
261#define MONGOOSEV_IRQ_UART1_TX_READY         20
262#define MONGOOSEV_IRQ_UART1_RX_READY         21
263#define MONGOOSEV_IRQ_RESERVED_BIT_18        22
264#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR   23
265#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR 24
266#define MONGOOSEV_IRQ_UART0_TX_EMPTY         25
267#define MONGOOSEV_IRQ_UART0_TX_READY         26
268#define MONGOOSEV_IRQ_UART0_RX_READY         27
269#define MONGOOSEV_IRQ_RESERVED_24            28
270#define MONGOOSEV_IRQ_RESERVED_25            29
271#define MONGOOSEV_IRQ_RESERVED_26            30
272#define MONGOOSEV_IRQ_RESERVED_27            31
273#define MONGOOSEV_IRQ_RESERVED_28            32
274#define MONGOOSEV_IRQ_RESERVED_29            33
275#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR    34
276#define MONGOOSEV_IRQ_CORRECTABLE_ERROR      35
277
278#define MONGOOSEV_IRQ_SOFTWARE_1             36
279#define MONGOOSEV_IRQ_SOFTWARE_2             37
280
281#endif
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