source: rtems/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h @ 7c05d28

4.104.114.84.95
Last change on this file since 7c05d28 was 7c05d28, checked in by Joel Sherrill <joel.sherrill@…>, on May 24, 2001 at 7:54:22 PM

2000-05-24 Joel Sherrill <joel@…>

  • mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, r46xx/vectorisrs/vectorisrs.c, tx39/vectorisrs/vectorisrs.c, tx39/include/tx3904.h: All exceptions were given low numbers and thus can be now be installed and processed in a uniform manner just like interrupts. Variances between various MIPS ISA levels are not accounted for at this time.
  • mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/maxvectors.c, r46xx/vectorisrs/Makefile.am, r46xx/vectorisrs/maxvectors.c, tx39/vectorisrs/Makefile.am, tx39/vectorisrs/maxvectors.c, shared/interrupts/maxvectors.c, shared/interrupts/Makefile.am: Split the shared maxvectors.c into a variety of CPU model specific versions to simplify the build process and reduce depdencies. Deleted shared/interrupts/maxvectors.c and created various CPU model versions.
  • Property mode set to 100644
File size: 14.1 KB
Line 
1/*
2 *  MIPS Mongoose-V specific information
3 *
4 *  COPYRIGHT (c) 1989-2001.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#ifndef __MONGOOSEV_h
15#define __MONGOOSEV_h
16
17/*
18 *  Macros to assist in accessing memory mapped Mongoose registers
19 */
20
21
22#define MONGOOSEV_READ( _base ) \
23  ( *((volatile unsigned32 *)(_base)) )
24
25#define MONGOOSEV_WRITE( _base, _value ) \
26  ( *((volatile unsigned32 *)(_base)) = (_value) )
27
28#define MONGOOSEV_READ_REGISTER( _base, _register ) \
29  ( *((volatile unsigned32 *)((_base) + (_register))) )
30
31#define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \
32  ( *((volatile unsigned32 *)((_base) + (_register))) = (_value) )
33
34
35
36
37
38/*
39 * Macros to read/write the Mongoose FPU control register.
40 */
41
42
43
44
45/*
46 *  BIU and DRAM Registers
47 */
48
49#define MONGOOSEV_BIU_CACHE_CONFIGURATION_REGISTER       0xFFFE0130
50#define MONGOOSEV_DRAM_CONFIGURATION_REGISTER            0xFFFE0120
51#define MONGOOSEV_REFRESH_TIMER_INITIAL_COUNTER_REGISTER 0xFFFE0010
52#define MONGOOSEV_WAIT_STATE_CONFIGURATION_REGISTER_BASE 0xFFFE0100
53
54/*
55 *  Peripheral Function Addresses
56 *
57 *  NOTE: Status and Interrupt Cause use the same bits
58 */
59
60#define MONGOOSEV_PERIPHERAL_COMMAND_REGISTER                   0xFFFE0180
61#define MONGOOSEV_PERIPHERAL_STATUS_REGISTER                    0xFFFE0184
62#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER  0xFFFE0188
63#define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER   0xFFFE018C
64
65#define MONGOOSEV_WATCHDOG                      0xBE000000
66
67/* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */
68#define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS     0x0001
69#define MONGOOSEV_UART_CMD_LOOPBACK_CTSN        0x0002
70#define MONGOOSEV_UART_CMD_LOOPBACK_RXTX        0x0004
71
72#define MONGOOSEV_UART_CMD_RX_ENABLE            0x001
73#define MONGOOSEV_UART_CMD_RX_DISABLE           0x000
74#define MONGOOSEV_UART_CMD_TX_ENABLE            0x002
75#define MONGOOSEV_UART_CMD_TX_DISABLE           0x000
76#define MONGOOSEV_UART_CMD_TX_READY             0x004
77#define MONGOOSEV_UART_CMD_PARITY_ENABLE        0x008
78#define MONGOOSEV_UART_CMD_PARITY_DISABLE       0x000
79#define MONGOOSEV_UART_CMD_PARITY_EVEN          0x010
80#define MONGOOSEV_UART_CMD_PARITY_ODD           0x000
81
82#define MONGOOSEV_UART0_CMD_SHIFT 5
83#define MONGOOSEV_UART1_CMD_SHIFT 11
84
85#define MONGOOSEV_UART_CMD_TX_ENABLE_0 \
86        (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
87#define MONGOOSEV_UART_CMD_RX_ENABLE_0 \
88        (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
89#define MONGOOSEV_UART_CMD_TX_READY_0 \
90        (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
91#define MONGOOSEV_UART_CMD_PARITY_ENABLE_0 \
92        (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
93#define MONGOOSEV_UART_CMD_PARITY_DISABLE_0 \
94        (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
95#define MONGOOSEV_UART_CMD_PARITY_EVEN_0 \
96        (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
97#define MONGOOSEV_UART_CMD_PARITY_ODD_0 \
98        (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
99
100#define MONGOOSEV_UART_CMD_TX_ENABLE_1 \
101        (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
102#define MONGOOSEV_UART_CMD_RX_ENABLE_1 \
103        (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
104#define MONGOOSEV_UART_CMD_TX_READY_1 \
105        (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT)
106#define MONGOOSEV_UART_CMD_PARITY_ENABLE_1 \
107        (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT)
108#define MONGOOSEV_UART_CMD_PARITY_DISABLE_1 \
109        (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT)
110#define MONGOOSEV_UART_CMD_PARITY_EVEN_1 \
111        (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT)
112#define MONGOOSEV_UART_CMD_PARITY_ODD_1 \
113        (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT)
114
115/* UART Bits in Peripheral Status and Interrupt Cause Register */
116#define MONGOOSEV_UART_RX_FRAME_ERROR              0x0001
117#define MONGOOSEV_UART_RX_OVERRUN_ERROR            0x0002
118#define MONGOOSEV_UART_TX_EMPTY                    0x0004
119#define MONGOOSEV_UART_TX_READY                    0x0008
120#define MONGOOSEV_UART_RX_READY                    0x0010
121
122#define MONGOOSEV_UART_ALL_RX_STATUS_BITS          0x0013
123#define MONGOOSEV_UART_ALL_STATUS_BITS             0x001F
124
125/*
126 *  The Peripheral Interrupt Status, Cause, and Mask registers have the
127 *  same bit assignments although some revisions of the document have
128 *  the Cause and Status registers incorrect. 
129 */
130
131#define MONGOOSEV_UART0_IRQ_SHIFT 11
132#define MONGOOSEV_UART1_IRQ_SHIFT 17
133
134#define MONGOOSEV_UART_FRAME_ERROR_1 \
135        (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
136#define MONGOOSEV_UART_RX_OVERRUN_ERROR_1 \
137        (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
138#define MONGOOSEV_UART_TX_EMPTY_1 \
139        (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
140#define MONGOOSEV_UART_TX_READY_1 \
141        (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
142#define MONGOOSEV_UART_RX_READY_1 \
143        (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
144
145#define MONGOOSEV_UART_FRAME_ERROR_0 \
146        (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
147#define MONGOOSEV_UART_RX_OVERRUN_ERROR_0 \
148        (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT)
149#define MONGOOSEV_UART_TX_EMPTY_0 \
150        (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT)
151#define MONGOOSEV_UART_TX_READY_0 \
152        (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
153#define MONGOOSEV_UART_RX_READY_0 \
154        (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT)
155
156/*
157 *  Bits in the Peripheral Interrupt Mask Register
158 */
159
160/*
161** Interrupt Status/Cause/Mask register bits - from 31 to 0
162*/
163#define MONGOOSEV_EDAC_SERR_BIT          0x80000000
164#define MONGOOSEV_EDAC_MERR_BIT          0x40000000
165#define MONGOOSEV_MAVN_WRITE_ACCESS      0x00800000
166#define MONGOOSEV_MAVN_READ_ACCESS       0x00400000
167/* 29 - 24 reserved */
168#define MONGOOSEV_UART_1_RX_READY        0x00200000
169#define MONGOOSEV_UART_1_TX_READY        0x00100000
170#define MONGOOSEV_UART_1_TX_EMPTY        0x00080000
171#define MONGOOSEV_UART_1_RX_OVERRUN      0x00040000
172#define MONGOOSEV_UART_1_FRAME_ERROR     0x00020000
173#define MONGOOSEV_RESERVED_16            0x00010000
174#define MONGOOSEV_UART_0_RX_READY        0x00008000
175#define MONGOOSEV_UART_0_TX_READY        0x00004000
176#define MONGOOSEV_UART_0_TX_EMPTY        0x00002000
177#define MONGOOSEV_UART_0_RX_OVERRUN      0x00001000
178#define MONGOOSEV_UART_0_FRAME_ERROR     0x00000800
179#define MONGOOSEV_RESERVED_10            0x00000400
180#define MONGOOSEV_EXTERN_INT_9           0x00000200
181#define MONGOOSEV_EXTERN_INT_8           0x00000100
182#define MONGOOSEV_EXTERN_INT_7           0x00000080
183#define MONGOOSEV_EXTERN_INT_6           0x00000040
184#define MONGOOSEV_EXTERN_INT_5           0x00000020
185#define MONGOOSEV_EXTERN_INT_4           0x00000010
186#define MONGOOSEV_EXTERN_INT_3           0x00000008
187#define MONGOOSEV_EXTERN_INT_2           0x00000004
188#define MONGOOSEV_EXTERN_INT_1           0x00000002
189#define MONGOOSEV_EXTERN_INT_0           0x00000001
190
191
192/*
193 *  EDAC Registers
194 */
195
196#define MONGOOSEV_EDAC_ERROR_ADDRESS_REGISTER       0xFFFE0190
197#define MONGOOSEV_EDAC_PARITY_TEST_MODE_REGISTER    0xFFFE0194
198
199/*
200 *  MAVN Registers
201 */
202
203#define MONGOOSEV_MAVN_TEST_REGISTER               0xFFFE01B4
204#define MONGOOSEV_MAVN_ACCESS_PRIVILEGE_REGISTER   0xFFFE01B8
205#define MONGOOSEV_MAVN_ACCESS_VIOLATION_REGISTER   0xFFFE01BC
206#define MONGOOSEV_MAVN_RANGE_0_REGISTER            0xFFFE01C0
207#define MONGOOSEV_MAVN_RANGE_1_REGISTER            0xFFFE01C4
208#define MONGOOSEV_MAVN_RANGE_2_REGISTER            0xFFFE01C8
209#define MONGOOSEV_MAVN_RANGE_3_REGISTER            0xFFFE01CC
210#define MONGOOSEV_MAVN_RANGE_4_REGISTER            0xFFFE01D0
211#define MONGOOSEV_MAVN_RANGE_5_REGISTER            0xFFFE01D4
212#define MONGOOSEV_MAVN_RANGE_6_REGISTER            0xFFFE01D8
213#define MONGOOSEV_MAVN_RANGE_7_REGISTER            0xFFFE01DC
214
215/*
216 *  Timer Base Addresses, Offsets, and Values
217 */
218
219#define MONGOOSEV_TIMER1_BASE    0xFFFE0000
220#define MONGOOSEV_TIMER2_BASE    0xFFFE0008
221
222#define MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER 0
223#define MONGOOSEV_TIMER_CONTROL_REGISTER         4
224
225/* Timer Control Register Constants */
226#define MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE    0x04
227#define MONGOOSEV_TIMER_CONTROL_INTERRUPT_ENABLE  0x02
228#define MONGOOSEV_TIMER_CONTROL_TIMEOUT           0x01
229
230/*
231 *  UART Base Addresses and Offsets
232 *
233 *  Many bits in the peripheral command register are UART related
234 *  and the bits are defined there.
235 */
236
237#define MONGOOSEV_UART0_BASE   0xFFFE01E8
238#define MONGOOSEV_UART1_BASE   0xFFFE01F4
239
240#define MONGOOSEV_RX_BUFFER    0
241#define MONGOOSEV_TX_BUFFER    4
242#define MONGOOSEV_BAUD_RATE    8
243
244/*
245 *  Interrupt Vector Numbers
246 *
247 *  NOTE: IRQ INT5 is logical or of peripheral cause register
248 *        per p. 5-22 of Mongoose-V manual.
249 */
250
251#define MONGOOSEV_IRQ_INT0                    MIPS_INTERRUPT_BASE+0
252#define MONGOOSEV_IRQ_TIMER1                  MONGOOSEV_IRQ_INT0
253#define MONGOOSEV_IRQ_INT1                    MIPS_INTERRUPT_BASE+1
254#define MONGOOSEV_IRQ_TIMER2                  MONGOOSEV_IRQ_INT1
255#define MONGOOSEV_IRQ_INT2                    MIPS_INTERRUPT_BASE+2
256#define MONGOOSEV_IRQ_INT3                    MIPS_INTERRUPT_BASE+3
257#define MONGOOSEV_IRQ_FPU                     MONGOOSEV_IRQ_INT3
258
259#define MONGOOSEV_IRQ_INT4                    MIPS_INTERRUPT_BASE+4
260
261/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
262#define MONGOOSEV_IRQ_PERIPHERAL_BASE         MIPS_INTERRUPT_BASE+5
263#define MONGOOSEV_IRQ_XINT0                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 0
264#define MONGOOSEV_IRQ_XINT1                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 1
265#define MONGOOSEV_IRQ_XINT2                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 2
266#define MONGOOSEV_IRQ_XINT3                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 3
267#define MONGOOSEV_IRQ_XINT4                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 4
268#define MONGOOSEV_IRQ_XINT5                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 5
269#define MONGOOSEV_IRQ_XINT6                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 6
270#define MONGOOSEV_IRQ_XINT7                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 7
271#define MONGOOSEV_IRQ_XINT8                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 8
272#define MONGOOSEV_IRQ_XINT9                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 9
273#define MONGOOSEV_IRQ_RESERVED_BIT_10        MONGOOSEV_IRQ_PERIPHERAL_BASE + 10
274#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR   MONGOOSEV_IRQ_PERIPHERAL_BASE + 11
275#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12
276#define MONGOOSEV_IRQ_UART0_TX_EMPTY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 13
277#define MONGOOSEV_IRQ_UART0_TX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 14
278#define MONGOOSEV_IRQ_UART0_RX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 15
279#define MONGOOSEV_IRQ_RESERVED_BIT_16        MONGOOSEV_IRQ_PERIPHERAL_BASE + 16
280#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR   MONGOOSEV_IRQ_PERIPHERAL_BASE + 17
281#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18
282#define MONGOOSEV_IRQ_UART1_TX_EMPTY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 19
283#define MONGOOSEV_IRQ_UART1_TX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 20
284#define MONGOOSEV_IRQ_UART1_RX_READY         MONGOOSEV_IRQ_PERIPHERAL_BASE + 21
285#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION  MONGOOSEV_IRQ_PERIPHERAL_BASE + 22
286#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23
287#define MONGOOSEV_IRQ_RESERVED_24            MONGOOSEV_IRQ_PERIPHERAL_BASE + 24
288#define MONGOOSEV_IRQ_RESERVED_25            MONGOOSEV_IRQ_PERIPHERAL_BASE + 25
289#define MONGOOSEV_IRQ_RESERVED_26            MONGOOSEV_IRQ_PERIPHERAL_BASE + 26
290#define MONGOOSEV_IRQ_RESERVED_27            MONGOOSEV_IRQ_PERIPHERAL_BASE + 27
291#define MONGOOSEV_IRQ_RESERVED_28            MONGOOSEV_IRQ_PERIPHERAL_BASE + 28
292#define MONGOOSEV_IRQ_RESERVED_29            MONGOOSEV_IRQ_PERIPHERAL_BASE + 29
293#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR    MONGOOSEV_IRQ_PERIPHERAL_BASE + 30
294#define MONGOOSEV_IRQ_CORRECTABLE_ERROR      MONGOOSEV_IRQ_PERIPHERAL_BASE + 31
295
296#define MONGOOSEV_IRQ_SOFTWARE_1             MIPS_INTERRUPT_BASE+37
297#define MONGOOSEV_IRQ_SOFTWARE_2             MIPS_INTERRUPT_BASE+38
298#define MONGOOSEV_MAXIMUM_VECTORS            MIPS_INTERRUPT_BASE+39
299
300
301/*
302 *  Status Register Bits
303 */
304
305#define SR_CUMASK       0xf0000000      /* coproc usable bits */
306#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
307#define SR_CU2          0x40000000      /* Coprocessor 2 usable */
308#define SR_CU1          0x20000000      /* Coprocessor 1 usable */
309#define SR_CU0          0x10000000      /* Coprocessor 0 usable */
310#define SR_BEV          0x00400000      /* use boot exception vectors */
311#define SR_TS           0x00200000      /* TLB shutdown */
312#define SR_PE           0x00100000      /* cache parity error */
313#define SR_CM           0x00080000      /* cache miss */
314#define SR_PZ           0x00040000      /* cache parity zero */
315#define SR_SWC          0x00020000      /* swap cache */
316#define SR_ISC          0x00010000      /* Isolate data cache */
317#define SR_IMASK        0x0000ff00      /* Interrupt mask */
318#define SR_IMASK8       0x00000000      /* mask level 8 */
319#define SR_IMASK7       0x00008000      /* mask level 7 */
320#define SR_IMASK6       0x0000c000      /* mask level 6 */
321#define SR_IMASK5       0x0000e000      /* mask level 5 */
322#define SR_IMASK4       0x0000f000      /* mask level 4 */
323#define SR_IMASK3       0x0000f800      /* mask level 3 */
324#define SR_IMASK2       0x0000fc00      /* mask level 2 */
325#define SR_IMASK1       0x0000fe00      /* mask level 1 */
326#define SR_IMASK0       0x0000ff00      /* mask level 0 */
327
328#define SR_IBIT8        0x00008000      /* bit level 8 */
329#define SR_IBIT7        0x00004000      /* bit level 7 */
330#define SR_IBIT6        0x00002000      /* bit level 6 */
331#define SR_IBIT5        0x00001000      /* bit level 5 */
332#define SR_IBIT4        0x00000800      /* bit level 4 */
333#define SR_IBIT3        0x00000400      /* bit level 3 */
334#define SR_IBIT2        0x00000200      /* bit level 2 */
335#define SR_IBIT1        0x00000100      /* bit level 1 */
336
337#define SR_KUO          0x00000020      /* old kernel/user, 0 => k, 1 => u */
338#define SR_IEO          0x00000010      /* old interrupt enable, 1 => enable */
339#define SR_KUP          0x00000008      /* prev kernel/user, 0 => k, 1 => u */
340#define SR_IEP          0x00000004      /* prev interrupt enable, 1 => enable */
341#define SR_KUC          0x00000002      /* cur kernel/user, 0 => k, 1 => u */
342#define SR_IEC          0x00000001      /* cur interrupt enable, 1 => enable */
343#define SR_KUMSK        (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC)
344
345#define SR_IMASKSHIFT   8
346
347#endif
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