1 | /* |
---|
2 | * MIPS Mongoose-V specific information |
---|
3 | * |
---|
4 | * COPYRIGHT (c) 1989-2001. |
---|
5 | * On-Line Applications Research Corporation (OAR). |
---|
6 | * |
---|
7 | * The license and distribution terms for this file may be |
---|
8 | * found in the file LICENSE in this distribution or at |
---|
9 | * http://www.OARcorp.com/rtems/license.html. |
---|
10 | * |
---|
11 | * $Id$ |
---|
12 | */ |
---|
13 | |
---|
14 | #ifndef __MONGOOSEV_h |
---|
15 | #define __MONGOOSEV_h |
---|
16 | |
---|
17 | /* |
---|
18 | * Macros to assist in accessing memory mapped Mongoose registers |
---|
19 | */ |
---|
20 | |
---|
21 | |
---|
22 | #define MONGOOSEV_READ( _base ) \ |
---|
23 | ( *((volatile unsigned32 *)(_base)) ) |
---|
24 | |
---|
25 | #define MONGOOSEV_WRITE( _base, _value ) \ |
---|
26 | ( *((volatile unsigned32 *)(_base)) = (_value) ) |
---|
27 | |
---|
28 | #define MONGOOSEV_READ_REGISTER( _base, _register ) \ |
---|
29 | ( *((volatile unsigned32 *)((_base) + (_register))) ) |
---|
30 | |
---|
31 | #define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \ |
---|
32 | ( *((volatile unsigned32 *)((_base) + (_register))) = (_value) ) |
---|
33 | |
---|
34 | |
---|
35 | |
---|
36 | |
---|
37 | |
---|
38 | /* |
---|
39 | * Macros to read/write the Mongoose FPU control register. |
---|
40 | */ |
---|
41 | |
---|
42 | |
---|
43 | |
---|
44 | |
---|
45 | /* |
---|
46 | * BIU and DRAM Registers |
---|
47 | */ |
---|
48 | |
---|
49 | #define MONGOOSEV_BIU_CACHE_CONFIGURATION_REGISTER 0xFFFE0130 |
---|
50 | #define MONGOOSEV_DRAM_CONFIGURATION_REGISTER 0xFFFE0120 |
---|
51 | #define MONGOOSEV_REFRESH_TIMER_INITIAL_COUNTER_REGISTER 0xFFFE0010 |
---|
52 | #define MONGOOSEV_WAIT_STATE_CONFIGURATION_REGISTER_BASE 0xFFFE0100 |
---|
53 | |
---|
54 | /* |
---|
55 | * Peripheral Function Addresses |
---|
56 | * |
---|
57 | * NOTE: Status and Interrupt Cause use the same bits |
---|
58 | */ |
---|
59 | |
---|
60 | #define MONGOOSEV_PERIPHERAL_COMMAND_REGISTER 0xFFFE0180 |
---|
61 | #define MONGOOSEV_PERIPHERAL_STATUS_REGISTER 0xFFFE0184 |
---|
62 | #define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER 0xFFFE0188 |
---|
63 | #define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER 0xFFFE018C |
---|
64 | |
---|
65 | #define MONGOOSEV_WATCHDOG 0xBE000000 |
---|
66 | |
---|
67 | /* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */ |
---|
68 | #define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS 0x0001 |
---|
69 | #define MONGOOSEV_UART_CMD_LOOPBACK_CTSN 0x0002 |
---|
70 | #define MONGOOSEV_UART_CMD_LOOPBACK_RXTX 0x0004 |
---|
71 | |
---|
72 | #define MONGOOSEV_UART_CMD_RX_ENABLE 0x001 |
---|
73 | #define MONGOOSEV_UART_CMD_RX_DISABLE 0x000 |
---|
74 | #define MONGOOSEV_UART_CMD_TX_ENABLE 0x002 |
---|
75 | #define MONGOOSEV_UART_CMD_TX_DISABLE 0x000 |
---|
76 | #define MONGOOSEV_UART_CMD_TX_READY 0x004 |
---|
77 | #define MONGOOSEV_UART_CMD_PARITY_ENABLE 0x008 |
---|
78 | #define MONGOOSEV_UART_CMD_PARITY_DISABLE 0x000 |
---|
79 | #define MONGOOSEV_UART_CMD_PARITY_EVEN 0x010 |
---|
80 | #define MONGOOSEV_UART_CMD_PARITY_ODD 0x000 |
---|
81 | |
---|
82 | #define MONGOOSEV_UART0_CMD_SHIFT 5 |
---|
83 | #define MONGOOSEV_UART1_CMD_SHIFT 11 |
---|
84 | |
---|
85 | #define MONGOOSEV_UART_CMD_TX_ENABLE_0 \ |
---|
86 | (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
---|
87 | #define MONGOOSEV_UART_CMD_RX_ENABLE_0 \ |
---|
88 | (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
---|
89 | #define MONGOOSEV_UART_CMD_TX_READY_0 \ |
---|
90 | (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT) |
---|
91 | #define MONGOOSEV_UART_CMD_PARITY_ENABLE_0 \ |
---|
92 | (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
---|
93 | #define MONGOOSEV_UART_CMD_PARITY_DISABLE_0 \ |
---|
94 | (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT) |
---|
95 | #define MONGOOSEV_UART_CMD_PARITY_EVEN_0 \ |
---|
96 | (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT) |
---|
97 | #define MONGOOSEV_UART_CMD_PARITY_ODD_0 \ |
---|
98 | (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT) |
---|
99 | |
---|
100 | #define MONGOOSEV_UART_CMD_TX_ENABLE_1 \ |
---|
101 | (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART1_CMD_SHIFT) |
---|
102 | #define MONGOOSEV_UART_CMD_RX_ENABLE_1 \ |
---|
103 | (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART1_CMD_SHIFT) |
---|
104 | #define MONGOOSEV_UART_CMD_TX_READY_1 \ |
---|
105 | (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART1_CMD_SHIFT) |
---|
106 | #define MONGOOSEV_UART_CMD_PARITY_ENABLE_1 \ |
---|
107 | (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART1_CMD_SHIFT) |
---|
108 | #define MONGOOSEV_UART_CMD_PARITY_DISABLE_1 \ |
---|
109 | (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART1_CMD_SHIFT) |
---|
110 | #define MONGOOSEV_UART_CMD_PARITY_EVEN_1 \ |
---|
111 | (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART1_CMD_SHIFT) |
---|
112 | #define MONGOOSEV_UART_CMD_PARITY_ODD_1 \ |
---|
113 | (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART1_CMD_SHIFT) |
---|
114 | |
---|
115 | /* UART Bits in Peripheral Status and Interrupt Cause Register */ |
---|
116 | #define MONGOOSEV_UART_RX_FRAME_ERROR 0x0001 |
---|
117 | #define MONGOOSEV_UART_RX_OVERRUN_ERROR 0x0002 |
---|
118 | #define MONGOOSEV_UART_TX_EMPTY 0x0004 |
---|
119 | #define MONGOOSEV_UART_TX_READY 0x0008 |
---|
120 | #define MONGOOSEV_UART_RX_READY 0x0010 |
---|
121 | |
---|
122 | #define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013 |
---|
123 | #define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F |
---|
124 | |
---|
125 | /* |
---|
126 | * The Peripheral Interrupt Status, Cause, and Mask registers have the |
---|
127 | * same bit assignments although some revisions of the document have |
---|
128 | * the Cause and Status registers incorrect. |
---|
129 | */ |
---|
130 | |
---|
131 | #define MONGOOSEV_UART0_IRQ_SHIFT 11 |
---|
132 | #define MONGOOSEV_UART1_IRQ_SHIFT 17 |
---|
133 | |
---|
134 | #define MONGOOSEV_UART_FRAME_ERROR_0 \ |
---|
135 | (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART0_IRQ_SHIFT) |
---|
136 | #define MONGOOSEV_UART_RX_OVERRUN_ERROR_0 \ |
---|
137 | (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART0_IRQ_SHIFT) |
---|
138 | #define MONGOOSEV_UART_TX_EMPTY_0 \ |
---|
139 | (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART0_IRQ_SHIFT) |
---|
140 | #define MONGOOSEV_UART_TX_READY_0 \ |
---|
141 | (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART0_IRQ_SHIFT) |
---|
142 | #define MONGOOSEV_UART_RX_READY_0 \ |
---|
143 | (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART0_IRQ_SHIFT) |
---|
144 | |
---|
145 | #define MONGOOSEV_UART_FRAME_ERROR_1 \ |
---|
146 | (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT) |
---|
147 | #define MONGOOSEV_UART_RX_OVERRUN_ERROR_1 \ |
---|
148 | (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT) |
---|
149 | #define MONGOOSEV_UART_TX_EMPTY_1 \ |
---|
150 | (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT) |
---|
151 | #define MONGOOSEV_UART_TX_READY_1 \ |
---|
152 | (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT) |
---|
153 | #define MONGOOSEV_UART_RX_READY_1 \ |
---|
154 | (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT) |
---|
155 | |
---|
156 | /* |
---|
157 | * Bits in the Peripheral Interrupt Mask Register |
---|
158 | */ |
---|
159 | |
---|
160 | /* |
---|
161 | ** Interrupt Status/Cause/Mask register bits - from 31 to 0 |
---|
162 | */ |
---|
163 | #define MONGOOSEV_EDAC_SERR_BIT 0x80000000 |
---|
164 | #define MONGOOSEV_EDAC_MERR_BIT 0x40000000 |
---|
165 | /* 29 - 24 reserved */ |
---|
166 | #define MONGOOSEV_MAVN_WRITE_ACCESS 0x00800000 |
---|
167 | #define MONGOOSEV_MAVN_READ_ACCESS 0x00400000 |
---|
168 | #define MONGOOSEV_UART_1_RX_READY 0x00200000 |
---|
169 | #define MONGOOSEV_UART_1_TX_READY 0x00100000 |
---|
170 | #define MONGOOSEV_UART_1_TX_EMPTY 0x00080000 |
---|
171 | #define MONGOOSEV_UART_1_RX_OVERRUN 0x00040000 |
---|
172 | #define MONGOOSEV_UART_1_FRAME_ERROR 0x00020000 |
---|
173 | #define MONGOOSEV_RESERVED_16 0x00010000 |
---|
174 | #define MONGOOSEV_UART_0_RX_READY 0x00008000 |
---|
175 | #define MONGOOSEV_UART_0_TX_READY 0x00004000 |
---|
176 | #define MONGOOSEV_UART_0_TX_EMPTY 0x00002000 |
---|
177 | #define MONGOOSEV_UART_0_RX_OVERRUN 0x00001000 |
---|
178 | #define MONGOOSEV_UART_0_FRAME_ERROR 0x00000800 |
---|
179 | #define MONGOOSEV_RESERVED_10 0x00000400 |
---|
180 | #define MONGOOSEV_EXTERN_INT_9 0x00000200 |
---|
181 | #define MONGOOSEV_EXTERN_INT_8 0x00000100 |
---|
182 | #define MONGOOSEV_EXTERN_INT_7 0x00000080 |
---|
183 | #define MONGOOSEV_EXTERN_INT_6 0x00000040 |
---|
184 | #define MONGOOSEV_EXTERN_INT_5 0x00000020 |
---|
185 | #define MONGOOSEV_EXTERN_INT_4 0x00000010 |
---|
186 | #define MONGOOSEV_EXTERN_INT_3 0x00000008 |
---|
187 | #define MONGOOSEV_EXTERN_INT_2 0x00000004 |
---|
188 | #define MONGOOSEV_EXTERN_INT_1 0x00000002 |
---|
189 | #define MONGOOSEV_EXTERN_INT_0 0x00000001 |
---|
190 | |
---|
191 | |
---|
192 | /* |
---|
193 | ** Peripheral Command bits (non-uart, those are defined above) |
---|
194 | */ |
---|
195 | #define MONGOOSEV_COMMAND_ENABLE_EDAC MONGOOSEV_EDAC_SERR_BIT |
---|
196 | #define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT |
---|
197 | |
---|
198 | |
---|
199 | |
---|
200 | /* |
---|
201 | * EDAC Registers |
---|
202 | */ |
---|
203 | |
---|
204 | #define MONGOOSEV_EDAC_ERROR_ADDRESS_REGISTER 0xFFFE0190 |
---|
205 | #define MONGOOSEV_EDAC_PARITY_TEST_MODE_REGISTER 0xFFFE0194 |
---|
206 | |
---|
207 | /* |
---|
208 | * MAVN Registers |
---|
209 | */ |
---|
210 | |
---|
211 | #define MONGOOSEV_MAVN_TEST_REGISTER 0xFFFE01B4 |
---|
212 | #define MONGOOSEV_MAVN_ACCESS_PRIVILEGE_REGISTER 0xFFFE01B8 |
---|
213 | #define MONGOOSEV_MAVN_ACCESS_VIOLATION_REGISTER 0xFFFE01BC |
---|
214 | #define MONGOOSEV_MAVN_RANGE_0_REGISTER 0xFFFE01C0 |
---|
215 | #define MONGOOSEV_MAVN_RANGE_1_REGISTER 0xFFFE01C4 |
---|
216 | #define MONGOOSEV_MAVN_RANGE_2_REGISTER 0xFFFE01C8 |
---|
217 | #define MONGOOSEV_MAVN_RANGE_3_REGISTER 0xFFFE01CC |
---|
218 | #define MONGOOSEV_MAVN_RANGE_4_REGISTER 0xFFFE01D0 |
---|
219 | #define MONGOOSEV_MAVN_RANGE_5_REGISTER 0xFFFE01D4 |
---|
220 | #define MONGOOSEV_MAVN_RANGE_6_REGISTER 0xFFFE01D8 |
---|
221 | #define MONGOOSEV_MAVN_RANGE_7_REGISTER 0xFFFE01DC |
---|
222 | |
---|
223 | /* |
---|
224 | * Timer Base Addresses, Offsets, and Values |
---|
225 | */ |
---|
226 | |
---|
227 | #define MONGOOSEV_TIMER1_BASE 0xFFFE0000 |
---|
228 | #define MONGOOSEV_TIMER2_BASE 0xFFFE0008 |
---|
229 | |
---|
230 | #define MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER 0 |
---|
231 | #define MONGOOSEV_TIMER_CONTROL_REGISTER 4 |
---|
232 | |
---|
233 | /* Timer Control Register Constants */ |
---|
234 | #define MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE 0x04 |
---|
235 | #define MONGOOSEV_TIMER_CONTROL_INTERRUPT_ENABLE 0x02 |
---|
236 | #define MONGOOSEV_TIMER_CONTROL_TIMEOUT 0x01 |
---|
237 | |
---|
238 | /* |
---|
239 | * UART Base Addresses and Offsets |
---|
240 | * |
---|
241 | * Many bits in the peripheral command register are UART related |
---|
242 | * and the bits are defined there. |
---|
243 | */ |
---|
244 | |
---|
245 | #define MONGOOSEV_UART0_BASE 0xFFFE01E8 |
---|
246 | #define MONGOOSEV_UART1_BASE 0xFFFE01F4 |
---|
247 | |
---|
248 | #define MONGOOSEV_RX_BUFFER 0 |
---|
249 | #define MONGOOSEV_TX_BUFFER 4 |
---|
250 | #define MONGOOSEV_BAUD_RATE 8 |
---|
251 | |
---|
252 | /* |
---|
253 | * Interrupt Vector Numbers |
---|
254 | * |
---|
255 | * NOTE: IRQ INT5 is logical or of peripheral cause register |
---|
256 | * per p. 5-22 of Mongoose-V manual. |
---|
257 | */ |
---|
258 | |
---|
259 | #define MONGOOSEV_IRQ_INT0 MIPS_INTERRUPT_BASE+0 |
---|
260 | #define MONGOOSEV_IRQ_TIMER1 MONGOOSEV_IRQ_INT0 |
---|
261 | #define MONGOOSEV_IRQ_INT1 MIPS_INTERRUPT_BASE+1 |
---|
262 | #define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1 |
---|
263 | #define MONGOOSEV_IRQ_INT2 MIPS_INTERRUPT_BASE+2 |
---|
264 | #define MONGOOSEV_IRQ_INT3 MIPS_INTERRUPT_BASE+3 |
---|
265 | #define MONGOOSEV_IRQ_FPU MONGOOSEV_IRQ_INT3 |
---|
266 | |
---|
267 | #define MONGOOSEV_IRQ_INT4 MIPS_INTERRUPT_BASE+4 |
---|
268 | |
---|
269 | /* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */ |
---|
270 | #define MONGOOSEV_IRQ_PERIPHERAL_BASE MIPS_INTERRUPT_BASE+5 |
---|
271 | #define MONGOOSEV_IRQ_XINT0 MONGOOSEV_IRQ_PERIPHERAL_BASE + 0 |
---|
272 | #define MONGOOSEV_IRQ_XINT1 MONGOOSEV_IRQ_PERIPHERAL_BASE + 1 |
---|
273 | #define MONGOOSEV_IRQ_XINT2 MONGOOSEV_IRQ_PERIPHERAL_BASE + 2 |
---|
274 | #define MONGOOSEV_IRQ_XINT3 MONGOOSEV_IRQ_PERIPHERAL_BASE + 3 |
---|
275 | #define MONGOOSEV_IRQ_XINT4 MONGOOSEV_IRQ_PERIPHERAL_BASE + 4 |
---|
276 | #define MONGOOSEV_IRQ_XINT5 MONGOOSEV_IRQ_PERIPHERAL_BASE + 5 |
---|
277 | #define MONGOOSEV_IRQ_XINT6 MONGOOSEV_IRQ_PERIPHERAL_BASE + 6 |
---|
278 | #define MONGOOSEV_IRQ_XINT7 MONGOOSEV_IRQ_PERIPHERAL_BASE + 7 |
---|
279 | #define MONGOOSEV_IRQ_XINT8 MONGOOSEV_IRQ_PERIPHERAL_BASE + 8 |
---|
280 | #define MONGOOSEV_IRQ_XINT9 MONGOOSEV_IRQ_PERIPHERAL_BASE + 9 |
---|
281 | #define MONGOOSEV_IRQ_RESERVED_BIT_10 MONGOOSEV_IRQ_PERIPHERAL_BASE + 10 |
---|
282 | #define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 11 |
---|
283 | #define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12 |
---|
284 | #define MONGOOSEV_IRQ_UART0_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 13 |
---|
285 | #define MONGOOSEV_IRQ_UART0_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 14 |
---|
286 | #define MONGOOSEV_IRQ_UART0_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 15 |
---|
287 | #define MONGOOSEV_IRQ_RESERVED_BIT_16 MONGOOSEV_IRQ_PERIPHERAL_BASE + 16 |
---|
288 | #define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 17 |
---|
289 | #define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18 |
---|
290 | #define MONGOOSEV_IRQ_UART1_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 19 |
---|
291 | #define MONGOOSEV_IRQ_UART1_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 20 |
---|
292 | #define MONGOOSEV_IRQ_UART1_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 21 |
---|
293 | #define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 22 |
---|
294 | #define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23 |
---|
295 | #define MONGOOSEV_IRQ_RESERVED_24 MONGOOSEV_IRQ_PERIPHERAL_BASE + 24 |
---|
296 | #define MONGOOSEV_IRQ_RESERVED_25 MONGOOSEV_IRQ_PERIPHERAL_BASE + 25 |
---|
297 | #define MONGOOSEV_IRQ_RESERVED_26 MONGOOSEV_IRQ_PERIPHERAL_BASE + 26 |
---|
298 | #define MONGOOSEV_IRQ_RESERVED_27 MONGOOSEV_IRQ_PERIPHERAL_BASE + 27 |
---|
299 | #define MONGOOSEV_IRQ_RESERVED_28 MONGOOSEV_IRQ_PERIPHERAL_BASE + 28 |
---|
300 | #define MONGOOSEV_IRQ_RESERVED_29 MONGOOSEV_IRQ_PERIPHERAL_BASE + 29 |
---|
301 | #define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 30 |
---|
302 | #define MONGOOSEV_IRQ_CORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 31 |
---|
303 | |
---|
304 | #define MONGOOSEV_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+37 |
---|
305 | #define MONGOOSEV_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+38 |
---|
306 | #define MONGOOSEV_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+39 |
---|
307 | |
---|
308 | |
---|
309 | /* |
---|
310 | * Status Register Bits |
---|
311 | */ |
---|
312 | |
---|
313 | #define SR_CUMASK 0xf0000000 /* coproc usable bits */ |
---|
314 | #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ |
---|
315 | #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ |
---|
316 | #define SR_CU1 0x20000000 /* Coprocessor 1 usable */ |
---|
317 | #define SR_CU0 0x10000000 /* Coprocessor 0 usable */ |
---|
318 | #define SR_BEV 0x00400000 /* use boot exception vectors */ |
---|
319 | #define SR_TS 0x00200000 /* TLB shutdown */ |
---|
320 | #define SR_PE 0x00100000 /* cache parity error */ |
---|
321 | #define SR_CM 0x00080000 /* cache miss */ |
---|
322 | #define SR_PZ 0x00040000 /* cache parity zero */ |
---|
323 | #define SR_SWC 0x00020000 /* swap cache */ |
---|
324 | #define SR_ISC 0x00010000 /* Isolate data cache */ |
---|
325 | #define SR_IMASK 0x0000ff00 /* Interrupt mask */ |
---|
326 | #define SR_IMASK8 0x00000000 /* mask level 8 */ |
---|
327 | #define SR_IMASK7 0x00008000 /* mask level 7 */ |
---|
328 | #define SR_IMASK6 0x0000c000 /* mask level 6 */ |
---|
329 | #define SR_IMASK5 0x0000e000 /* mask level 5 */ |
---|
330 | #define SR_IMASK4 0x0000f000 /* mask level 4 */ |
---|
331 | #define SR_IMASK3 0x0000f800 /* mask level 3 */ |
---|
332 | #define SR_IMASK2 0x0000fc00 /* mask level 2 */ |
---|
333 | #define SR_IMASK1 0x0000fe00 /* mask level 1 */ |
---|
334 | #define SR_IMASK0 0x0000ff00 /* mask level 0 */ |
---|
335 | |
---|
336 | #define SR_IBIT8 0x00008000 /* bit level 8 */ |
---|
337 | #define SR_IBIT7 0x00004000 /* bit level 7 */ |
---|
338 | #define SR_IBIT6 0x00002000 /* bit level 6 */ |
---|
339 | #define SR_IBIT5 0x00001000 /* bit level 5 */ |
---|
340 | #define SR_IBIT4 0x00000800 /* bit level 4 */ |
---|
341 | #define SR_IBIT3 0x00000400 /* bit level 3 */ |
---|
342 | #define SR_IBIT2 0x00000200 /* bit level 2 */ |
---|
343 | #define SR_IBIT1 0x00000100 /* bit level 1 */ |
---|
344 | |
---|
345 | #define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ |
---|
346 | #define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ |
---|
347 | #define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ |
---|
348 | #define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ |
---|
349 | #define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ |
---|
350 | #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ |
---|
351 | #define SR_KUMSK (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC) |
---|
352 | |
---|
353 | #define SR_IMASKSHIFT 8 |
---|
354 | |
---|
355 | #endif |
---|