[acdb6558] | 1 | /* |
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| 2 | * MIPS Mongoose-V specific information |
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| 3 | * |
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| 4 | * COPYRIGHT (c) 1989-2001. |
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| 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * http://www.OARcorp.com/rtems/license.html. |
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| 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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| 14 | #ifndef __MONGOOSEV_h |
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| 15 | #define __MONGOOSEV_h |
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| 16 | |
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| 17 | /* |
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| 18 | * Macros to assist in accessing memory mapped Mongoose registers |
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| 19 | */ |
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| 20 | |
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[2e7ed911] | 21 | |
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[acdb6558] | 22 | #define MONGOOSEV_READ( _base ) \ |
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[2e7ed911] | 23 | ( *((volatile unsigned32 *)(_base)) ) |
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[acdb6558] | 24 | |
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| 25 | #define MONGOOSEV_WRITE( _base, _value ) \ |
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[2e7ed911] | 26 | ( *((volatile unsigned32 *)(_base)) = (_value) ) |
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[acdb6558] | 27 | |
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| 28 | #define MONGOOSEV_READ_REGISTER( _base, _register ) \ |
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[2e7ed911] | 29 | ( *((volatile unsigned32 *)((_base) + (_register))) ) |
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[acdb6558] | 30 | |
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| 31 | #define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \ |
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[2e7ed911] | 32 | ( *((volatile unsigned32 *)((_base) + (_register))) = (_value) ) |
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| 33 | |
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| 34 | |
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| 35 | |
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| 36 | |
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| 37 | |
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| 38 | /* |
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| 39 | * Macros to read/write the Mongoose FPU control register. |
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| 40 | */ |
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| 41 | |
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| 42 | |
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| 43 | |
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[b85df34] | 44 | |
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[acdb6558] | 45 | /* |
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| 46 | * BIU and DRAM Registers |
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| 47 | */ |
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| 48 | |
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| 49 | #define MONGOOSEV_BIU_CACHE_CONFIGURATION_REGISTER 0xFFFE0130 |
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| 50 | #define MONGOOSEV_DRAM_CONFIGURATION_REGISTER 0xFFFE0120 |
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| 51 | #define MONGOOSEV_REFRESH_TIMER_INITIAL_COUNTER_REGISTER 0xFFFE0010 |
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| 52 | #define MONGOOSEV_WAIT_STATE_CONFIGURATION_REGISTER_BASE 0xFFFE0100 |
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| 53 | |
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| 54 | /* |
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| 55 | * Peripheral Function Addresses |
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| 56 | * |
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| 57 | * NOTE: Status and Interrupt Cause use the same bits |
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| 58 | */ |
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| 59 | |
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| 60 | #define MONGOOSEV_PERIPHERAL_COMMAND_REGISTER 0xFFFE0180 |
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| 61 | #define MONGOOSEV_PERIPHERAL_STATUS_REGISTER 0xFFFE0184 |
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| 62 | #define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER 0xFFFE0188 |
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| 63 | #define MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER 0xFFFE018C |
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| 64 | |
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[2e7ed911] | 65 | #define MONGOOSEV_WATCHDOG 0xBE000000 |
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[b85df34] | 66 | |
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[acdb6558] | 67 | /* UART Bits in Peripheral Command Register Bits (TX/RX tied together here) */ |
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[2e7ed911] | 68 | #define MONGOOSEV_UART_CMD_RESET_BOTH_PORTS 0x0001 |
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| 69 | #define MONGOOSEV_UART_CMD_LOOPBACK_CTSN 0x0002 |
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| 70 | #define MONGOOSEV_UART_CMD_LOOPBACK_RXTX 0x0004 |
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| 71 | |
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| 72 | #define MONGOOSEV_UART_CMD_RX_ENABLE 0x001 |
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| 73 | #define MONGOOSEV_UART_CMD_RX_DISABLE 0x000 |
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| 74 | #define MONGOOSEV_UART_CMD_TX_ENABLE 0x002 |
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| 75 | #define MONGOOSEV_UART_CMD_TX_DISABLE 0x000 |
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| 76 | #define MONGOOSEV_UART_CMD_TX_READY 0x004 |
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| 77 | #define MONGOOSEV_UART_CMD_PARITY_ENABLE 0x008 |
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| 78 | #define MONGOOSEV_UART_CMD_PARITY_DISABLE 0x000 |
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| 79 | #define MONGOOSEV_UART_CMD_PARITY_EVEN 0x010 |
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| 80 | #define MONGOOSEV_UART_CMD_PARITY_ODD 0x000 |
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[acdb6558] | 81 | |
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| 82 | #define MONGOOSEV_UART0_CMD_SHIFT 5 |
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| 83 | #define MONGOOSEV_UART1_CMD_SHIFT 11 |
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| 84 | |
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| 85 | #define MONGOOSEV_UART_CMD_TX_ENABLE_0 \ |
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| 86 | (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
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| 87 | #define MONGOOSEV_UART_CMD_RX_ENABLE_0 \ |
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| 88 | (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
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| 89 | #define MONGOOSEV_UART_CMD_TX_READY_0 \ |
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| 90 | (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT) |
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| 91 | #define MONGOOSEV_UART_CMD_PARITY_ENABLE_0 \ |
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| 92 | (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
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| 93 | #define MONGOOSEV_UART_CMD_PARITY_DISABLE_0 \ |
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| 94 | (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT) |
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| 95 | #define MONGOOSEV_UART_CMD_PARITY_EVEN_0 \ |
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| 96 | (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT) |
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| 97 | #define MONGOOSEV_UART_CMD_PARITY_ODD_0 \ |
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| 98 | (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT) |
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| 99 | |
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| 100 | #define MONGOOSEV_UART_CMD_TX_ENABLE_1 \ |
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| 101 | (MONGOOSEV_UART_CMD_TX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
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| 102 | #define MONGOOSEV_UART_CMD_RX_ENABLE_1 \ |
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| 103 | (MONGOOSEV_UART_CMD_RX_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
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| 104 | #define MONGOOSEV_UART_CMD_TX_READY_1 \ |
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| 105 | (MONGOOSEV_UART_CMD_TX_READY << MONGOOSEV_UART0_CMD_SHIFT) |
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| 106 | #define MONGOOSEV_UART_CMD_PARITY_ENABLE_1 \ |
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| 107 | (MONGOOSEV_UART_CMD_PARITY_ENABLE << MONGOOSEV_UART0_CMD_SHIFT) |
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| 108 | #define MONGOOSEV_UART_CMD_PARITY_DISABLE_1 \ |
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| 109 | (MONGOOSEV_UART_CMD_PARITY_DISABLE << MONGOOSEV_UART0_CMD_SHIFT) |
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| 110 | #define MONGOOSEV_UART_CMD_PARITY_EVEN_1 \ |
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| 111 | (MONGOOSEV_UART_CMD_PARITY_EVEN << MONGOOSEV_UART0_CMD_SHIFT) |
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| 112 | #define MONGOOSEV_UART_CMD_PARITY_ODD_1 \ |
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| 113 | (MONGOOSEV_UART_CMD_PARITY_ODD << MONGOOSEV_UART0_CMD_SHIFT) |
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| 114 | |
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| 115 | /* UART Bits in Peripheral Status and Interrupt Cause Register */ |
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| 116 | #define MONGOOSEV_UART_RX_FRAME_ERROR 0x0001 |
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| 117 | #define MONGOOSEV_UART_RX_OVERRUN_ERROR 0x0002 |
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| 118 | #define MONGOOSEV_UART_TX_EMPTY 0x0004 |
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| 119 | #define MONGOOSEV_UART_TX_READY 0x0008 |
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| 120 | #define MONGOOSEV_UART_RX_READY 0x0010 |
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| 121 | |
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[2e7ed911] | 122 | #define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013 |
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[acdb6558] | 123 | #define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F |
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| 124 | |
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| 125 | /* |
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| 126 | * The Peripheral Interrupt Status, Cause, and Mask registers have the |
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| 127 | * same bit assignments although some revisions of the document have |
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| 128 | * the Cause and Status registers incorrect. |
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| 129 | */ |
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| 130 | |
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| 131 | #define MONGOOSEV_UART0_IRQ_SHIFT 11 |
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| 132 | #define MONGOOSEV_UART1_IRQ_SHIFT 17 |
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| 133 | |
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| 134 | #define MONGOOSEV_UART_FRAME_ERROR_1 \ |
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| 135 | (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 136 | #define MONGOOSEV_UART_RX_OVERRUN_ERROR_1 \ |
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| 137 | (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 138 | #define MONGOOSEV_UART_TX_EMPTY_1 \ |
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| 139 | (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 140 | #define MONGOOSEV_UART_TX_READY_1 \ |
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| 141 | (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 142 | #define MONGOOSEV_UART_RX_READY_1 \ |
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| 143 | (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 144 | |
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| 145 | #define MONGOOSEV_UART_FRAME_ERROR_0 \ |
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| 146 | (MONGOOSEV_UART_FRAME_ERROR << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 147 | #define MONGOOSEV_UART_RX_OVERRUN_ERROR_0 \ |
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| 148 | (MONGOOSEV_UART_RX_OVERRUN_ERROR << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 149 | #define MONGOOSEV_UART_TX_EMPTY_0 \ |
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| 150 | (MONGOOSEV_UART_TX_EMPTY << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 151 | #define MONGOOSEV_UART_TX_READY_0 \ |
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| 152 | (MONGOOSEV_UART_TX_READY << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 153 | #define MONGOOSEV_UART_RX_READY_0 \ |
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| 154 | (MONGOOSEV_UART_RX_READY << MONGOOSEV_UART1_IRQ_SHIFT) |
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| 155 | |
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| 156 | /* |
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| 157 | * Bits in the Peripheral Interrupt Mask Register |
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| 158 | */ |
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| 159 | |
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| 160 | /* |
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| 161 | ** Interrupt Status/Cause/Mask register bits - from 31 to 0 |
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| 162 | */ |
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| 163 | #define MONGOOSEV_EDAC_SERR_BIT 0x80000000 |
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| 164 | #define MONGOOSEV_EDAC_MERR_BIT 0x40000000 |
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[2e7ed911] | 165 | #define MONGOOSEV_MAVN_WRITE_ACCESS 0x00800000 |
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| 166 | #define MONGOOSEV_MAVN_READ_ACCESS 0x00400000 |
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[acdb6558] | 167 | /* 29 - 24 reserved */ |
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| 168 | #define MONGOOSEV_UART_1_RX_READY 0x00200000 |
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| 169 | #define MONGOOSEV_UART_1_TX_READY 0x00100000 |
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| 170 | #define MONGOOSEV_UART_1_TX_EMPTY 0x00080000 |
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| 171 | #define MONGOOSEV_UART_1_RX_OVERRUN 0x00040000 |
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| 172 | #define MONGOOSEV_UART_1_FRAME_ERROR 0x00020000 |
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[2e7ed911] | 173 | #define MONGOOSEV_RESERVED_16 0x00010000 |
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| 174 | #define MONGOOSEV_UART_0_RX_READY 0x00008000 |
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| 175 | #define MONGOOSEV_UART_0_TX_READY 0x00004000 |
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| 176 | #define MONGOOSEV_UART_0_TX_EMPTY 0x00002000 |
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| 177 | #define MONGOOSEV_UART_0_RX_OVERRUN 0x00001000 |
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| 178 | #define MONGOOSEV_UART_0_FRAME_ERROR 0x00000800 |
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| 179 | #define MONGOOSEV_RESERVED_10 0x00000400 |
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[acdb6558] | 180 | #define MONGOOSEV_EXTERN_INT_9 0x00000200 |
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| 181 | #define MONGOOSEV_EXTERN_INT_8 0x00000100 |
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| 182 | #define MONGOOSEV_EXTERN_INT_7 0x00000080 |
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| 183 | #define MONGOOSEV_EXTERN_INT_6 0x00000040 |
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| 184 | #define MONGOOSEV_EXTERN_INT_5 0x00000020 |
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| 185 | #define MONGOOSEV_EXTERN_INT_4 0x00000010 |
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| 186 | #define MONGOOSEV_EXTERN_INT_3 0x00000008 |
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| 187 | #define MONGOOSEV_EXTERN_INT_2 0x00000004 |
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| 188 | #define MONGOOSEV_EXTERN_INT_1 0x00000002 |
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| 189 | #define MONGOOSEV_EXTERN_INT_0 0x00000001 |
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| 190 | |
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| 191 | |
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| 192 | /* |
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| 193 | * EDAC Registers |
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| 194 | */ |
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| 195 | |
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| 196 | #define MONGOOSEV_EDAC_ERROR_ADDRESS_REGISTER 0xFFFE0190 |
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| 197 | #define MONGOOSEV_EDAC_PARITY_TEST_MODE_REGISTER 0xFFFE0194 |
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| 198 | |
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| 199 | /* |
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| 200 | * MAVN Registers |
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| 201 | */ |
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| 202 | |
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| 203 | #define MONGOOSEV_MAVN_TEST_REGISTER 0xFFFE01B4 |
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| 204 | #define MONGOOSEV_MAVN_ACCESS_PRIVILEGE_REGISTER 0xFFFE01B8 |
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| 205 | #define MONGOOSEV_MAVN_ACCESS_VIOLATION_REGISTER 0xFFFE01BC |
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| 206 | #define MONGOOSEV_MAVN_RANGE_0_REGISTER 0xFFFE01C0 |
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| 207 | #define MONGOOSEV_MAVN_RANGE_1_REGISTER 0xFFFE01C4 |
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| 208 | #define MONGOOSEV_MAVN_RANGE_2_REGISTER 0xFFFE01C8 |
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| 209 | #define MONGOOSEV_MAVN_RANGE_3_REGISTER 0xFFFE01CC |
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| 210 | #define MONGOOSEV_MAVN_RANGE_4_REGISTER 0xFFFE01D0 |
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| 211 | #define MONGOOSEV_MAVN_RANGE_5_REGISTER 0xFFFE01D4 |
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| 212 | #define MONGOOSEV_MAVN_RANGE_6_REGISTER 0xFFFE01D8 |
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| 213 | #define MONGOOSEV_MAVN_RANGE_7_REGISTER 0xFFFE01DC |
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| 214 | |
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| 215 | /* |
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| 216 | * Timer Base Addresses, Offsets, and Values |
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| 217 | */ |
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| 218 | |
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| 219 | #define MONGOOSEV_TIMER1_BASE 0xFFFE0000 |
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| 220 | #define MONGOOSEV_TIMER2_BASE 0xFFFE0008 |
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| 221 | |
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| 222 | #define MONGOOSEV_TIMER_INITIAL_COUNTER_REGISTER 0 |
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| 223 | #define MONGOOSEV_TIMER_CONTROL_REGISTER 4 |
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| 224 | |
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| 225 | /* Timer Control Register Constants */ |
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| 226 | #define MONGOOSEV_TIMER_CONTROL_COUNTER_ENABLE 0x04 |
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| 227 | #define MONGOOSEV_TIMER_CONTROL_INTERRUPT_ENABLE 0x02 |
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| 228 | #define MONGOOSEV_TIMER_CONTROL_TIMEOUT 0x01 |
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| 229 | |
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| 230 | /* |
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| 231 | * UART Base Addresses and Offsets |
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| 232 | * |
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| 233 | * Many bits in the peripheral command register are UART related |
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| 234 | * and the bits are defined there. |
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| 235 | */ |
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| 236 | |
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| 237 | #define MONGOOSEV_UART0_BASE 0xFFFE01E8 |
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| 238 | #define MONGOOSEV_UART1_BASE 0xFFFE01F4 |
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| 239 | |
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| 240 | #define MONGOOSEV_RX_BUFFER 0 |
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| 241 | #define MONGOOSEV_TX_BUFFER 4 |
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| 242 | #define MONGOOSEV_BAUD_RATE 8 |
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| 243 | |
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| 244 | /* |
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| 245 | * Interrupt Vector Numbers |
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| 246 | * |
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| 247 | * NOTE: IRQ INT5 is logical or of peripheral cause register |
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| 248 | * per p. 5-22 of Mongoose-V manual. |
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| 249 | */ |
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| 250 | |
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| 251 | #define MONGOOSEV_IRQ_INT0 0 |
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| 252 | #define MONGOOSEV_IRQ_TIMER1 MONGOOSEV_IRQ_INT0 |
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| 253 | #define MONGOOSEV_IRQ_INT1 1 |
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| 254 | #define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1 |
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| 255 | #define MONGOOSEV_IRQ_INT2 2 |
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[2e7ed911] | 256 | #define MONGOOSEV_IRQ_INT3 3 |
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| 257 | #define MONGOOSEV_IRQ_FPU MONGOOSEV_IRQ_INT3 |
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| 258 | |
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| 259 | #define MONGOOSEV_IRQ_INT4 4 |
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| 260 | |
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[acdb6558] | 261 | /* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */ |
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[2e7ed911] | 262 | #define MONGOOSEV_IRQ_PERIPHERAL_BASE 5 |
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| 263 | #define MONGOOSEV_IRQ_XINT0 MONGOOSEV_IRQ_PERIPHERAL_BASE + 0 |
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| 264 | #define MONGOOSEV_IRQ_XINT1 MONGOOSEV_IRQ_PERIPHERAL_BASE + 1 |
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| 265 | #define MONGOOSEV_IRQ_XINT2 MONGOOSEV_IRQ_PERIPHERAL_BASE + 2 |
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| 266 | #define MONGOOSEV_IRQ_XINT3 MONGOOSEV_IRQ_PERIPHERAL_BASE + 3 |
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| 267 | #define MONGOOSEV_IRQ_XINT4 MONGOOSEV_IRQ_PERIPHERAL_BASE + 4 |
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| 268 | #define MONGOOSEV_IRQ_XINT5 MONGOOSEV_IRQ_PERIPHERAL_BASE + 5 |
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| 269 | #define MONGOOSEV_IRQ_XINT6 MONGOOSEV_IRQ_PERIPHERAL_BASE + 6 |
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| 270 | #define MONGOOSEV_IRQ_XINT7 MONGOOSEV_IRQ_PERIPHERAL_BASE + 7 |
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| 271 | #define MONGOOSEV_IRQ_XINT8 MONGOOSEV_IRQ_PERIPHERAL_BASE + 8 |
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| 272 | #define MONGOOSEV_IRQ_XINT9 MONGOOSEV_IRQ_PERIPHERAL_BASE + 9 |
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| 273 | #define MONGOOSEV_IRQ_RESERVED_BIT_10 MONGOOSEV_IRQ_PERIPHERAL_BASE + 10 |
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| 274 | #define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 11 |
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| 275 | #define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12 |
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| 276 | #define MONGOOSEV_IRQ_UART0_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 13 |
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| 277 | #define MONGOOSEV_IRQ_UART0_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 14 |
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| 278 | #define MONGOOSEV_IRQ_UART0_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 15 |
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| 279 | #define MONGOOSEV_IRQ_RESERVED_BIT_16 MONGOOSEV_IRQ_PERIPHERAL_BASE + 16 |
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| 280 | #define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 17 |
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| 281 | #define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18 |
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| 282 | #define MONGOOSEV_IRQ_UART1_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 19 |
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| 283 | #define MONGOOSEV_IRQ_UART1_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 20 |
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| 284 | #define MONGOOSEV_IRQ_UART1_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 21 |
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| 285 | #define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 22 |
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| 286 | #define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23 |
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| 287 | #define MONGOOSEV_IRQ_RESERVED_24 MONGOOSEV_IRQ_PERIPHERAL_BASE + 24 |
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| 288 | #define MONGOOSEV_IRQ_RESERVED_25 MONGOOSEV_IRQ_PERIPHERAL_BASE + 25 |
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| 289 | #define MONGOOSEV_IRQ_RESERVED_26 MONGOOSEV_IRQ_PERIPHERAL_BASE + 26 |
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| 290 | #define MONGOOSEV_IRQ_RESERVED_27 MONGOOSEV_IRQ_PERIPHERAL_BASE + 27 |
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| 291 | #define MONGOOSEV_IRQ_RESERVED_28 MONGOOSEV_IRQ_PERIPHERAL_BASE + 28 |
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| 292 | #define MONGOOSEV_IRQ_RESERVED_29 MONGOOSEV_IRQ_PERIPHERAL_BASE + 29 |
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| 293 | #define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 30 |
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| 294 | #define MONGOOSEV_IRQ_CORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 31 |
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| 295 | |
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| 296 | #define MONGOOSEV_IRQ_SOFTWARE_1 37 |
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| 297 | #define MONGOOSEV_IRQ_SOFTWARE_2 38 |
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| 298 | |
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| 299 | |
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| 300 | /* gdm, 5/14. Added exception vectoring to the ISR table- these |
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| 301 | entries are never called by the ISR servicing, only by the exception |
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| 302 | servicing routine. The ISR table is used because vector setup there |
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| 303 | is already supported. Please note exception routines are passed 2 |
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| 304 | parameters; one of the below vectors and a pointer to the exception's |
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| 305 | stack frame, the register layout of which is found in |
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| 306 | |
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| 307 | exec/score/cpu/mips/iregdef.h |
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| 308 | |
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| 309 | in conjunction with |
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| 310 | |
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| 311 | exec/score/cpu/mips/cpu_asm.S |
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| 312 | |
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| 313 | */ |
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| 314 | |
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| 315 | #define MONGOOSEV_EXCEPTION_BASE 39 |
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| 316 | |
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| 317 | #define MONGOOSEV_EXCEPTION_ADEL MONGOOSEV_EXCEPTION_BASE+0 |
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| 318 | #define MONGOOSEV_EXCEPTION_ADES MONGOOSEV_EXCEPTION_BASE+1 |
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| 319 | #define MONGOOSEV_EXCEPTION_IBE MONGOOSEV_EXCEPTION_BASE+2 |
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| 320 | #define MONGOOSEV_EXCEPTION_DBE MONGOOSEV_EXCEPTION_BASE+3 |
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| 321 | #define MONGOOSEV_EXCEPTION_SYSCALL MONGOOSEV_EXCEPTION_BASE+4 |
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| 322 | #define MONGOOSEV_EXCEPTION_BREAK MONGOOSEV_EXCEPTION_BASE+5 |
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| 323 | #define MONGOOSEV_EXCEPTION_RI MONGOOSEV_EXCEPTION_BASE+6 |
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| 324 | #define MONGOOSEV_EXCEPTION_CPU MONGOOSEV_EXCEPTION_BASE+7 |
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| 325 | #define MONGOOSEV_EXCEPTION_OVERFLOW MONGOOSEV_EXCEPTION_BASE+8 |
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| 326 | |
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| 327 | |
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| 328 | |
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| 329 | |
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| 330 | |
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| 331 | |
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| 332 | #define SR_CUMASK 0xf0000000 /* coproc usable bits */ |
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| 333 | #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ |
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| 334 | #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ |
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| 335 | #define SR_CU1 0x20000000 /* Coprocessor 1 usable */ |
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| 336 | #define SR_CU0 0x10000000 /* Coprocessor 0 usable */ |
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| 337 | #define SR_BEV 0x00400000 /* use boot exception vectors */ |
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| 338 | #define SR_TS 0x00200000 /* TLB shutdown */ |
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| 339 | #define SR_PE 0x00100000 /* cache parity error */ |
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| 340 | #define SR_CM 0x00080000 /* cache miss */ |
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| 341 | #define SR_PZ 0x00040000 /* cache parity zero */ |
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| 342 | #define SR_SWC 0x00020000 /* swap cache */ |
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| 343 | #define SR_ISC 0x00010000 /* Isolate data cache */ |
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| 344 | #define SR_IMASK 0x0000ff00 /* Interrupt mask */ |
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| 345 | #define SR_IMASK8 0x00000000 /* mask level 8 */ |
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| 346 | #define SR_IMASK7 0x00008000 /* mask level 7 */ |
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| 347 | #define SR_IMASK6 0x0000c000 /* mask level 6 */ |
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| 348 | #define SR_IMASK5 0x0000e000 /* mask level 5 */ |
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| 349 | #define SR_IMASK4 0x0000f000 /* mask level 4 */ |
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| 350 | #define SR_IMASK3 0x0000f800 /* mask level 3 */ |
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| 351 | #define SR_IMASK2 0x0000fc00 /* mask level 2 */ |
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| 352 | #define SR_IMASK1 0x0000fe00 /* mask level 1 */ |
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| 353 | #define SR_IMASK0 0x0000ff00 /* mask level 0 */ |
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| 354 | |
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| 355 | #define SR_IBIT8 0x00008000 /* bit level 8 */ |
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| 356 | #define SR_IBIT7 0x00004000 /* bit level 7 */ |
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| 357 | #define SR_IBIT6 0x00002000 /* bit level 6 */ |
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| 358 | #define SR_IBIT5 0x00001000 /* bit level 5 */ |
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| 359 | #define SR_IBIT4 0x00000800 /* bit level 4 */ |
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| 360 | #define SR_IBIT3 0x00000400 /* bit level 3 */ |
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| 361 | #define SR_IBIT2 0x00000200 /* bit level 2 */ |
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| 362 | #define SR_IBIT1 0x00000100 /* bit level 1 */ |
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| 363 | |
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| 364 | #define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ |
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| 365 | #define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ |
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| 366 | #define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ |
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| 367 | #define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ |
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| 368 | #define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ |
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| 369 | #define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ |
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| 370 | #define SR_KUMSK (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC) |
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| 371 | |
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| 372 | #define SR_IMASKSHIFT 8 |
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[acdb6558] | 373 | |
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| 374 | #endif |
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