1 | /* |
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2 | * |
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3 | * COPYRIGHT (c) 1989-1999. |
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4 | * On-Line Applications Research Corporation (OAR). |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.OARcorp.com/rtems/license.html. |
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9 | * |
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10 | * $Id$ |
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11 | */ |
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12 | |
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13 | #ifndef _MG5UART_H_ |
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14 | #define _MG5UART_H_ |
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15 | |
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16 | #ifdef __cplusplus |
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17 | extern "C" { |
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18 | #endif |
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19 | |
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20 | /* |
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21 | * This is the ASCII for "MG5U" which should be unique enough to |
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22 | * distinguish this type of serial device from others. |
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23 | */ |
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24 | |
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25 | #define SERIAL_MG5UART 0x474D5535 |
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26 | |
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27 | #define MG5UART_UART0 0 |
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28 | #define MG5UART_UART1 1 |
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29 | |
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30 | /* |
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31 | * These are just used in the interface between this driver and |
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32 | * the read/write register routines when accessing the first |
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33 | * control port. They are indices of registers from the bases. |
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34 | */ |
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35 | |
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36 | /* shared registers from peripheral base (i.e. from ulCtrlPort1) */ |
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37 | /* |
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38 | #define MG5UART_COMMAND_REGISTER 0 |
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39 | #define MG5UART_STATUS_REGISTER 1 |
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40 | #define MG5UART_INTERRUPT_CAUSE_REGISTER 2 |
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41 | #define MG5UART_INTERRUPT_MASK_REGISTER 3 |
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42 | */ |
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43 | |
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44 | #define MG5UART_COMMAND_REGISTER 0 |
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45 | #define MG5UART_STATUS_REGISTER 0x04 |
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46 | #define MG5UART_INTERRUPT_CAUSE_REGISTER 0x08 |
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47 | #define MG5UART_INTERRUPT_MASK_REGISTER 0x0C |
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48 | |
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49 | /* port specific registers from uart base (i.e. from ulCtrlPort2) */ |
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50 | #define MG5UART_RX_BUFFER 0 |
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51 | #define MG5UART_TX_BUFFER 4 |
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52 | #define MG5UART_BAUD_RATE 8 |
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53 | |
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54 | /* |
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55 | * Interrupt mask values |
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56 | */ |
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57 | |
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58 | #define MG5UART_ENABLE_ALL_EXCEPT_TX MONGOOSEV_UART_ALL_RX_STATUS_BITS |
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59 | |
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60 | /* all rx ints on, but only tx ready. no need to also int on tx empty */ |
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61 | #define MG5UART_ENABLE_ALL (MONGOOSEV_UART_ALL_STATUS_BITS & ~MONGOOSEV_UART_TX_EMPTY) |
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62 | |
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63 | #define MG5UART_DISABLE_ALL 0x0000 |
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64 | |
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65 | /* |
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66 | * Assume vectors are sequential. |
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67 | */ |
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68 | |
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69 | #define MG5UART_IRQ_RX_FRAME_ERROR 0 |
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70 | #define MG5UART_IRQ_RX_OVERRUN_ERROR 1 |
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71 | #define MG5UART_IRQ_TX_EMPTY 2 |
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72 | #define MG5UART_IRQ_TX_READY 3 |
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73 | #define MG5UART_IRQ_RX_READY 4 |
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74 | /* |
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75 | * Driver function table |
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76 | */ |
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77 | |
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78 | extern console_fns mg5uart_fns; |
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79 | extern console_fns mg5uart_fns_polled; |
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80 | |
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81 | /* |
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82 | * Default register access routines |
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83 | */ |
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84 | |
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85 | unsigned32 mg5uart_get_register( /* registers are on 32-bit boundaries */ |
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86 | unsigned32 ulCtrlPort, /* and accessed as word */ |
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87 | unsigned32 ucRegNum |
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88 | ); |
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89 | |
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90 | void mg5uart_set_register( |
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91 | unsigned32 ulCtrlPort, |
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92 | unsigned32 ucRegNum, |
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93 | unsigned32 ucData |
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94 | ); |
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95 | |
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96 | #ifdef __cplusplus |
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97 | } |
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98 | #endif |
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99 | |
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100 | #endif /* _MG5UART_H_ */ |
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