source: rtems/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h @ 948a069

Last change on this file since 948a069 was 2e7ed911, checked in by Joel Sherrill <joel.sherrill@…>, on May 22, 2001 at 11:20:14 PM

2001-05-22 Greg Menke <gregory.menke@…>

  • Assisted in design and debug by Joel Sherrill <joel@…>.
  • mongoosev/duart/mg5uart.c, mongoosev/duart/mg5uart.h, mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, shared/interrupts/maxvectors.c: Now works. Significant rework of exceptions and interrupt vectoring to clean things up.
  • shared/interrupts/vectorexceptions.c: Removed.
  • shared/interrupts/Makefile.am: Reflects above.
  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*
2 *
3 *  COPYRIGHT (c) 1989-1999.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.OARcorp.com/rtems/license.html.
9 *
10 *  $Id$
11 */
12
13#ifndef _MG5UART_H_
14#define _MG5UART_H_
15
16#ifdef __cplusplus
17extern "C" {
18#endif
19
20/*
21 *  This is the ASCII for "MG5U" which should be unique enough to
22 *  distinguish this type of serial device from others.
23 */
24
25#define SERIAL_MG5UART 0x474D5535
26
27#define MG5UART_UART0  0
28#define MG5UART_UART1  1
29
30/*
31 *  These are just used in the interface between this driver and
32 *  the read/write register routines when accessing the first
33 *  control port.  They are indices of registers from the bases.
34 */
35
36/* shared registers from peripheral base (i.e. from ulCtrlPort1) */
37/*
38#define MG5UART_COMMAND_REGISTER          0
39#define MG5UART_STATUS_REGISTER           1
40#define MG5UART_INTERRUPT_CAUSE_REGISTER  2
41#define MG5UART_INTERRUPT_MASK_REGISTER   3
42*/
43
44#define MG5UART_COMMAND_REGISTER          0
45#define MG5UART_STATUS_REGISTER           0x04
46#define MG5UART_INTERRUPT_CAUSE_REGISTER  0x08
47#define MG5UART_INTERRUPT_MASK_REGISTER   0x0C
48
49/* port specific registers from uart base (i.e. from ulCtrlPort2) */
50#define MG5UART_RX_BUFFER  0
51#define MG5UART_TX_BUFFER  4
52#define MG5UART_BAUD_RATE  8
53
54/*
55 *  Interrupt mask values
56 */
57
58#define MG5UART_ENABLE_ALL_EXCEPT_TX MONGOOSEV_UART_ALL_RX_STATUS_BITS
59
60/* all rx ints on, but only tx ready.  no need to also int on tx empty */
61#define MG5UART_ENABLE_ALL           (MONGOOSEV_UART_ALL_STATUS_BITS & ~MONGOOSEV_UART_TX_EMPTY)
62
63#define MG5UART_DISABLE_ALL          0x0000
64
65/*
66 *  Assume vectors are sequential.
67 */
68
69#define MG5UART_IRQ_RX_FRAME_ERROR   0
70#define MG5UART_IRQ_RX_OVERRUN_ERROR 1
71#define MG5UART_IRQ_TX_EMPTY         2
72#define MG5UART_IRQ_TX_READY         3
73#define MG5UART_IRQ_RX_READY         4
74/*
75 * Driver function table
76 */
77
78extern console_fns mg5uart_fns;
79extern console_fns mg5uart_fns_polled;
80
81/*
82 * Default register access routines
83 */
84
85unsigned32 mg5uart_get_register(    /* registers are on 32-bit boundaries */
86  unsigned32  ulCtrlPort,           /*   and accessed as word             */
87  unsigned32  ucRegNum
88);
89
90void  mg5uart_set_register(
91  unsigned32  ulCtrlPort,
92  unsigned32  ucRegNum,
93  unsigned32  ucData
94);
95
96#ifdef __cplusplus
97}
98#endif
99
100#endif /* _MG5UART_H_ */
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