source: rtems/c/src/lib/libcpu/mips/mongoosev/README @ 948a069

Last change on this file since 948a069 was 2835b3a5, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 1, 2002 at 3:15:02 PM

2001-02-01 Greg Menke <gregory.menke@…>

  • Lots of tinkering and tuning as part of improving interrupt latency and improving the per-task interrupt level control and FP mask handling. With these modifications interrupt latency was measured at a worst-case of 100us, average below 60 us on a 12 Mhz R3000 class CPU with 50 RTEMS tasks in the application.
  • mongoosev/README: Updated.
  • mongoosev/include/mongoose-v.h: Masks modified.
  • mongoosev/vectorisrs/vectorisrs.c: Significant overhaul to address software prioritization of interrupts. If a higher priority interrupt occurs while we are looking for new interrupts, we will reinitiate the scan of all interrupts.
  • shared/interrupts/vectorexceptions.c: Removed warning and deleted blank lines.
  • Property mode set to 100644
File size: 2.5 KB
2#  $Id$
5The Synova Mongoose-V is a radiation hardened derivative of the
6LSI 33K with on-CPU peripherals.
11Per-task floating point enable/disable is supported for both immediate
12and deferred FPU context swaps.
14Interrupt Levels are adapted reasonably well to the MIPS interrupt
15model. Bit 0 of the int level is a global enable/disable, corresponding
16to bit 0 of the processor's SR register.  Bits 1 thru 6 are configured
17as masks for the Int0 thru Int5 interrupts.  The 2 software interrupt
18bits are always enabled by default.  Each task maintains its own
19Interrupt Level setting, reconfiguring the SR register's interrupt bits
20whenever scheduled in.  The software ints, though not addressable via
21the various Interrupt Level functions, are maintained on a per-task
22basis, so if software manipulates them directly, things should behave as
23expected.  At the time of these udpates, the Interrupt Level was only 8
24bits, and completely supporting the global enable, software ints and the
25hardware ints would require 9 bits.  When more than 8 bits are
26available, there is no reason the software interrupts could not be added
27to the Interrupt Level.
29While supporting the Int0 thru Int5 bits in this way doesn't seem
30wonderfully useful, it does increase the level of compliance with the
31RTEMS spec.
33Interrupt Level 0 corresponds to interrupts globally enabled, software
34ints enabled and Int0 thru Int5 enabled.  If values other than 0 are
35supplied, they should be formulated to impose the desired bitmask.
36Interrupt priority is not a strong concept on this bsp, it is provided
37only by the order in which interrupts are checked. 
39If during the vectoring of an interrupt, others arrive, they will all be
40processed in accordance with their ordering in SR & the peripheral
41register.  For example, if while we're vectoring Int4, Int3 and Int5 are
42asserted, Int3 will be serviced before Int5.  The peripheral interrupts
43are individually vectored as a consequence of Int5 being asserted,
44however Int5 is not itself vectored.  Within the set of peripheral
45interrupts, bit 0 is vectored first, 31 is last.
47Interrupts are not nested for MIPS1 or MIPS3 processors, but are
48processed serially as possible.  On an unloaded 50 task RTEMS program,
49runnning on a 12mhz MIPS1 processor, worst-case latencies of 100us were
50observed, the average being down at 60us or below.
53These features are principally a consequence of fixes and tweaks to the
54MIPS1 and MIPS3 processor support, and should be equally effective on
55both levels of MIPS processors for any of their bsp's.
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