1 | # |
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2 | # $Id$ |
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3 | # |
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4 | |
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5 | The Synova Mongoose-V is a radiation hardened derivative of the |
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6 | LSI 33K with on-CPU peripherals. |
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7 | |
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8 | Status |
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9 | ====== |
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10 | |
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11 | Per-task floating point enable/disable is supported for both immediate |
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12 | and deferred FPU context swaps. |
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13 | |
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14 | Interrupt Levels are adapted reasonably well to the MIPS interrupt |
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15 | model. Bit 0 of the int level is a global enable/disable, corresponding |
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16 | to bit 0 of the processor's SR register. Bits 1 thru 6 are configured |
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17 | as masks for the Int0 thru Int5 interrupts. The 2 software interrupt |
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18 | bits are always enabled by default. Each task maintains its own |
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19 | Interrupt Level setting, reconfiguring the SR register's interrupt bits |
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20 | whenever scheduled in. The software ints, though not addressable via |
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21 | the various Interrupt Level functions, are maintained on a per-task |
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22 | basis, so if software manipulates them directly, things should behave as |
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23 | expected. At the time of these udpates, the Interrupt Level was only 8 |
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24 | bits, and completely supporting the global enable, software ints and the |
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25 | hardware ints would require 9 bits. When more than 8 bits are |
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26 | available, there is no reason the software interrupts could not be added |
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27 | to the Interrupt Level. |
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28 | |
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29 | While supporting the Int0 thru Int5 bits in this way doesn't seem |
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30 | wonderfully useful, it does increase the level of compliance with the |
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31 | RTEMS spec. |
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32 | |
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33 | Interrupt Level 0 corresponds to interrupts globally enabled, software |
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34 | ints enabled and Int0 thru Int5 enabled. If values other than 0 are |
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35 | supplied, they should be formulated to impose the desired bitmask. |
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36 | Interrupt priority is not a strong concept on this bsp, it is provided |
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37 | only by the order in which interrupts are checked. |
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38 | |
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39 | If during the vectoring of an interrupt, others arrive, they will all be |
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40 | processed in accordance with their ordering in SR & the peripheral |
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41 | register. For example, if while we're vectoring Int4, Int3 and Int5 are |
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42 | asserted, Int3 will be serviced before Int5. The peripheral interrupts |
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43 | are individually vectored as a consequence of Int5 being asserted, |
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44 | however Int5 is not itself vectored. Within the set of peripheral |
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45 | interrupts, bit 0 is vectored first, 31 is last. |
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46 | |
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47 | Interrupts are not nested for MIPS1 or MIPS3 processors, but are |
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48 | processed serially as possible. On an unloaded 50 task RTEMS program, |
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49 | runnning on a 12mhz MIPS1 processor, worst-case latencies of 100us were |
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50 | observed, the average being down at 60us or below. |
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51 | |
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52 | |
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53 | These features are principally a consequence of fixes and tweaks to the |
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54 | MIPS1 and MIPS3 processor support, and should be equally effective on |
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55 | both levels of MIPS processors for any of their bsp's. |
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56 | |
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57 | |
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58 | |
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59 | |
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60 | |
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